JPH08502146A - 集積回路の内部接続構造とその製造方法 - Google Patents
集積回路の内部接続構造とその製造方法Info
- Publication number
- JPH08502146A JPH08502146A JP6510197A JP51019794A JPH08502146A JP H08502146 A JPH08502146 A JP H08502146A JP 6510197 A JP6510197 A JP 6510197A JP 51019794 A JP51019794 A JP 51019794A JP H08502146 A JPH08502146 A JP H08502146A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- layer
- substrate
- insert
- assembly method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70653—Metrology techniques
- G03F7/70658—Electrical testing
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/0735—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card arranged on a flexible frame or film
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.少なくとも一つの金属回路パッドを有する集積回路との電気的コンタクトを 作るデバイスであって、 (a)支持基板と、 (b)前記基板に支持され、前記基板から突き出る少なくとも一つの挿 入構造と、 前記挿入構造は、前記基板に最も近い基本部と前記挿入構造の末端の端部を有 し、 (c)前記挿入構造の端部に配置された伝導材料層と、 (d)前記挿入構造の端部への電気的伝導路を与える前記伝導材料層と 結合する伝導手段と を備えることを特徴とするデバイス。 2.前記挿入構造の側壁は絶縁材料層を備えることを特徴とする請求項1に記載 のデバイス。 3.前記絶縁材料は、シリコン窒化物とシリコン酸化物を備えるグループから選 択されることを特徴とする請求項2に記載のデバイス。 4.複数の挿入構造が集積回路上の対応する複数の回路パッドと結合する並びで 、支持基板に配置されることを特徴とする請求項1に記載のデバイス。 5.集積回路との電気的コンタクトを作るデバイス組立方法であって、 (a)犠牲基板の表面上にマスク層を配置する工程と、 (b)前記マスク層を用いて開ロパタンをエッチングする工程と、 (c)先細りする側壁を有するウエルパタンを形成するために、開ロパ タンによって露出される前記犠牲基板をエッチングする工程と、 (d)前記ウエルの各々内に伝導材料層を配置する工程と、 (e)工程(d)で形成された構造上に絶縁材料層を配置する工程と、 (f)前記ウエルの各々内に配置された前記伝導材料の少なくとも端部 を露出するための、前記犠牲基板をエッチングで取り除く工程とを備え、 突き出る挿入構造パタンを形成することを特徴とするデバイス組立方法 。 6.前記犠牲基板はシリコンであることを特徴とする請求項5に記載のデバイス 組立方法。 7.前記シリコンは、<100>結晶オリエンテーションを有することを特徴と する請求項6に記載のデバイス組立方法。 8.前記絶縁材料は、シリコン酸化物とシリコン窒化物を備えるグループから選 択されることを特徴とすることを特徴とする請求項5に記載のデバイス組立方法 。 9.前記絶縁材料は、約1x108ダイン(dynes)/cm2の引張り応力を有するこ とを特徴とする請求項8に記載のデバイス組立方法。 10.前記絶縁材料は、マスク層を形成するために配置されることを特徴とする 請求項9に記載のデバイス組立方法。 11.前記犠牲基板は、工程(f)で全体的に取り除かれることを特徴とする請 求項5に記載のデバイス組立方法。 12.前記犠牲基板上にエッチングストップ層を形成する工程をさらに備え、 前記エッチングストップ層上に半導体層を形成し、前記エッチングストップ層 に対する前記犠牲基板を工程(f)で取り除く工程が後に続くことを特徴とする 請求項5に記載のデバイス組立方法。 13.前記エッチングストップ層を取り除く工程をさらに備えることを特徴とす る請求項12に記載のデバイス組立方法。 14.集積回路を前記半導体層上に組立てる工程をさらに備えることを特徴とす る請求項13に記載のデバイス組立方法。 15.前記エッチングストップ層は、エピタキシャル層であることを特徴とする 請求項12に記載のデバイス組立方法。 16.前記エッチングストップ層は、ゲルマニウム-ボロンシリコンであること を特徴とする請求項15に記載のデバイス組立方法。 17.前記エッチングストップ層は、約2x1020ボロン原子/cm3のドープ剤濃 度を有することを特徴とする請求項16に記載のデバイス組立方法。 18.前記半導体層は、エピタキシャル層であることを特徴とする請求項15に 記載のデバイス組立方法。 19.集積挿入構造を有する集積回路の組立て方法であって、 (a)エッチングストップ層を半導体基板上に形成する工程と、 (b)回路段階半導体層を前記エッチングストップ層上に形成する工程 と、 (c)マスク層を前記回路段階半導体層の露出表面に配置する工程と、 (d)マスク層を用いて開口パタンのエッチングを行う工程と、 (e)前記開ロパタンの下にある前記半導体基板に向かって先細りする 側壁を有するウエルパタンをエッチングする工程と、 (f)伝導材料層を前記ウエルの各々に配置する工程と、 (g)工程(f)で形成された構造上に絶縁材料層を配置する工程と、 (h)前記ウエルの各々に配置された前記伝導材料の少なくとも1端部 を露出するための、前記エッチングストップ層までの前記半導体基板をエッチン グして取り除く工程と、 それによって、挿入構造を投影するパタンを形成し、 (i)前記回路段階半導体層を露出するために、前記エッチングストッ プ層を取り除く工程と を備えることを特徴とする集積回路の組立て方法。 20.前記半導体基板はシリコンであることを特徴とする請求項19に記載の集 積回路の組立て方法。 21.前記シリコンは、<100>結晶オリエンテーションを有することを特徴 とする請求項20に記載の集積回路の組立て方法。 22.前記絶縁材料は、シリコン窒化物とシリコン酸化物を備えるグループから 選択されることを特徴とする請求項18に記載の集積回路の組立て方法。 23.前記絶縁材料は、約1x108ダイン(dynes)/cm2の引張り応力を有する ことを特徴とする請求項22に記載の集積回路の組立て方法。 24.前記絶縁材料は、前記マスク層を形成するように配置されることを特徴と する請求項23に記載の集積回路の組立て方法。 25.前記エッチングストップ層はエピタキシャル層であることを特徴とする請 求項19に記載の集積回路の組立て方法。 26.前記エッチングストップ層は、ゲルマニウム-ボロンがドープされたシリ コンであることを特徴とする請求項25に記載のデバイス組立方法。 27.前記エッチングストップ層は、約2x1020ボロン原子/cm3のドープ剤濃 度を有することを特徴とする請求項26に記載のデバイス組立方法。 28.前記回路段階半導体層は、エピタキシャル層であることを特徴とする請求 項19に記載のデバイス組立方法。 29.集積回路を前記回路段階半導体層上に組立てる工程をさらに備えることを 特徴とする請求項28に記載のデバイス組立方法。 30.複数の金属コンタクトパッドを有する集積回路を電気的に活性化させるた めのデバイスであって、 (a)支持基板と、 (b)前記基板に支持され、前記基板から前記集積回路上の複数のコン タクトパッドのうちの対応コンタクトパッドと結合した整列状態で、突き出る複 数の挿入構造と、 前記挿入構造は、前記基板に最も近い基本部と前記挿入構造の末端の端部と前 記基本部から前記端部に向かって先細りする側壁を有し、 (c)前記挿入構造の各々の端部に配置された伝導材料層と、 (d)前記挿入構造の端部へ電気的伝導路を与えるための各挿入構造の 前記伝導材料層と結合する伝導手段と、 (e)複数の挿入構造と対応する前記複数のコンタクトパッドを接続す るために、前記支持基板に結合した力の適用手段とを備え、 電気的コミュミケーションを確立することを特徴とするデバイス。 31.前記集積回路は、複数の集積回路のダイと、ウエハーの各ダイと接続する ための挿入構造を備えるデバイスを有する前記ウエハーを備えることを特徴とす る請求項30に記載のデバイス。 32.複数の金属コンタクトパッドを有する集積回路をマウントするデバイスで あって、 (a)支持基板と、 (b)前記基板によって支持され、前記基板から、前記集積回路上の複 数のコンタクトパッドのうちの対応するコンタクトパッドと結合した結合整列状 態で、突き出る複数の挿入構造と、 前記挿入構造の各々は、前記基板に最も近い基本部と、前記対応するコンタク トパッドを貫く前記挿入構造の末端にある端部と、前記基本部から前記端部に向 かって先細りする側壁を有し、 (c)前記挿入構造の各々の前記端部に配置された伝導材料層と、 (d)電気的伝導路を前記挿入構造の前記端部に与えるための、各挿入 構造の前記伝導材料層と結合する伝導手段とを備え、 前記対応するコンタクトパッドとの電気的コミュニケーションを確立するデバ イス。 33. (a)複数の開口を有する半導体基板に形成された集積回路と、 (b)前記複数の開口のそれぞれに配置され、前記複数の開口から突き 出る複数の挿入構造と、 前記挿入構造の各々は、前記基板に最も近い基本部と、前記挿入構造の末端に ある先端部とを有し、 (c)前記挿入構造の各々の前記先端部に配置された伝導材料層と、 (d)前記挿入構造の前記先端部と前記集積回路の対応ノード間の電気 的伝導路を提供するための、各挿入構造の前記伝導材料層と結合する伝導手段と を備えることを特徴とする集積回路デバイス。 34. 複数の集積回路デバイスを備える電子デバイスであって、前記複数の集 積回路デバイスの各々は、第1と第2の面と、 (a)複数の開口を有する半導体基板に形成された集積回路と、 (b)複数の開口のそれぞれに配置され、前記集積回路デバイスの前記 第1の面から突き出た複数の挿入構造と、 前記挿入構造の各々は、前記基板に最も近い基本部と、前記挿入構造の末端に ある先端部を有し、 (c)前記挿入構造の各々の前記先端部に配置された伝導材料層と、 (d)前記挿入構造の前記先端部と前記集積回路の対応ノード間に電気 的伝導路を与えるための、各挿入構造の前記伝導材料層に結合した第1の伝導手 段と、 (e)前記集積回路デバイスの前記第2の面に配置された複数のコンタ クトパッドと、 (f)前記コンタクトパッドと前記集積回路の対応ノード間に電気的伝 導路を与えるために、前記コンタクトパッドの各々と結合した第2の伝導手段と を備え、 前記複数の集積回路デバイスは、近傍の集積回路デバイスの対応コンタクトパ ッドとの結合コンタクト内に、一つの集積回路デバイスの前記挿入デバイスの前 記先端部を有し、スタックされることを特徴とするデバイス。
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US07/960,588 US5323035A (en) | 1992-10-13 | 1992-10-13 | Interconnection structure for integrated circuits and method for making same |
US07/960,588 | 1992-10-13 | ||
PCT/US1993/009709 WO1994009513A1 (en) | 1992-10-13 | 1993-10-12 | Interconnection structure for integrated circuits and method for making same |
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EP (1) | EP0664925B1 (ja) |
JP (1) | JP3699978B2 (ja) |
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-
1993
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- 1993-10-12 KR KR1019950701387A patent/KR100307082B1/ko not_active IP Right Cessation
- 1993-10-12 EP EP93923359A patent/EP0664925B1/en not_active Expired - Lifetime
- 1993-10-12 DE DE69331416T patent/DE69331416T2/de not_active Expired - Fee Related
- 1993-10-12 WO PCT/US1993/009709 patent/WO1994009513A1/en active IP Right Grant
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1994
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US6639303B2 (en) | 1996-10-29 | 2003-10-28 | Tru-Si Technolgies, Inc. | Integrated circuits and methods for their fabrication |
US6882030B2 (en) | 1996-10-29 | 2005-04-19 | Tru-Si Technologies, Inc. | Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate |
Also Published As
Publication number | Publication date |
---|---|
WO1994009513A1 (en) | 1994-04-28 |
JP3699978B2 (ja) | 2005-09-28 |
EP0664925A1 (en) | 1995-08-02 |
EP0664925A4 (en) | 1995-10-11 |
US5323035A (en) | 1994-06-21 |
DE69331416T2 (de) | 2003-04-17 |
DE69331416D1 (de) | 2002-02-07 |
KR100307082B1 (ko) | 2001-12-17 |
EP0664925B1 (en) | 2002-01-02 |
US5453404A (en) | 1995-09-26 |
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