US20010050574A1 - Interconnect for testing semiconductor dice having raised bond pads - Google Patents
Interconnect for testing semiconductor dice having raised bond pads Download PDFInfo
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- US20010050574A1 US20010050574A1 US09/213,573 US21357398A US2001050574A1 US 20010050574 A1 US20010050574 A1 US 20010050574A1 US 21357398 A US21357398 A US 21357398A US 2001050574 A1 US2001050574 A1 US 2001050574A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06733—Geometry aspects
- G01R1/06738—Geometry aspects related to tip portion
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06755—Material aspects
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
Definitions
- Known good die is a collective term that denotes unpackaged die having the same reliability as the equivalent packaged die.
- test apparatus in the form of temporary carriers suitable for testing discrete, unpackaged semiconductor dice.
- test apparatus for conducting burn-in tests for discrete die are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al. and U.S. Pat. No. 5,302,891 to Wood et al., which are assigned to Micron Technology, Inc.
- Other test apparatus for discrete die are disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No. 5,073,117 to Malhi et al., which are assigned to Texas Instruments.
- a bond pad typically includes a metal oxide layer that must be penetrated to make an ohmic contact.
- Some prior art contact structures such as probe cards, scrape the bond pads which wipes away the oxide layer and causes excessive damage to the bond pads.
- Other interconnect structures such as probe tips may pierce both the oxide layer and the metal bond pad and leave a deep gouge.
- Still other interconnect structures, such as microbumps, may not even pierce the oxide layer preventing the formation of an ohmic contact.
- Another important consideration in testing of known good die is the effect of thermal expansion during the test procedure.
- a die is heated to an elevated temperature and maintained at temperature for a prolonged period. This causes thermal expansion of the die and temporary interconnect. If the die and the temporary interconnect expand by a different amount, stress may develop at the connection point and adversely effect the electrical connection. This may also lead to excessive damage of bond pads.
- a “bumped” semiconductor die includes bond pads formed with a bump of solderable material such as a lead-tin alloy. Bumped dice are often used for flip chip bonding wherein the die is mounted face down on a substrate, such as a printed circuit board, and then attached to the substrate by welding or soldering.
- the bumps are formed as balls of material that are circular in a cross sectional plane parallel to the face of the die. The bumps typically have a diameter of from 50 ⁇ m to 100 ⁇ m.
- the sides of the bump typically bow or curve outwardly from a flat top surface. The flat top surface forms the actual region of contact with a mating electrode on the printed circuit board or other substrate.
- an improved method of testing, and an improved method for fabricating a temporary interconnect for testing unpackaged semiconductor dice having raised contact locations are provided.
- the improved method of testing includes a temporary interconnect adapted to establish an electrical connection with raised contact locations on the die without damage to the contact locations.
- the interconnect includes a substrate (e.g., silicon) having contact members formed in a pattern that matches the size and spacing of the contact locations on the die.
- the contact members on the interconnect include one or more sharpened projections. The sharpened projections are adapted to penetrate the raised contact locations on the die and to pierce any residual insulating material to establish an ohmic connection.
- the sharpened projections are formed integrally with the substrate using an etching process or using an oxidation growth process.
- the sharpened projections are formed either on a surface of the substrate, or in a recess in the substrate which is sized to retain the raised contact locations on the die.
- the sharpened projections are formed with a size and shape which permits penetration into the contact locations but with a self-limiting penetration depth.
- the sharpened projections are formed as an array of parallel elongated blades.
- the elongated blades can be formed in a variety of cross sectional configurations (e.g., triangular, rounded profile, flat tops).
- the elongated blades can be formed in a spaced array or with no spaces therebetween.
- the sharpened projections are formed on an insulating layer of the interconnect substrate and are covered with a conductive layer.
- the conductive layer can be formed as a single layer of a highly conductive metal such as aluminum or iridium, or a conductive material such as polysilicon. Conductive traces or runners are formed in electrical contact with the conductive layer to establish an electrical pathway to and from the contact members of the interconnect.
- the conductive layer for the contact members can also be formed as a stack comprising two different layers of material.
- An outer layer of the stack is preferably a metal such as platinum, which is chemically inert and provides a barrier layer that will not react with the raised material (e.g., bump) at the contact location on the die.
- the inner layer of the stack can be a metal such as aluminum or titanium which can be easily bonded to conductive traces.
- the inner layer and conductive traces can also be formed of a same material.
- the conductive layer can also be formed as a metal silicide.
- a metal silicide can be formed by depositing a silicon containing layer and a metal layer on the sharpened projections and reacting these layers to form a metal silicide. The unreacted portions of the silicon containing layer and metal layer are then etched selective to the metal silicide using a salicide process.
- a method for fabricating a temporary interconnect in accordance with the invention includes the steps of: forming a substrate; forming an array of contact members on the substrate as one or more elongated sharpened projections adapted to penetrate a raised contact location (e.g., bump) on a die to a limited penetration depth; forming an insulating layer (e.g., SiO 2 , Si 3 N 4 ) over the entire substrate including the sharpened projections; forming a conductive layer over the sharpened projections; and then forming conductive traces on the substrate in electrical communication with the conductive layer.
- the sharpened projections can be mounted within an indentation formed in the substrate that is adapted to retain the raised contact location on the die.
- interconnects Preferably a large number of interconnects are formed on a single substrate or wafer. This substrate can then be diced (e.g., saw cut) to singulate the interconnects.
- the temporary interconnect is placed in a temporary carrier (i.e., test apparatus) along with the die, and an electrical path is established between the conductive traces on the interconnect and external test circuitry associated with the test apparatus.
- FIG. 1 is a schematic cross sectional view illustrating a substrate and a mask layer during an initial process step for forming an interconnect in accordance with the invention
- FIG. 2 is a schematic cross sectional view of the substrate taken along section line 2 - 2 of FIG. 3 showing the mask layer after patterning and etching to form a mask having solid areas and openings;
- FIG. 3 is a perspective view of FIG. 2;
- FIG. 4 is a cross sectional view showing formation of the sharpened projections on the substrate using the mask layer and an etch process
- FIG. 5A is a cross sectional view taken along section line 5 A- 5 A of FIG. 6 showing the sharpened projections formed on the substrate with a triangular cross section using an anisotropic etch process;
- FIG. 5B is a cross sectional view, equivalent to FIG. 5A, showing the sharpened projections formed on the substrate with a rounded profile using an isotropic etch process;
- FIG. 5C is a cross sectional view equivalent to FIG. 5A showing the sharpened projections formed on the substrate with a truncated pyramidal cross section, using an anisotropic etch process;
- FIG. 5D is a cross sectional view equivalent to FIG. 5A showing the sharpened projections formed on the substrate using an anisotropic etch with no spaces in between the projections;
- FIG. 5E is a cross sectional view showing the sharpened projections formed on the substrate using an oxidation growth process
- FIG. 6 is a perspective view of the substrate and sharpened projections shown in FIG. 5;
- FIG. 7 is a cross sectional view of the substrate and sharpened projections showing the formation of an insulating layer over the substrate;
- FIG. 8 is a cross sectional view of the substrate and sharpened projections showing the formation of a conductive layer on the sharpened projections;
- FIG. 8A is a cross sectional view of the substrate and sharpened projections showing the formation of a conductive layer on the sharpened projections comprising a stack of two different metal layers;
- FIG. 8B is a cross sectional view of the substrate and sharpened projections showing the formation of a conductive layer on the projections formed of a metal silicide;
- FIG. 9 is a plan view of an interconnect formed in accordance with the invention.
- FIG. 10 is a cross sectional view illustrating testing of an unpackaged semiconductor die using an interconnect formed in accordance with the invention and showing the sharpened projections electrically engaging a bumped contact location of the die;
- FIG. 10A is a cross sectional view illustrating testing of an unpackaged semiconductor die in accordance with the invention using an alternate embodiment contact structure in which the sharpened projections are mounted within an indentation formed in the substrate.
- the interconnect 10 includes a substrate 12 formed of a material having a coefficient of thermal expansion (CTE) that closely matches the CTE of a silicon die.
- CTE coefficient of thermal expansion
- Suitable materials for the substrate include monocrystalline silicon, silicon-on-glass, silicon-on-sapphire, germanium, or ceramic.
- the substrate 12 includes a planar outer surface 14 having a mask layer 16 of a material such as silicon nitride (Si 3 N 4 ) formed thereon.
- a typical thickness for the mask layer 16 is about 500 ⁇ to 3000 ⁇ .
- the mask layer 16 may be formed using a suitable deposition process such as CVD.
- the mask layer 16 is patterned and etched selective to the substrate 12 to form a hard mask that includes masking blocks 18 , 20 , 24 , 26 and openings therebetween.
- this etch step may be performed using a wet or dry etch.
- a layer of silicon nitride may be etched with a pattern of openings using hot (e.g., 180° C.) phosphoric acid.
- the masking blocks 18 , 20 , 24 , 26 are elongated rectangular blocks.
- the masking blocks 18 , 20 , 24 , 26 are formed in a parallel spaced array.
- the peripheral dimensions of the array are selected to accommodate the dimensions of a raised contact location on a semiconductor die.
- the raised contact location can be a bond pad having a metal bump with a diameter of from 1 ⁇ m-500 ⁇ m.
- a parallel spaced array is merely exemplary and other configurations are possible.
- Other suitable arrangements for the masking blocks include enclosed rectangles, squares, triangles, T-shapes and X-shapes.
- elongated sharpened projections 40 , 42 , 44 , 46 are formed on the substrate 12 .
- the sharpened projections 40 , 42 , 44 , 46 can be formed using an etching process (anisotropic or isotropic), using an oxidation process, or using a deposition process.
- etching With etching, a wet or dry isotropic, or anisotropic, etch process is used to form the sharpened projections 40 , 42 , 44 , 46 as the material under the masking blocks 18 , 20 , 24 , 26 is undercut by the etchant reacting with the substrate 12 .
- the exposed substrate 12 between the masking blocks 18 , 20 , 24 , 26 etches faster than the covered substrate 12 under the blocks 18 , 20 , 24 , 26 .
- the masking blocks 18 , 20 , 24 , 26 are stripped using a wet etchant such as H 3 PO 4 that is selective to the substrate 12 .
- a wet etchant such as H 3 PO 4 that is selective to the substrate 12 .
- an etchant solution containing a mixture of KOH and H 2 O can be utilized. As shown in FIG. 5A, this results in the formation of triangular shaped sharpened projections 40 , 42 , 44 , 46 .
- This triangular shape is a function of the different etch rates of monocrystalline silicon along the different crystalline orientations.
- the surface of the substrate 12 represents the (100) planes of the silicon which etches faster than the sloped sidewalls that represent the ( 110 ) plane.
- the slope of the sidewalls of the sharpened projections is about 54° with the horizontal.
- the width of the masking blocks 18 , 20 , 24 , 26 and the parameters of the etch process are controlled to form a pointed tip 58 on each projection 40 , 42 , 44 , 46 .
- an etchant solution containing a mixture of HF, HNO 3 and H 2 O can be utilized. As shown in FIG. 5B, this results in sharpened projections 40 B, 42 B, 44 B, 46 B having a pointed tip 58 B and a rounded sidewall contour.
- the sidewalls of the sharpened projections 40 B, 42 B, 44 B, 46 B are undercut below the masking blocks 18 , 20 , 24 , 26 (FIG. 4) with a radius “r”.
- the value of the radius “r” is controlled by the etch parameters (i.e., time, temperature, concentration of etchant) and by the width of the masking blocks 18 , 20 , 24 , 26 (FIG. 4).
- FIG. 5C illustrates another embodiment wherein the sharpened projections 40 C, 42 C, 44 C, 46 C are formed with a cross section of a truncated pyramid with a flat tip 58 C.
- an anisotropic etch is used.
- the width of the masking blocks 18 , 20 , 24 , 26 and parameters of the etch process are controlled to form the flat tip 58 C.
- FIG. 5D illustrates another embodiment wherein the sharpened projections 40 D, 42 D, 44 D, 46 D are formed in a saw tooth array with no spaces between the base portions.
- an anisotropic etch is used and the process parameters, including the etch time and width of the masking blocks 18 , 20 , 24 , 26 are controlled to provide a desired height and tip 58 D to tip 58 D spacing.
- the sharpened projections can be formed using an oxidizing process.
- an oxidizing process the substrate 12 E may be subjected to an oxidizing atmosphere to oxidize exposed portions of the substrate 12 not covered by the masking blocks 18 E, 20 E, 24 E, 26 E.
- the oxidizing atmosphere may comprise steam and 02 at an elevated temperature (e.g., 950° C).
- the oxidizing atmosphere oxidizes the exposed portions of the substrate 12 and forms an oxide layer 49 (e.g., silicon dioxide).
- sharpened projections 40 E, 42 E, 44 E and 46 E are formed under the masking blocks 18 E, 20 E, 24 E, 26 E.
- the oxide layer 49 can also be stripped using a suitable wet etchant such as HF.
- the sharpened projections can also be formed by a deposition process out of a different material than the substrate 12 .
- a CVD process can be used to form the sharpened projections out of a deposited metal.
- the sharpened projections 40 , 42 , 44 , 46 are formed in an array of parallel spaced, elongated, knife edges which form a contact member 43 .
- the contact member 43 has an overall peripheral dimension adapted to accommodate the size of a raised contact location (e.g., bumped bond pad) on a semiconductor die.
- a raised contact location e.g., bumped bond pad
- multiple sharpened projections are formed for each contact member 43 , it is to be understood that a single sharpened projection per contact member 43 would also be suitable.
- the sharpened projections 40 , 42 , 44 , 46 project from a surface 56 of the substrate 12 and include pointed tips 58 and bases 60 .
- the bases 60 of adjacent sharpened projections 40 , 42 , 44 , 46 are spaced from one another a distance sufficient to define a penetration stop plane 62 there between.
- the function of the penetration stop plane 62 will be apparent from the continuing discussion.
- Example spacing between bases 60 would be 10 ⁇ m, while an example length of the bases 60 and tips 58 would be from 3 to 10 ⁇ m.
- each sharpened projections 40 , 42 , 44 , 46 is preferably about one-thousandth ( ⁇ fraction (1/1000) ⁇ ) to one-quarter ( ⁇ fraction ( 1 / 4 ) ⁇ ) the diameter of a bumped bond pad on a semiconductor die. This height is selected to allow good electrical contact and at the same time provide minimum damage to raised contact locations (e.g., bumps) on dice that are typically tested using the interconnect 10 and then used for flip chip bonding. As an example, this projecting distance of the sharpened projections 40 , 42 , 44 , 46 , from the substrate 12 will be on the order of 1 to 3 ⁇ m. Subsequent to formation of the sharpened projections 40 , 42 , 44 , 46 , additional etching may be used to further sharpen the tips 58 .
- an insulating layer 64 is formed over the entire substrate 12 including the contact member 43 .
- the insulating layer 64 can be formed of a material such as SiO 2 by exposing the substrate 12 to an oxidizing atmosphere for a short time or by using a CVD process.
- the insulating layer 64 can also be formed of a material such as Si 3 N 4 .
- a conductive layer 66 is formed on the insulating layer 64 and in an area of the substrate overlying each contact member 43 .
- the conductive layer 66 can be formed of a highly conductive metal, such as aluminum (Al), iridium (Ir), copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo) or alloys of these metals.
- a suitable metallization process to form the conductive layer 66 can include the steps of deposition (e.g., sputter, CVD), patterning (e.g., photopatterning) and etching (e.g., wet or dry etch).
- the conductive layer 66 can also be formed of a conductive material such as doped polysilicon.
- a conductive material such as doped polysilicon.
- an LPCVD process can be used to form a conductive layer 66 out of polysilicon doped with phosphorus.
- a conductive layer 66 A can also be formed as a stack of two materials.
- the stacked conductive layer 66 A includes a barrier layer 68 and a bonding layer 70 .
- the barrier layer 68 is formulated to prevent formation of an oxide layer that would change the resistivity of the contact member 43 .
- the barrier layer 68 is formulated to prevent reaction of the conductive layer 66 A with the contact location (e.g., metal bump 88 —FIG. 10) on the die and prevent the diffusion of impurities from the contact location on the die to the bonding layer 70 and vice versa.
- the barrier layer 68 is preferably a metal that will not easily form a “permanent” or “chemical” bond with a raised metal contact location on the die even under a large mechanical force (e.g., 10 lb./interconnect) and at high temperatures. In addition, this metal must be chemically stable (i.e., non reactive) for temperatures up to about 200° C.
- the barrier layer 68 can be formed of a metal such as platinum (Pt), titanium (Ti) or a titanium alloy (e.g., TiN, TiW).
- the bonding layer 70 is formulated to provide a good mechanical bond with conductive traces 72 A that are subsequently formed on the substrate 12 out of a highly conductive material.
- the bonding layer 70 can be formed of aluminum (Al), tungsten (W) or titanium (Ti).
- the bonding layer 70 can be formed of a same material as the conductive traces 72 A using a single masking step.
- a conductive layer 66 B can also be formed by depositing a silicon containing layer 76 (e.g., polysilicon, amorphous silicon) and a metal layer 78 , and reacting these layers to form a metal silicide 78 A.
- a silicon containing layer 76 e.g., polysilicon, amorphous silicon
- the metal layer 78 is formed of a metal that will react with the silicon containing layer 76 to form a metal silicide.
- Suitable metals include the refractory metals, such as titanium (Ti), tungsten (W), tantalum (Ta), platinum (Pt) and molybdenum (Mo).
- silicides of these metals WSi 2 , TaSi 2 , MoSi 2 , PtSi 2 and TiSi 2
- Other suitable metals include cobalt (Co), nickel (Ni), molybdenum (Mo), copper (Cu), gold (Au) and iridium (Ir).
- a sintering process is performed in which the metal layer 78 is heated and reacts with the silicon containing layer 76 to form a silicide layer 78 A.
- This type of sintering process is also known in the art as silicide sintering.
- Such a sintering step can be performed by heating the silicon containing layer 76 and metal layer 78 to a temperature of about 650° to 820° C. for typical thicknesses in thousands of angstroms (e.g., 2000 ⁇ -3000 ⁇ ).
- This sintering process can be performed in one single step or using multiple temperature steps.
- a silicide layer 78 A forms at the interface of the metal layer 78 and the silicon containing layer 76 .
- the unreacted portions of the metal layer 78 and the silicon containing layer 76 are removed while the silicide layer 78 A is left intact.
- This process is known in the art as a salicide process. This can be done by etching the metal layer 78 and silicon containing layer 76 selective to the silicide layer 78 A.
- the unreacted titanium can be removed with a wet etchant such as a solution of ammonia and hydrogen peroxide, or a H 2 SO 4 /H 2 O 2 mixture, that will attack the metal layer 78 and not the silicide layer 78 A.
- a dry etch process with an etchant species such as Cl 2 or BCl 3 can be used to etch the metal layer 78 selective to the silicide layer 78 A.
- a wet etchant such as an HF:HNO 3 :H 2 O acid mixture (typical ratios of 1:10:10) can be used to remove the unreacted silicon.
- a wet isotropic etchant can also be used for this purpose.
- the silicon containing layer 76 can be etched selective to the silicide layer 78 A using a dry etch process and an etchant such as NF 3 at low pressures (typically 30 m torr) or CL 2 and HBr at 130 m torr.
- the resistivity of the silicide layer 78 A may be lowered using an annealing process. This may be accomplished by heating the substrate 10 and silicide layer 78 A to a temperature of between about 780° C. to 850° C. for several minutes.
- FIG. 9 is a plan view of the completed interconnect 10 with a semiconductor die 85 superimposed.
- conductive traces 72 are formed on the interconnect 10 in electrical communication with the conductive layer 66 (or 66 A-FIG. 8A, 66 B-FIG. 8B).
- the conductive traces 72 extend to an edge of the interconnect 10 and include bond sites 73 .
- the bond sites 73 are used for wire bonding a bond wire 74 (FIG. 10) to provide an electrical pathway from external test circuitry to the conductive layer 66 .
- This electrical pathway can also be established using a mechanical connectors 74 M (e.g., slide contacts, clip contacts) adapted to provide a temporary electrical connection with the conductive traces 72 .
- a mechanical connectors 74 M e.g., slide contacts, clip contacts
- FIG. 10 a cross section of the interconnect 10 during testing of a semiconductor die 85 is shown.
- the semiconductor die 85 is an unpackaged die having a bond pad 86 formed with a metal bump 88 .
- the interconnect 10 and die 85 are mounted within a temporary carrier suitable for testing discrete unpackaged semiconductor die.
- a temporary carrier is described in previously cited U.S. Pat. No. 5,302,891 entitled “Discrete Die Burn-In For Non-Packaged Die”, which is incorporated herein by reference.
- Other suitable carriers are disclosed in related application Ser. No. 08/345,064 filed Nov. 14, 1994 and entitled “Carrier For Testing An Unpackaged Semiconductor Die”, which is also incorporated herein by reference.
- With such a carrier the interconnect 10 is used to establish a temporary electrical connection with the die 85 .
- the interconnect 10 and die 85 are temporarily biased together by the carrier and are separated following the test procedure.
- the interconnect 10 is mounted within the carrier and wire 74 is wire bonded to the bond sites 73 (FIG. 9). (Alternately mechanical connectors 74 M-FIG. 10 can be used.) This places the wire 74 in electrical communication with the conductive layer 66 at one end. An opposite end of the wire 74 is placed in electrical communication with external connectors (not shown) located on the carrier. This can also be accomplished by wire bonding.
- the external connectors on the carrier are connectable to external test circuitry.
- the test circuitry is adapted to generate test signals for testing the operability of the integrated circuits formed on the die 85 .
- the carrier includes provision for aligning the die 85 and interconnect 10 and biasing the die 85 and interconnect 10 together.
- the interconnect 10 and die 85 are biased together such that the sharpened projections 40 , 42 , 44 , 46 penetrate into the metal bump 88 .
- the sharpened projections 40 , 42 , 44 , 46 completely penetrate any oxide layer covering the bump 88 to establish an ohmic connection.
- a penetration depth of the sharpened projections 40 , 42 , 44 , 46 into the bump 88 is limited by the stop plane 62 (FIG. 6) provided by the flat top surface of the conductive layer 66 .
- the sharpened projections 40 , 42 , 44 , 46 are dimensioned to penetrate to a predetermined depth that is less than the height of the bump 88 .
- the sharpened projections Preferably have a height which is much less than the diameter of the bump 88 (e.g., ⁇ fraction (1/100) ⁇ ) to prevent excessive surface damage and spreading of the bump 88 .
- the bumps 88 are typically used later for flip chip bonding the die 85 to a printed circuit board. If damage to the bump 88 is minimized during testing, the bump 88 will not require a subsequent reflow process.
- the interconnect 10 ′ functions substantially the same as interconnect 10 but includes an indentation 90 formed in the substrate 12 ′ for retaining the bump 88 .
- the indentation 90 can be formed during formation of the sharpened projections for the contact member 43 ′ using an etching process.
- the same etch mask used to form the sharpened projections can also include an opening for forming the indentation 90 .
- the indentation 90 is sized to abut and retain the bump 88 during the testing procedure. This centers the bump 88 over the contact member 43 ′.
- the indentation 90 helps to prevent spreading of the bump 88 due to the penetration of the sharpened projections of the contact member 43 ′.
- an insulating layer 64 ′ is formed on the substrate 12 ′ and a conductive layer 66 ′ is formed over the contact member 43 ′ substantially as previously described.
- the conductive layer 66 ′ can be formed to overlap the indentation 90 as shown in FIG. 10A.
- the conductive layer 66 ′ can be formed as a stack of dissimilar metals (e.g., FIG. 8A), as a silicide (e.g., FIG. 8B) or as a layer of polysilicon.
- Conductive traces 72 ′ equivalent to traces 72 (FIG. 9) are formed on the substrate 12 ′ in electrical communication with the conductive layer 66 ′. Wire bonding or mechanical connectors, as previously described, can then be used to establish an electrical pathway to the conductive layer 66 ′.
- the invention provides an improved method for testing a discrete, unpackaged semiconductor die having raised bond pads and an improved method for forming an interconnect for testing this type of die.
- preferred materials have been described, it is to be understood that other materials may also be utilized.
- the method of the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.
Abstract
Description
- Because of a trend towards multi-chip modules, semiconductor manufacturers are required to supply unpackaged dice that have been tested and certified as known good die (KGD). Known good die is a collective term that denotes unpackaged die having the same reliability as the equivalent packaged die.
- The need for known good die has led to the development of test apparatus in the form of temporary carriers suitable for testing discrete, unpackaged semiconductor dice. As an example, test apparatus for conducting burn-in tests for discrete die are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al. and U.S. Pat. No. 5,302,891 to Wood et al., which are assigned to Micron Technology, Inc. Other test apparatus for discrete die are disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No. 5,073,117 to Malhi et al., which are assigned to Texas Instruments.
- With this type of test apparatus, a non-permanent electrical connection must be made between contact locations on the die, such as bond pads, and external test circuitry associated with the test apparatus. The bond pads provide a connection point for testing the integrated circuitry formed on the die.
- In making this temporary electrical connection, it is desirable to effect a connection that causes as little damage as possible to the bond pad. If the temporary connection to a bond pad damages the pad, the entire die may be rendered as unusable. This is difficult to accomplish because the connection must also produce a low resistance or ohmic contact with the bond pad. A bond pad typically includes a metal oxide layer that must be penetrated to make an ohmic contact.
- Some prior art contact structures, such as probe cards, scrape the bond pads which wipes away the oxide layer and causes excessive damage to the bond pads. Other interconnect structures such as probe tips may pierce both the oxide layer and the metal bond pad and leave a deep gouge. Still other interconnect structures, such as microbumps, may not even pierce the oxide layer preventing the formation of an ohmic contact.
- Another important consideration in testing of known good die is the effect of thermal expansion during the test procedure. As an example, during burn-in testing, a die is heated to an elevated temperature and maintained at temperature for a prolonged period. This causes thermal expansion of the die and temporary interconnect. If the die and the temporary interconnect expand by a different amount, stress may develop at the connection point and adversely effect the electrical connection. This may also lead to excessive damage of bond pads.
- One type of semiconductor dice having a raised topology is referred to as a “bumped” die. A “bumped” semiconductor die includes bond pads formed with a bump of solderable material such as a lead-tin alloy. Bumped dice are often used for flip chip bonding wherein the die is mounted face down on a substrate, such as a printed circuit board, and then attached to the substrate by welding or soldering. Typically the bumps are formed as balls of material that are circular in a cross sectional plane parallel to the face of the die. The bumps typically have a diameter of from 50 μm to 100 μm. The sides of the bump typically bow or curve outwardly from a flat top surface. The flat top surface forms the actual region of contact with a mating electrode on the printed circuit board or other substrate.
- In the past, following testing of a bumped die, it has been necessary to reflow the bumps, which are typically damaged by the test procedure. This is an additional process step which adds to the expense and complexity of the testing process. Furthermore, it requires heating the tested die which can adversely affect the integrated circuitry formed on the die.
- In view of the need in the art for improved methods for testing unpackaged, bumped, semiconductor dice, it is an object of the present invention to provide an improved method of testing unpackaged semiconductor dice having raised or bumped bond pads.
- It is a further object of the present invention to provide an improved method for forming a temporary interconnect adapted to test semiconductor die having raised or bumped bond pads.
- It is a further object of the present invention to provide an improved method for fabricating temporary interconnects for bumped semiconductor dice that uses semiconductor manufacturing techniques and that provides an improved contact structure.
- Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.
- In accordance with the present invention, an improved method of testing, and an improved method for fabricating a temporary interconnect for testing unpackaged semiconductor dice having raised contact locations (e.g., bumped bond pads) are provided. The improved method of testing includes a temporary interconnect adapted to establish an electrical connection with raised contact locations on the die without damage to the contact locations. The interconnect includes a substrate (e.g., silicon) having contact members formed in a pattern that matches the size and spacing of the contact locations on the die. The contact members on the interconnect include one or more sharpened projections. The sharpened projections are adapted to penetrate the raised contact locations on the die and to pierce any residual insulating material to establish an ohmic connection.
- The sharpened projections are formed integrally with the substrate using an etching process or using an oxidation growth process. The sharpened projections are formed either on a surface of the substrate, or in a recess in the substrate which is sized to retain the raised contact locations on the die. In addition, the sharpened projections are formed with a size and shape which permits penetration into the contact locations but with a self-limiting penetration depth. In an illustrative embodiment, the sharpened projections are formed as an array of parallel elongated blades. Depending on the method of formation, the elongated blades can be formed in a variety of cross sectional configurations (e.g., triangular, rounded profile, flat tops). In addition, the elongated blades can be formed in a spaced array or with no spaces therebetween.
- The sharpened projections are formed on an insulating layer of the interconnect substrate and are covered with a conductive layer. The conductive layer can be formed as a single layer of a highly conductive metal such as aluminum or iridium, or a conductive material such as polysilicon. Conductive traces or runners are formed in electrical contact with the conductive layer to establish an electrical pathway to and from the contact members of the interconnect.
- The conductive layer for the contact members can also be formed as a stack comprising two different layers of material. An outer layer of the stack is preferably a metal such as platinum, which is chemically inert and provides a barrier layer that will not react with the raised material (e.g., bump) at the contact location on the die. The inner layer of the stack can be a metal such as aluminum or titanium which can be easily bonded to conductive traces. The inner layer and conductive traces can also be formed of a same material.
- The conductive layer can also be formed as a metal silicide. A metal silicide can be formed by depositing a silicon containing layer and a metal layer on the sharpened projections and reacting these layers to form a metal silicide. The unreacted portions of the silicon containing layer and metal layer are then etched selective to the metal silicide using a salicide process.
- A method for fabricating a temporary interconnect in accordance with the invention, includes the steps of: forming a substrate; forming an array of contact members on the substrate as one or more elongated sharpened projections adapted to penetrate a raised contact location (e.g., bump) on a die to a limited penetration depth; forming an insulating layer (e.g., SiO2, Si3N4) over the entire substrate including the sharpened projections; forming a conductive layer over the sharpened projections; and then forming conductive traces on the substrate in electrical communication with the conductive layer. Optionally, the sharpened projections can be mounted within an indentation formed in the substrate that is adapted to retain the raised contact location on the die.
- Preferably a large number of interconnects are formed on a single substrate or wafer. This substrate can then be diced (e.g., saw cut) to singulate the interconnects. In use, the temporary interconnect is placed in a temporary carrier (i.e., test apparatus) along with the die, and an electrical path is established between the conductive traces on the interconnect and external test circuitry associated with the test apparatus.
- FIG. 1 is a schematic cross sectional view illustrating a substrate and a mask layer during an initial process step for forming an interconnect in accordance with the invention;
- FIG. 2 is a schematic cross sectional view of the substrate taken along section line2-2 of FIG. 3 showing the mask layer after patterning and etching to form a mask having solid areas and openings;
- FIG. 3 is a perspective view of FIG. 2;
- FIG. 4 is a cross sectional view showing formation of the sharpened projections on the substrate using the mask layer and an etch process;
- FIG. 5A is a cross sectional view taken along section line5A-5A of FIG. 6 showing the sharpened projections formed on the substrate with a triangular cross section using an anisotropic etch process;
- FIG. 5B is a cross sectional view, equivalent to FIG. 5A, showing the sharpened projections formed on the substrate with a rounded profile using an isotropic etch process;
- FIG. 5C is a cross sectional view equivalent to FIG. 5A showing the sharpened projections formed on the substrate with a truncated pyramidal cross section, using an anisotropic etch process;
- FIG. 5D is a cross sectional view equivalent to FIG. 5A showing the sharpened projections formed on the substrate using an anisotropic etch with no spaces in between the projections;
- FIG. 5E is a cross sectional view showing the sharpened projections formed on the substrate using an oxidation growth process;
- FIG. 6 is a perspective view of the substrate and sharpened projections shown in FIG. 5;
- FIG. 7 is a cross sectional view of the substrate and sharpened projections showing the formation of an insulating layer over the substrate;
- FIG. 8 is a cross sectional view of the substrate and sharpened projections showing the formation of a conductive layer on the sharpened projections;
- FIG. 8A is a cross sectional view of the substrate and sharpened projections showing the formation of a conductive layer on the sharpened projections comprising a stack of two different metal layers;
- FIG. 8B is a cross sectional view of the substrate and sharpened projections showing the formation of a conductive layer on the projections formed of a metal silicide;
- FIG. 9 is a plan view of an interconnect formed in accordance with the invention;
- FIG. 10 is a cross sectional view illustrating testing of an unpackaged semiconductor die using an interconnect formed in accordance with the invention and showing the sharpened projections electrically engaging a bumped contact location of the die; and
- FIG. 10A is a cross sectional view illustrating testing of an unpackaged semiconductor die in accordance with the invention using an alternate embodiment contact structure in which the sharpened projections are mounted within an indentation formed in the substrate.
- Referring now to FIG. 1, a process for forming an
interconnect 10 for testing unpackaged semiconductor dice having raised contact locations, such as bumped bond pads, is shown. Theinterconnect 10 includes asubstrate 12 formed of a material having a coefficient of thermal expansion (CTE) that closely matches the CTE of a silicon die. Suitable materials for the substrate include monocrystalline silicon, silicon-on-glass, silicon-on-sapphire, germanium, or ceramic. - The
substrate 12 includes a planarouter surface 14 having amask layer 16 of a material such as silicon nitride (Si3N4) formed thereon. A typical thickness for themask layer 16 is about 500 Å to 3000 Å. Themask layer 16 may be formed using a suitable deposition process such as CVD. - Next, as shown in FIG. 2, the
mask layer 16 is patterned and etched selective to thesubstrate 12 to form a hard mask that includes masking blocks 18, 20, 24, 26 and openings therebetween. Depending on the materials used for themask layer 16, this etch step may be performed using a wet or dry etch. As an example, a layer of silicon nitride may be etched with a pattern of openings using hot (e.g., 180° C.) phosphoric acid. - As shown in the perspective view of FIG. 3, the masking blocks18, 20, 24, 26 are elongated rectangular blocks. In addition, the masking blocks 18, 20, 24, 26 are formed in a parallel spaced array. The peripheral dimensions of the array are selected to accommodate the dimensions of a raised contact location on a semiconductor die. As an example, the raised contact location can be a bond pad having a metal bump with a diameter of from 1 μm-500 μm. As is apparent however, such a parallel spaced array is merely exemplary and other configurations are possible. Other suitable arrangements for the masking blocks include enclosed rectangles, squares, triangles, T-shapes and X-shapes.
- Next, as shown in FIG. 4, elongated sharpened
projections substrate 12. The sharpenedprojections - With etching, a wet or dry isotropic, or anisotropic, etch process is used to form the sharpened
projections substrate 12. In other words, the exposedsubstrate 12 between the masking blocks 18, 20, 24, 26 etches faster than the coveredsubstrate 12 under theblocks - Following the etching process the masking blocks18, 20, 24, 26 are stripped using a wet etchant such as H3PO4 that is selective to the
substrate 12. For an anisotropic etch, in which the etch rate is different in different directions, an etchant solution containing a mixture of KOH and H2O can be utilized. As shown in FIG. 5A, this results in the formation of triangular shaped sharpenedprojections substrate 12 represents the (100) planes of the silicon which etches faster than the sloped sidewalls that represent the (110) plane. For asilicon substrate 12, the slope of the sidewalls of the sharpened projections is about 54° with the horizontal. For forming the triangular shaped sharpenedprojections pointed tip 58 on eachprojection - For an isotropic etch, in which the etch rate is the same in all directions, an etchant solution containing a mixture of HF, HNO3 and H2O can be utilized. As shown in FIG. 5B, this results in sharpened
projections tip 58B and a rounded sidewall contour. In this embodiment the sidewalls of the sharpenedprojections - FIG. 5C illustrates another embodiment wherein the sharpened
projections 40C, 42C, 44C, 46C are formed with a cross section of a truncated pyramid with aflat tip 58C. In this embodiment an anisotropic etch is used. In addition, the width of the masking blocks 18, 20, 24, 26 and parameters of the etch process (e.g., time, temperature, concentration of etchant) are controlled to form theflat tip 58C. - FIG. 5D illustrates another embodiment wherein the sharpened
projections - Alternately, in place of an isotropic or anisotropic etch process, the sharpened projections can be formed using an oxidizing process. This is shown in FIG. 5E. With an oxidizing process the
substrate 12E may be subjected to an oxidizing atmosphere to oxidize exposed portions of thesubstrate 12 not covered by the masking blocks 18E, 20E, 24E, 26E. As an example, the oxidizing atmosphere may comprise steam and 02 at an elevated temperature (e.g., 950° C). The oxidizing atmosphere oxidizes the exposed portions of thesubstrate 12 and forms an oxide layer 49 (e.g., silicon dioxide). At the same time, sharpenedprojections 40E, 42E, 44E and 46E are formed under the masking blocks 18E, 20E, 24E, 26E. With an oxidizing process, theoxide layer 49 can also be stripped using a suitable wet etchant such as HF. - The sharpened projections can also be formed by a deposition process out of a different material than the
substrate 12. As an example, a CVD process can be used to form the sharpened projections out of a deposited metal. - Referring now to FIG. 6, which represents the structure after completion of the process illustrated by FIG. 5A, the sharpened
projections contact member 43. Thecontact member 43 has an overall peripheral dimension adapted to accommodate the size of a raised contact location (e.g., bumped bond pad) on a semiconductor die. Although multiple sharpened projections are formed for eachcontact member 43, it is to be understood that a single sharpened projection percontact member 43 would also be suitable. - The sharpened
projections surface 56 of thesubstrate 12 and include pointedtips 58 and bases 60. Thebases 60 of adjacent sharpenedprojections penetration stop plane 62 there between. The function of thepenetration stop plane 62 will be apparent from the continuing discussion. Example spacing betweenbases 60 would be 10 μm, while an example length of thebases 60 andtips 58 would be from 3 to 10 μm. The height of each sharpenedprojections interconnect 10 and then used for flip chip bonding. As an example, this projecting distance of the sharpenedprojections substrate 12 will be on the order of 1 to 3 μm. Subsequent to formation of the sharpenedprojections tips 58. - Following the formation of the sharpened
projections layer 64 is formed over theentire substrate 12 including thecontact member 43. The insulatinglayer 64 can be formed of a material such as SiO2 by exposing thesubstrate 12 to an oxidizing atmosphere for a short time or by using a CVD process. The insulatinglayer 64 can also be formed of a material such as Si3N4. - Next, as shown in FIG. 8, a
conductive layer 66 is formed on the insulatinglayer 64 and in an area of the substrate overlying eachcontact member 43. Theconductive layer 66 can be formed of a highly conductive metal, such as aluminum (Al), iridium (Ir), copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo) or alloys of these metals. A suitable metallization process to form theconductive layer 66 can include the steps of deposition (e.g., sputter, CVD), patterning (e.g., photopatterning) and etching (e.g., wet or dry etch). - The
conductive layer 66 can also be formed of a conductive material such as doped polysilicon. As an example, an LPCVD process can be used to form aconductive layer 66 out of polysilicon doped with phosphorus. - As shown in FIG. 8A, a
conductive layer 66A can also be formed as a stack of two materials. The stackedconductive layer 66A includes abarrier layer 68 and a bonding layer 70. Thebarrier layer 68 is formulated to prevent formation of an oxide layer that would change the resistivity of thecontact member 43. In addition, thebarrier layer 68 is formulated to prevent reaction of theconductive layer 66A with the contact location (e.g.,metal bump 88—FIG. 10) on the die and prevent the diffusion of impurities from the contact location on the die to the bonding layer 70 and vice versa. - The
barrier layer 68 is preferably a metal that will not easily form a “permanent” or “chemical” bond with a raised metal contact location on the die even under a large mechanical force (e.g., 10 lb./interconnect) and at high temperatures. In addition, this metal must be chemically stable (i.e., non reactive) for temperatures up to about 200° C. By way of example, thebarrier layer 68 can be formed of a metal such as platinum (Pt), titanium (Ti) or a titanium alloy (e.g., TiN, TiW). - The bonding layer70 is formulated to provide a good mechanical bond with
conductive traces 72A that are subsequently formed on thesubstrate 12 out of a highly conductive material. By way of example, the bonding layer 70 can be formed of aluminum (Al), tungsten (W) or titanium (Ti). In some applications the bonding layer 70 can be formed of a same material as theconductive traces 72A using a single masking step. - As shown in FIG. 8B, a
conductive layer 66B can also be formed by depositing a silicon containing layer 76 (e.g., polysilicon, amorphous silicon) and ametal layer 78, and reacting these layers to form ametal silicide 78A. A typical thickness of thesilicon containing layer 76 would be from about 500 Å to 3000 Å - The
metal layer 78 is formed of a metal that will react with thesilicon containing layer 76 to form a metal silicide. Suitable metals include the refractory metals, such as titanium (Ti), tungsten (W), tantalum (Ta), platinum (Pt) and molybdenum (Mo). In general, silicides of these metals (WSi2, TaSi2, MoSi2, PtSi2 and TiSi2) are formed by alloying with a silicon surface. Other suitable metals include cobalt (Co), nickel (Ni), molybdenum (Mo), copper (Cu), gold (Au) and iridium (Ir). - Following deposition of the
metal layer 78, a sintering process is performed in which themetal layer 78 is heated and reacts with thesilicon containing layer 76 to form asilicide layer 78A. This type of sintering process is also known in the art as silicide sintering. Such a sintering step can be performed by heating thesilicon containing layer 76 andmetal layer 78 to a temperature of about 650° to 820° C. for typical thicknesses in thousands of angstroms (e.g., 2000 Å-3000 Å). This sintering process can be performed in one single step or using multiple temperature steps. Asilicide layer 78A forms at the interface of themetal layer 78 and thesilicon containing layer 76. - The unreacted portions of the
metal layer 78 and thesilicon containing layer 76 are removed while thesilicide layer 78A is left intact. This process is known in the art as a salicide process. This can be done by etching themetal layer 78 andsilicon containing layer 76 selective to thesilicide layer 78A. By way of example, for a TiSi2 silicide layer 78A, the unreacted titanium can be removed with a wet etchant such as a solution of ammonia and hydrogen peroxide, or a H2SO4/H2O2 mixture, that will attack themetal layer 78 and not thesilicide layer 78A. Alternately, a dry etch process with an etchant species such as Cl2 or BCl3 can be used to etch themetal layer 78 selective to thesilicide layer 78A. - For etching the unreacted portion of the
silicon containing layer 76 selective to thesilicide layer 78A, a wet etchant such as an HF:HNO3:H2O acid mixture (typical ratios of 1:10:10) can be used to remove the unreacted silicon. A wet isotropic etchant can also be used for this purpose. Alternately thesilicon containing layer 76 can be etched selective to thesilicide layer 78A using a dry etch process and an etchant such as NF3 at low pressures (typically 30 m torr) or CL2 and HBr at 130 m torr. - Following formation of the
silicide layer 78A, the resistivity of thesilicide layer 78A may be lowered using an annealing process. This may be accomplished by heating thesubstrate 10 andsilicide layer 78A to a temperature of between about 780° C. to 850° C. for several minutes. - FIG. 9 is a plan view of the completed
interconnect 10 with asemiconductor die 85 superimposed. As shown in FIG. 9, conductive traces 72 are formed on theinterconnect 10 in electrical communication with the conductive layer 66 (or 66A-FIG. 8A, 66B-FIG. 8B). As also shown in FIG. 9, the conductive traces 72 extend to an edge of theinterconnect 10 and includebond sites 73. Thebond sites 73 are used for wire bonding a bond wire 74 (FIG. 10) to provide an electrical pathway from external test circuitry to theconductive layer 66. This electrical pathway can also be established using amechanical connectors 74M (e.g., slide contacts, clip contacts) adapted to provide a temporary electrical connection with the conductive traces 72. - Referring now to FIG. 10, a cross section of the
interconnect 10 during testing of asemiconductor die 85 is shown. The semiconductor die 85 is an unpackaged die having abond pad 86 formed with ametal bump 88. For testing thedie 85, theinterconnect 10 and die 85 are mounted within a temporary carrier suitable for testing discrete unpackaged semiconductor die. By way of example, a temporary carrier is described in previously cited U.S. Pat. No. 5,302,891 entitled “Discrete Die Burn-In For Non-Packaged Die”, which is incorporated herein by reference. Other suitable carriers are disclosed in related application Ser. No. 08/345,064 filed Nov. 14, 1994 and entitled “Carrier For Testing An Unpackaged Semiconductor Die”, which is also incorporated herein by reference. With such a carrier theinterconnect 10 is used to establish a temporary electrical connection with thedie 85. Theinterconnect 10 and die 85 are temporarily biased together by the carrier and are separated following the test procedure. - Initially, the
interconnect 10 is mounted within the carrier andwire 74 is wire bonded to the bond sites 73 (FIG. 9). (Alternatelymechanical connectors 74M-FIG. 10 can be used.) This places thewire 74 in electrical communication with theconductive layer 66 at one end. An opposite end of thewire 74 is placed in electrical communication with external connectors (not shown) located on the carrier. This can also be accomplished by wire bonding. - The external connectors on the carrier are connectable to external test circuitry. The test circuitry is adapted to generate test signals for testing the operability of the integrated circuits formed on the
die 85. The carrier includes provision for aligning thedie 85 andinterconnect 10 and biasing thedie 85 andinterconnect 10 together. - The
interconnect 10 and die 85 are biased together such that the sharpenedprojections metal bump 88. The sharpenedprojections bump 88 to establish an ohmic connection. At the same time, a penetration depth of the sharpenedprojections bump 88 is limited by the stop plane 62 (FIG. 6) provided by the flat top surface of theconductive layer 66. - Additionally, the sharpened
projections bump 88. Preferably the sharpened projections have a height which is much less than the diameter of the bump 88 (e.g., {fraction (1/100)}) to prevent excessive surface damage and spreading of thebump 88. Thebumps 88 are typically used later for flip chip bonding thedie 85 to a printed circuit board. If damage to thebump 88 is minimized during testing, thebump 88 will not require a subsequent reflow process. - Referring now to FIG. 10A, an
alternate embodiment interconnect 10′ is shown. Theinterconnect 10′ functions substantially the same asinterconnect 10 but includes anindentation 90 formed in thesubstrate 12′ for retaining thebump 88. Theindentation 90 can be formed during formation of the sharpened projections for thecontact member 43′ using an etching process. The same etch mask used to form the sharpened projections can also include an opening for forming theindentation 90. Theindentation 90 is sized to abut and retain thebump 88 during the testing procedure. This centers thebump 88 over thecontact member 43′. In addition theindentation 90 helps to prevent spreading of thebump 88 due to the penetration of the sharpened projections of thecontact member 43′. - Following formation of the
indentation 90 andcontact member 43′ an insulatinglayer 64′ is formed on thesubstrate 12′ and aconductive layer 66′ is formed over thecontact member 43′ substantially as previously described. Theconductive layer 66′ can be formed to overlap theindentation 90 as shown in FIG. 10A. In addition theconductive layer 66′ can be formed as a stack of dissimilar metals (e.g., FIG. 8A), as a silicide (e.g., FIG. 8B) or as a layer of polysilicon. Conductive traces 72′ equivalent to traces 72 (FIG. 9) are formed on thesubstrate 12′ in electrical communication with theconductive layer 66′. Wire bonding or mechanical connectors, as previously described, can then be used to establish an electrical pathway to theconductive layer 66′. - Thus the invention provides an improved method for testing a discrete, unpackaged semiconductor die having raised bond pads and an improved method for forming an interconnect for testing this type of die. Although preferred materials have been described, it is to be understood that other materials may also be utilized. Furthermore, although the method of the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.
Claims (41)
Priority Applications (1)
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US09/213,573 US6414506B2 (en) | 1993-09-03 | 1998-12-17 | Interconnect for testing semiconductor dice having raised bond pads |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
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US08/116,394 US5326428A (en) | 1993-09-03 | 1993-09-03 | Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability |
US08/206,747 US5523697A (en) | 1993-09-03 | 1994-03-04 | Testing apparatus for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof |
US08/335,267 US5483741A (en) | 1993-09-03 | 1994-11-07 | Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice |
US08/369,067 US5592736A (en) | 1993-09-03 | 1995-01-05 | Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads |
US68816996A | 1996-09-23 | 1996-09-23 | |
US09/213,573 US6414506B2 (en) | 1993-09-03 | 1998-12-17 | Interconnect for testing semiconductor dice having raised bond pads |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170315169A1 (en) * | 2010-09-07 | 2017-11-02 | Johnstech International Corporation | Electrically Conductive Pins For Microcircuit Tester |
US20170363659A1 (en) * | 2016-06-17 | 2017-12-21 | International Business Machines Corporation | Integrated self-coining probe |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6310484B1 (en) * | 1996-04-01 | 2001-10-30 | Micron Technology, Inc. | Semiconductor test interconnect with variable flexure contacts |
US6369600B2 (en) | 1998-07-06 | 2002-04-09 | Micron Technology, Inc. | Test carrier for testing semiconductor components including interconnect with support members for preventing component flexure |
US6980017B1 (en) * | 1999-03-10 | 2005-12-27 | Micron Technology, Inc. | Test interconnect for bumped semiconductor components and method of fabrication |
US6581446B1 (en) * | 1999-04-13 | 2003-06-24 | The University Of Houston | Determination of adhesion strength of HVOF coating by spherical indentation |
US6759858B2 (en) * | 1999-10-20 | 2004-07-06 | Intel Corporation | Integrated circuit test probe having ridge contact |
US6380555B1 (en) * | 1999-12-24 | 2002-04-30 | Micron Technology, Inc. | Bumped semiconductor component having test pads, and method and system for testing bumped semiconductor components |
US6975030B1 (en) | 2000-01-10 | 2005-12-13 | Micron Technology, Inc. | Silicon carbide contact for semiconductor components |
US6563215B1 (en) | 2000-01-10 | 2003-05-13 | Micron Technology, Inc. | Silicon carbide interconnect for semiconductor components and method of fabrication |
US7033920B1 (en) * | 2000-01-10 | 2006-04-25 | Micron Technology, Inc. | Method for fabricating a silicon carbide interconnect for semiconductor components |
US7173336B2 (en) * | 2000-01-31 | 2007-02-06 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
US7701069B2 (en) * | 2003-06-30 | 2010-04-20 | Intel Corporation | Solder interface locking using unidirectional growth of an intermetallic compound |
US7142449B2 (en) * | 2004-01-16 | 2006-11-28 | Hewlett-Packard Development Company, L.P. | Low temperature silicided tip |
JP3833669B2 (en) * | 2004-04-08 | 2006-10-18 | シャープ株式会社 | Semiconductor device and manufacturing method of semiconductor device |
FR2876243B1 (en) * | 2004-10-04 | 2007-01-26 | Commissariat Energie Atomique | DUCTILE BURST CONDUCTIVE PROTUBERANCE COMPONENT AND METHOD FOR ELECTRICAL CONNECTION BETWEEN THIS COMPONENT AND A COMPONENT HAVING HARD CONDUCTIVE POINTS |
US7630174B2 (en) * | 2006-01-20 | 2009-12-08 | Hitachi Global Storage Technologies Netherlands B.V. | Suspension and prober designs for recording head testing |
US7612574B2 (en) * | 2007-01-25 | 2009-11-03 | Micron Technology, Inc. | Systems and methods for defect testing of externally accessible integrated circuit interconnects |
WO2012106762A1 (en) * | 2011-02-09 | 2012-08-16 | South East Water Limited | Wirelessly networked fluid monitoring method, system and apparatus |
AU2014202604B2 (en) * | 2011-02-09 | 2015-08-27 | South East Water Corporation | Wirelessly networked fluid monitoring method, system and apparatus |
US8956973B2 (en) * | 2012-03-27 | 2015-02-17 | International Business Machines Corporation | Bottom-up plating of through-substrate vias |
FR3110769B1 (en) * | 2020-05-19 | 2022-06-24 | Commissariat Energie Atomique | Process for processing an electronic circuit for hybrid molecular bonding |
Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4329642A (en) | 1979-03-09 | 1982-05-11 | Siliconix, Incorporated | Carrier and test socket for leadless integrated circuit |
US4585991A (en) | 1982-06-03 | 1986-04-29 | Texas Instruments Incorporated | Solid state multiprobe testing apparatus |
US5323035A (en) | 1992-10-13 | 1994-06-21 | Glenn Leedy | Interconnection structure for integrated circuits and method for making same |
JPH0817192B2 (en) | 1988-05-30 | 1996-02-21 | 株式会社日立製作所 | Method for manufacturing probe head for semiconductor LSI inspection device |
US5137461A (en) | 1988-06-21 | 1992-08-11 | International Business Machines Corporation | Separable electrical connection technology |
US4937653A (en) | 1988-07-21 | 1990-06-26 | American Telephone And Telegraph Company | Semiconductor integrated circuit chip-to-chip interconnection scheme |
US4899107A (en) | 1988-09-30 | 1990-02-06 | Micron Technology, Inc. | Discrete die burn-in for nonpackaged die |
US5408190A (en) | 1991-06-04 | 1995-04-18 | Micron Technology, Inc. | Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die |
US5073117A (en) | 1989-03-30 | 1991-12-17 | Texas Instruments Incorporated | Flip-chip test socket adaptor and method |
JPH0369131A (en) | 1989-08-08 | 1991-03-25 | Fujitsu Ltd | Probe for semiconductor integrated circuit test use; manufacture of semiconductor device including test process using same probe |
US4943343A (en) | 1989-08-14 | 1990-07-24 | Zaher Bardai | Self-aligned gate process for fabricating field emitter arrays |
AU637874B2 (en) | 1990-01-23 | 1993-06-10 | Sumitomo Electric Industries, Ltd. | Substrate for packaging a semiconductor device |
US5207585A (en) | 1990-10-31 | 1993-05-04 | International Business Machines Corporation | Thin interface pellicle for dense arrays of electrical interconnects |
US5172050A (en) | 1991-02-15 | 1992-12-15 | Motorola, Inc. | Micromachined semiconductor probe card |
US5541525A (en) | 1991-06-04 | 1996-07-30 | Micron Technology, Inc. | Carrier for testing an unpackaged semiconductor die |
US5302891A (en) | 1991-06-04 | 1994-04-12 | Micron Technology, Inc. | Discrete die burn-in for non-packaged die |
US5686317A (en) | 1991-06-04 | 1997-11-11 | Micron Technology, Inc. | Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die |
US5519332A (en) | 1991-06-04 | 1996-05-21 | Micron Technology, Inc. | Carrier for testing an unpackaged semiconductor die |
US5815000A (en) | 1991-06-04 | 1998-09-29 | Micron Technology, Inc. | Method for testing semiconductor dice with conventionally sized temporary packages |
US5691649A (en) | 1991-06-04 | 1997-11-25 | Micron Technology, Inc. | Carrier having slide connectors for testing unpackaged semiconductor dice |
US5495179A (en) | 1991-06-04 | 1996-02-27 | Micron Technology, Inc. | Carrier having interchangeable substrate used for testing of semiconductor dies |
US5367253A (en) | 1991-06-04 | 1994-11-22 | Micron Semiconductor, Inc. | Clamped carrier for testing of semiconductor dies |
US5781022A (en) | 1991-06-04 | 1998-07-14 | Micron Technology, Inc. | Substrate having self limiting contacts for establishing an electrical connection with a semiconductor die |
US5177438A (en) | 1991-08-02 | 1993-01-05 | Motorola, Inc. | Low resistance probe for semiconductor |
US5177439A (en) | 1991-08-30 | 1993-01-05 | U.S. Philips Corporation | Probe card for testing unencapsulated semiconductor devices |
US5206585A (en) | 1991-12-02 | 1993-04-27 | At&T Bell Laboratories | Methods for testing integrated circuit devices |
JP3215424B2 (en) | 1992-03-24 | 2001-10-09 | ユニシス・コーポレイション | Integrated circuit module with fine self-alignment characteristics |
KR940001341A (en) | 1992-06-29 | 1994-01-11 | 디. 아이. 캐플란 | Instant connection for quick electrical access to electronic devices |
US5329423A (en) | 1993-04-13 | 1994-07-12 | Scholz Kenneth D | Compressive bump-and-socket interconnection scheme for integrated circuits |
US5420520A (en) | 1993-06-11 | 1995-05-30 | International Business Machines Corporation | Method and apparatus for testing of integrated circuit chips |
US5523696A (en) | 1993-06-14 | 1996-06-04 | International Business Machines Corp. | Method and apparatus for testing integrated circuit chips |
US5592736A (en) | 1993-09-03 | 1997-01-14 | Micron Technology, Inc. | Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads |
US5326428A (en) | 1993-09-03 | 1994-07-05 | Micron Semiconductor, Inc. | Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability |
US5478779A (en) | 1994-03-07 | 1995-12-26 | Micron Technology, Inc. | Electrically conductive projections and semiconductor processing method of forming same |
US5419807A (en) | 1993-09-03 | 1995-05-30 | Micron Technology, Inc. | Method of providing electrical interconnect between two layers within a silicon substrate, semiconductor apparatus, and method of forming apparatus for testing semiconductor circuitry for operability |
US5483741A (en) | 1993-09-03 | 1996-01-16 | Micron Technology, Inc. | Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice |
US5500605A (en) | 1993-09-17 | 1996-03-19 | At&T Corp. | Electrical test apparatus and method |
JP2710544B2 (en) | 1993-09-30 | 1998-02-10 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Probe structure, method of forming probe structure |
US5629837A (en) | 1995-09-20 | 1997-05-13 | Oz Technologies, Inc. | Button contact for surface mounting an IC device to a circuit board |
US5691041A (en) | 1995-09-29 | 1997-11-25 | International Business Machines Corporation | Socket for semi-permanently connecting a solder ball grid array device using a dendrite interposer |
-
1998
- 1998-12-17 US US09/213,573 patent/US6414506B2/en not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170315169A1 (en) * | 2010-09-07 | 2017-11-02 | Johnstech International Corporation | Electrically Conductive Pins For Microcircuit Tester |
US10877090B2 (en) * | 2010-09-07 | 2020-12-29 | Johnstech International Corporation | Electrically conductive pins for microcircuit tester |
US20170363659A1 (en) * | 2016-06-17 | 2017-12-21 | International Business Machines Corporation | Integrated self-coining probe |
US10001508B2 (en) * | 2016-06-17 | 2018-06-19 | International Business Machines Corporation | Integrated self-coining probe |
US10585119B2 (en) | 2016-06-17 | 2020-03-10 | International Business Machines Corporation | Integrated self-coining probe |
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