JPH0846318A - Chip component mounting structure - Google Patents
Chip component mounting structureInfo
- Publication number
- JPH0846318A JPH0846318A JP17658394A JP17658394A JPH0846318A JP H0846318 A JPH0846318 A JP H0846318A JP 17658394 A JP17658394 A JP 17658394A JP 17658394 A JP17658394 A JP 17658394A JP H0846318 A JPH0846318 A JP H0846318A
- Authority
- JP
- Japan
- Prior art keywords
- chip component
- electrode
- chip
- land
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＬＳＩチップ等のチッ
プ部品の実装構造に関し、さらに詳しくは、ＭＣＭ（マ
ルチチップモジュール）に適用可能なチップ部品の実装
構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure for a chip component such as an LSI chip, and more particularly to a mounting structure for a chip component applicable to an MCM (multi-chip module).
【０００２】近年、リードやボンディングワイヤを用い
ないチップ部品の実装技術として、フリップチップボン
ディングが実用化されている。フリップチップボンディ
ングでは、チップ部品の上面に設けられた電源やグラン
ドのための電極についての配線が困難になることがあ
り、その対策が要望されている。In recent years, flip chip bonding has been put into practical use as a mounting technique for chip parts that does not use leads or bonding wires. In flip-chip bonding, it may be difficult to wire electrodes for power supply and ground provided on the upper surface of the chip component, and countermeasures against this are required.
【０００３】[0003]
【従来の技術】従来、チップ部品の下面に設けられた複
数の電極にそれぞれ概略球形の半田バンプを固着してお
き、チップ部品をプリント基板上に位置決め載置した
後、半田バンプを溶融させて、チップ部品の各電極をプ
リント基板上の導体パターンに半田付け接続するように
したフリップチップボンディング技術が公知である。2. Description of the Related Art Conventionally, a substantially spherical solder bump is fixed to each of a plurality of electrodes provided on the lower surface of a chip component, the chip component is positioned and mounted on a printed circuit board, and then the solder bump is melted. Flip chip bonding technology is known in which each electrode of a chip component is soldered and connected to a conductor pattern on a printed circuit board.
【０００４】[0004]
【発明が解決しようとする課題】フリップチップボンデ
ィングは、リードやボンディングワイヤを用いることな
しにチップ部品とプリント基板とを高密度に接続するこ
とができるという点で画期的なものであるが、チップ部
品の上面に設けられた電極についてプリント基板への接
続を行うことができないという欠点を有している。Flip chip bonding is epoch-making in that chip components and printed circuit boards can be connected at high density without using leads or bonding wires. The electrode provided on the upper surface of the chip component has a drawback that it cannot be connected to the printed board.
【０００５】例えば、ベアチップをプリント基板にフリ
ップチップボンディングにより実装してＭＣＭを製造す
る場合、ベアチップの上面にグランド電位の部分が生じ
ることがあり、ベアチップ上面のグランド（接地）電位
の電極を直接プリント基板に接続する必要が生じること
がある。For example, when a bare chip is mounted on a printed circuit board by flip-chip bonding to manufacture an MCM, a ground potential portion may occur on the upper surface of the bare chip, and the electrode of the ground (ground) potential on the upper surface of the bare chip is directly printed. It may be necessary to connect to the board.
【０００６】よって、本発明の目的は、フリップチップ
ボンディングが適用されるチップ部品の実装構造におい
て、チップ部品の上面に設けられた電極を容易にプリン
ト基板に接続することができる構造を提供することにあ
る。Therefore, an object of the present invention is to provide a structure for mounting a chip component to which flip chip bonding is applied, in which an electrode provided on the upper surface of the chip component can be easily connected to a printed board. It is in.
【０００７】[0007]
【課題を解決するための手段】本発明によると、その上
面に少なくとも１つの第１の電極を有し、その下面に複
数の第２の電極を有するチップ部品と、上記第２の電極
に対向する複数の導体パターンと該導体パターンの周囲
に位置する少なくとも１つのランドとを有するプリント
基板と、上記第２の電極と該第２の電極が対応する上記
導体パターンとをそれぞれ接続する複数のバンプと、上
記チップ部品の周囲に設けられ、上記第１の電極と上記
ランドを接続する導電性ペーストとを備えたチップ部品
の実装構造が提供される。According to the present invention, a chip part having at least one first electrode on its upper surface and a plurality of second electrodes on its lower surface, and a chip component facing the second electrode. A printed circuit board having a plurality of conductor patterns and at least one land located around the conductor pattern, and a plurality of bumps for respectively connecting the second electrode and the conductor pattern to which the second electrode corresponds. And a mounting structure for a chip component, which is provided around the chip component and includes a conductive paste that connects the first electrode and the land.
【０００８】[0008]
【作用】本発明のチップ部品の実装構造では、導電性ペ
ーストをチップ部品の周囲に設け、これによりチップ部
品の上面に設けられた第１の電極とプリント基板上のラ
ンドとを接続するようにしているので、本発明の目的が
達成される。In the chip component mounting structure of the present invention, the conductive paste is provided around the chip component so that the first electrode provided on the upper surface of the chip component is connected to the land on the printed circuit board. Therefore, the object of the present invention is achieved.
【０００９】[0009]
【実施例】以下本発明の実施例を添付図面に沿って詳細
に説明する。図１は本発明の第１実施例を示すＭＣＭの
部分的な平面図である。このＭＣＭは、プリント基板２
上にベアチップ４をフリップチップボンディングにより
実装して構成される。Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a partial plan view of an MCM showing a first embodiment of the present invention. This MCM is printed circuit board 2
The bare chip 4 is mounted thereon by flip chip bonding.
【００１０】ベアチップ４の上面には、グランド用の電
極６と電源用の電極８とが設けられている。ベアチップ
４は平面的にはほぼ正方形をなしており、ベアチップ４
をプリント基板２上に実装するに際しての位置決めを行
うことを１つの目的として、プリント基板２上の対角位
置にはランド１０及び１２が形成されている。An electrode 6 for ground and an electrode 8 for power supply are provided on the upper surface of the bare chip 4. The bare chip 4 has a substantially square shape in plan view.
The lands 10 and 12 are formed at diagonal positions on the printed circuit board 2 for the purpose of positioning the printed circuit board 2 on the printed circuit board 2.
【００１１】このようなランドを予め定められた位置に
形成しておくことによって、その位置を通常の画像認識
技術により把握することで、ベアチップ４の実装作業を
自動化することができる。By forming such a land at a predetermined position and grasping the position by a normal image recognition technique, the mounting work of the bare chip 4 can be automated.
【００１２】この実施例では、グランド用の電極６は導
電性ペースト１４によりランド１０に接続され、電源用
の電極８は導電性ペースト１６によりランド１２に接続
される。In this embodiment, the ground electrode 6 is connected to the land 10 by the conductive paste 14, and the power supply electrode 8 is connected to the land 12 by the conductive paste 16.
【００１３】導電性ペーストとしては、銀ペースト、半
田ペースト、カーボンペースト、液状物質等を用いるこ
とができる。図２は、図１に示されるＭＣＭのグランド
用の電極６近傍の断面図である。ベアチップ４はその下
面に複数の電極１８を有しており、プリント基板２の上
面には、電極１８の各々にそれぞれ対応して複数の導体
パターン２０が形成されている。符号２２は各電極１８
を各導体パターン２０にそれぞれフリップチップボンデ
ィングするためのバンプを示している。バンプ２２の材
質は、半田、金等の金属である。As the conductive paste, silver paste, solder paste, carbon paste, liquid substance or the like can be used. FIG. 2 is a cross-sectional view of the MCM shown in FIG. 1 in the vicinity of the ground electrode 6. The bare chip 4 has a plurality of electrodes 18 on its lower surface, and a plurality of conductor patterns 20 are formed on the upper surface of the printed circuit board 2 in correspondence with each of the electrodes 18. Reference numeral 22 denotes each electrode 18
The bumps for flip-chip bonding to the conductor patterns 20 are shown. The material of the bumps 22 is a metal such as solder or gold.
【００１４】この実施例では、ランド１０は、スルーホ
ール２４を介してプリント基板２の内部に積層されるグ
ランド層２６に接続されている。また、ベアチップ４と
プリント基板２の間には、絶縁性充填剤２８が充填され
ており、バンプ２２は充填剤２８に埋設されている。In this embodiment, the land 10 is connected to the ground layer 26 laminated inside the printed circuit board 2 via the through hole 24. An insulating filler 28 is filled between the bare chip 4 and the printed board 2, and the bumps 22 are embedded in the filler 28.
【００１５】図示はしないが、図１の電源用の電極８に
ついてもランド１２に対応して設けられるスルーホール
を介してプリント配線板２の内部又は表面に積層される
電源層に接続されている。Although not shown, the power supply electrode 8 of FIG. 1 is also connected to a power supply layer laminated inside or on the surface of the printed wiring board 2 through a through hole provided corresponding to the land 12. .
【００１６】この実施例によると、ベアチップ４をプリ
ント基板２上にフリップチップボンディングにより実装
した後に、ベアチップ４の上面に形成された電極６及び
８を導電性ペースト１４及び１６によりそれぞれ容易に
プリント基板２上のランド１０及び１２に接続すること
ができる。According to this embodiment, after the bare chip 4 is mounted on the printed board 2 by flip chip bonding, the electrodes 6 and 8 formed on the upper surface of the bare chip 4 are easily printed by the conductive pastes 14 and 16, respectively. 2 can be connected to the lands 10 and 12 above.
【００１７】また、グランド用の電極６については、導
電性ペースト１４、ランド１０及びスルーホール２４を
介して通常比較的面積が大きいグランド層２６に接続し
ているので、ベアチップ４についての放熱性が向上す
る。Further, since the ground electrode 6 is connected to the ground layer 26 which is usually relatively large in area through the conductive paste 14, the land 10 and the through hole 24, the heat dissipation of the bare chip 4 is improved. improves.
【００１８】この放熱性を高いレベルで維持するために
は、導電性ペースト１４として伝熱性に優れたものを用
いるのが望ましい。導電性ペースト１４は例えば金属粉
を樹脂中に分散させたものであるので、導電性ペースト
における金属粉濃度を高めるか或いは伝熱性が良好な金
属粉を採用すればよい。In order to maintain the heat dissipation at a high level, it is desirable to use the conductive paste 14 having excellent heat conductivity. Since the conductive paste 14 is, for example, a metal powder dispersed in a resin, the metal powder concentration in the conductive paste may be increased or a metal powder having a good heat transfer property may be adopted.
【００１９】さらに、本実施例では、ベアチップ４とプ
リント基板２の間に絶縁性充填剤を介在させているの
で、ベアチップ４の材質の線熱膨張係数とプリント基板
２の材質の線熱膨張係数とが異なる場合におけるこのＭ
ＣＭの使用温度範囲を拡大することができる。Further, in this embodiment, since the insulative filler is interposed between the bare chip 4 and the printed circuit board 2, the linear thermal expansion coefficient of the material of the bare chip 4 and the linear thermal expansion coefficient of the material of the printed circuit board 2 are increased. This M when and are different
The operating temperature range of CM can be expanded.
【００２０】即ち、ベアチップ４の線熱膨張係数とプリ
ント基板２の線熱膨張係数とが大きく異なる場合、この
ＭＣＭを製造時における温度と異なる温度に加熱或いは
冷却すると、フリップチップボンディング部に亀裂が生
じ易いものであるが、絶縁性充填剤１８をベアチップ４
及びプリント基板２に密着しておくことによって、熱歪
みの発生を最小限に押さえることができ、破損等を未然
に防止することができるのである。That is, when the coefficient of linear thermal expansion of the bare chip 4 and the coefficient of linear thermal expansion of the printed circuit board 2 are greatly different, if this MCM is heated or cooled to a temperature different from the temperature at the time of manufacturing, cracks will occur in the flip chip bonding portion. Although easily generated, the insulating filler 18 is added to the bare chip 4
Further, by closely contacting with the printed circuit board 2, it is possible to minimize the occurrence of thermal strain and prevent damage or the like in advance.
【００２１】尚、この実施例では、図２に示されるよう
に、グランド用の電極６はプリント基板２の内層として
得られるグランド層に接続されているが、グランド層は
プリント基板２の上面或いは下面に形成されていてもよ
い 図３は本発明の第２実施例を示すＭＣＭの部分的な平面
図である。この実施例は、接地用の電極６をプリント基
板２上のランド１０に接続するための導電性ペースト１
４を、ベアチップ４の上面のほぼ全面に渡りさらに塗布
している点で特徴付けられる。導電性ペースト１４は電
源用の電極８とランド１２を接続するための導電性ペー
スト１６とは絶縁させられている。In this embodiment, as shown in FIG. 2, the ground electrode 6 is connected to a ground layer obtained as an inner layer of the printed board 2, but the ground layer is the upper surface of the printed board 2 or It may be formed on the lower surface. FIG. 3 is a partial plan view of the MCM showing the second embodiment of the present invention. In this embodiment, the conductive paste 1 for connecting the ground electrode 6 to the land 10 on the printed circuit board 2 is used.
4 is further coated on almost the entire upper surface of the bare chip 4. The conductive paste 14 is insulated from the conductive paste 16 for connecting the power source electrode 8 and the land 12.
【００２２】この実施例によると、導電性ペースト１４
が前実施例におけるのと同じようにプリント基板２のグ
ランド層に接続されている場合に、ベアチップ４に対す
る放熱性をさらに向上させることができる。また、これ
に加えて、ベアチップ４に対する電磁遮蔽性が得られる
という効果も生じる。According to this embodiment, the conductive paste 14
Is connected to the ground layer of the printed circuit board 2 in the same manner as in the previous embodiment, the heat dissipation of the bare chip 4 can be further improved. In addition to this, there is an effect that the electromagnetic shielding property with respect to the bare chip 4 is obtained.
【００２３】導電性ペースト１４はこの実施例ではベア
チップ４の上面のほぼ全面に塗布されているが、導電性
ペースト１４の使用量を減少させるために、導電性ペー
スト１４はベアチップ４の上面上にメッシュ状に塗布さ
れていてもよい。この場合にも、十分な放熱性の向上と
電磁遮蔽性が得られる。Although the conductive paste 14 is applied to almost the entire upper surface of the bare chip 4 in this embodiment, the conductive paste 14 is applied to the upper surface of the bare chip 4 in order to reduce the amount of the conductive paste 14 used. It may be applied in a mesh form. Also in this case, sufficient heat dissipation and electromagnetic shielding can be obtained.
【００２４】図４は本発明の第３実施例を示すＭＣＭの
部分的な平面図である。この実施例は、プリント基板２
上のベアチップ４の周囲にグランド用のランド１０を複
数設けておき、それぞれのランド１０を覆うように導電
性ペースト１４を設けている点で特徴付けられる。FIG. 4 is a partial plan view of the MCM showing the third embodiment of the present invention. In this embodiment, the printed circuit board 2
It is characterized in that a plurality of ground lands 10 are provided around the upper bare chip 4 and a conductive paste 14 is provided so as to cover each land 10.
【００２５】各ランド１０は図２に示されるのと同じよ
うにプリント基板２の内部に積層されるグランド層に接
続される。この実施例によると、ベアチップ４に対する
放熱性をさらに高めることができるので、この実施例は
発熱量の大きいベアチップの実装に適している。Each land 10 is connected to a ground layer laminated inside the printed circuit board 2 in the same manner as shown in FIG. According to this embodiment, since the heat dissipation to the bare chip 4 can be further enhanced, this embodiment is suitable for mounting a bare chip which generates a large amount of heat.
【００２６】図５は本発明の第４実施例を示すＭＣＭの
部分的な断面図である。この実施例では、ベアチップ４
の下面の最外周部に位置するバンプ２２Ａが導電性ペー
スト１４に接続されるようにしている。FIG. 5 is a partial sectional view of an MCM showing a fourth embodiment of the present invention. In this embodiment, the bare chip 4
The bumps 22A located on the outermost peripheral portion of the lower surface of are connected to the conductive paste 14.
【００２７】このような構成は、例えば、絶縁性充填剤
２８を予めバンプ２２Ａの内側にまで充填しておき、そ
の後に導電性ペースト１４を塗布することにより実現さ
れる。Such a structure is realized, for example, by previously filling the inside of the bump 22A with the insulating filler 28 and then applying the conductive paste 14.
【００２８】この実施例によると、バンプ２２Ａが対応
するベアチップ４の電極１８Ａが接地電位である場合
に、その接地接続を容易に行うことができる。以上説明
した実施例では、ベアチップをプリント基板に実装して
なるＭＣＭへの本発明の適用例が開示されているが、本
発明はベアチップに限らずＴＡＢ、リードフレームを有
するチップ部品、ＢＧＡ（ボールグリッドアレイ）等に
も適用可能である。According to this embodiment, when the electrode 18A of the bare chip 4 corresponding to the bump 22A is at the ground potential, the ground connection can be easily made. In the embodiment described above, the application example of the present invention to the MCM in which the bare chip is mounted on the printed circuit board is disclosed, but the present invention is not limited to the bare chip, the chip component having the TAB and the lead frame, the BGA (ball). It is also applicable to a grid array) or the like.
【００２９】[0029]
【発明の効果】以上説明したように、本発明によると、
フリップチップボンディングが適用されるチップ部品の
実装構造において、チップ部品の上面に設けられた電極
を容易にプリント基板に接続することができるようにな
るという効果が生じる。As described above, according to the present invention,
In the mounting structure of the chip component to which the flip chip bonding is applied, it is possible to easily connect the electrode provided on the upper surface of the chip component to the printed board.
【図１】本発明の第１実施例を示すＭＣＭ（マルチチッ
プモジュール）の部分的な平面図である。FIG. 1 is a partial plan view of an MCM (multi-chip module) showing a first embodiment of the present invention.
【図２】本発明の第１実施例を示すＭＣＭの部分的な断
面図である。FIG. 2 is a partial cross-sectional view of the MCM showing the first embodiment of the present invention.
【図３】本発明の第２実施例を示すＭＣＭの部分的な平
面図である。FIG. 3 is a partial plan view of an MCM showing a second embodiment of the present invention.
【図４】本発明の第３実施例を示すＭＣＭの部分的な平
面図である。FIG. 4 is a partial plan view of an MCM showing a third embodiment of the present invention.
【図５】本発明の第４実施例を示すＭＣＭの部分的な断
面図である。FIG. 5 is a partial sectional view of an MCM showing a fourth embodiment of the present invention.
２ プリント基板 ４ ベアチップ（チップ部品） ６，８，１８ 電極 １０，１２ ランド １４，１６ 導電性ペースト ２０ 導体パターン ２４ スルーホール ２６ グランド層 2 Printed circuit board 4 Bare chip (chip component) 6,8,18 Electrode 10,12 Land 14,16 Conductive paste 20 Conductor pattern 24 Through hole 26 Ground layer
Claims (5)
を有し、その下面に複数の第２の電極を有するチップ部
品と、 上記第２の電極に対向する複数の導体パターンと該導体
パターンの周囲に位置する少なくとも１つのランドとを
有するプリント基板と、 上記第２の電極と該第２の電極が対応する上記導体パタ
ーンとをそれぞれ接続する複数のバンプと、 上記チップ部品の周囲に設けられ、上記第１の電極と上
記ランドを接続する導電性ペーストとを備えたチップ部
品の実装構造。1. A chip component having at least one first electrode on an upper surface thereof and a plurality of second electrodes on a lower surface thereof, a plurality of conductor patterns facing the second electrodes, and the conductor pattern. And a plurality of bumps respectively connecting the second electrode and the conductor pattern corresponding to the second electrode, and a printed board having at least one land located around the chip component, and provided around the chip component. And a mounting structure for a chip component, comprising a conductive paste for connecting the first electrode and the land.
ールと、該スルーホールに接続されるグランド層とをさ
らに有する請求項１に記載のチップ部品の実装構造。2. The first electrode is a ground electrode, and the printed circuit board further has a through hole connected to the land and a ground layer connected to the through hole. Mounting structure of chip parts.
覆うように設けられている請求項１に記載のチップ部品
の実装構造。3. The chip component mounting structure according to claim 1, wherein the first electrode is a ground electrode, and the conductive paste is provided so as to further cover an upper surface of the chip component.
に充填される絶縁性充填剤をさらに備え、 上記半田バンプは該充填剤に埋設される請求項１に記載
のチップ部品の実装構造。4. The mounting structure for a chip component according to claim 1, further comprising an insulative filler filled between the chip component and the printed circuit board, wherein the solder bump is embedded in the filler.
用の位置合わせランドである請求項１に記載のチップ部
品の実装構造。5. The mounting structure for a chip component according to claim 1, wherein the land is an alignment land for positioning the chip component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17658394A JP2933830B2 (en) | 1994-07-28 | 1994-07-28 | Chip component mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17658394A JP2933830B2 (en) | 1994-07-28 | 1994-07-28 | Chip component mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0846318A true JPH0846318A (en) | 1996-02-16 |
| JP2933830B2 JP2933830B2 (en) | 1999-08-16 |
Family
ID=16016107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17658394A Expired - Fee Related JP2933830B2 (en) | 1994-07-28 | 1994-07-28 | Chip component mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2933830B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4973761B2 (en) | 2009-05-25 | 2012-07-11 | 株式会社デンソー | Semiconductor device |
-
1994
- 1994-07-28 JP JP17658394A patent/JP2933830B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2933830B2 (en) | 1999-08-16 |
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