JPH0845977A - Integrated circuit module - Google Patents

Integrated circuit module

Info

Publication number
JPH0845977A
JPH0845977A JP6181520A JP18152094A JPH0845977A JP H0845977 A JPH0845977 A JP H0845977A JP 6181520 A JP6181520 A JP 6181520A JP 18152094 A JP18152094 A JP 18152094A JP H0845977 A JPH0845977 A JP H0845977A
Authority
JP
Japan
Prior art keywords
integrated circuit
wire bonding
circuit board
circuit
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6181520A
Other languages
Japanese (ja)
Inventor
Mitsunori Abe
光紀 安陪
Eiji Mishiro
英治 三代
Michiaki Takada
理映 高田
Nana Nakajima
奈々 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6181520A priority Critical patent/JPH0845977A/en
Publication of JPH0845977A publication Critical patent/JPH0845977A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize high density wire bonding by arranging the wire bonding pads on an integrated circuit in correspondence with protrusions and recesses of a conductive layer formed on the circuit board. CONSTITUTION:Square protrusions and recesses 19 are formed on each side of a ground pattern 13 around an integrated circuit 12. A signal circuit and a power supply circuit are set at appropriate positions for the wire bonding pads 14 on the circuit board 11 side being connected through wires 16 with the wire bonding pads 15 on the integrated circuit 12. The wire bonding pad 15 on the integrated circuit 12 side being connected with a ground circuit is connected through the wire 16 with a protrusion 19 formed on the periphery of the ground pattern 13 and thereby it is connected efficiently through the shortest route. This structure realizes high density and high quality wire bonding easily.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、集積回路と該集積回路
の搭載される回路基板との配線接続構造の改良された集
積回路モジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit module having an improved wiring connection structure between an integrated circuit and a circuit board on which the integrated circuit is mounted.

【０００２】ＬＳＩなどの集積回路を回路基板上に搭載
させるとともに、回路基板の回路パターンと回路接続さ
せて集積回路モジュールとすることが行なわれる。この
ような集積回路モジュールは、一つの集積回路を搭載さ
せるもの以外に、最近では複数の集積回路を同一の回路
基板上に搭載させる、いわゆるマルチチップモジュール
（ＭＣＭ）なども開発実用化されるようになっている。[0002] An integrated circuit such as an LSI is mounted on a circuit board and is connected to a circuit pattern on the circuit board to form an integrated circuit module. In addition to the one in which one integrated circuit is mounted, recently, a so-called multi-chip module (MCM) in which a plurality of integrated circuits are mounted on the same circuit board is also developed and put to practical use. It has become.

【０００３】このようなことから、電子・通信装置の小
形化、高密度化ならびに高速化の要望の高まりに応じる
ためには、集積回路に形成される入出力用端子（Ｉ／Ｏ
端子）数が増加されるとともに回路基板側の端子の小形
化ならびに端子の狭ピッチ化技術が必須な要件である。
しかしながら、小形化、狭ピッチ化には種々の要因から
おのずと限界があって限界以上の実現化には困難をとも
ない不可能な状態となる。Therefore, in order to meet the increasing demand for miniaturization, high density and high speed of electronic / communication devices, input / output terminals (I / O) formed in an integrated circuit are required.
As the number of terminals increases, the miniaturization of terminals on the circuit board side and the narrow pitch technology of terminals are essential requirements.
However, the miniaturization and the narrowing of the pitch are naturally limited due to various factors, and it is difficult and impossible to realize the size beyond the limit.

【０００４】[0004]

【従来の技術】従来の集積回路モジュールの要部を図８
の図（ａ）に示す。図（ａ）は集積回路１つ分の平面図
であり、その要部拡大図が図（ｂ）に示される。2. Description of the Related Art FIG. 8 shows a main part of a conventional integrated circuit module.
Is shown in FIG. FIG. 1A is a plan view of one integrated circuit, and an enlarged view of the main part is shown in FIG.

【０００５】回路基板１上には集積回路２搭載用の接地
パターン（ダイパッド）３が集積回路２の下面よりも僅
かに大きく形成されており、その接地パターン３面上に
集積回路２の下面の接地導体面電極が導電接着剤によっ
て導電接続（ダイボンド）された状態に搭載されてい
る。A ground pattern (die pad) 3 for mounting the integrated circuit 2 is formed on the circuit board 1 slightly larger than the lower surface of the integrated circuit 2, and the lower surface of the integrated circuit 2 is formed on the ground pattern 3 surface. The ground conductor surface electrode is mounted in a state of being conductively connected (die-bonded) with a conductive adhesive.

【０００６】接地パターン３周囲の回路基板１上にはパ
ターン形成された短冊状のワイヤボンデイング用パッド
４が各辺に沿って内外の２列に形成されており、集積回
路２上面の各辺に形成されたワイヤボンデイング用パッ
ド５との間をそれぞれワイヤ６でボンデイング接続させ
る。各辺の中央部分のワイヤ６は図が煩雑となるために
図示省略して示してある。On the circuit board 1 around the ground pattern 3, pattern-shaped strip-shaped wire bonding pads 4 are formed in two rows inside and outside along each side, and on each side of the upper surface of the integrated circuit 2. Bonding connections are made with the wires 6 between the formed wire bonding pads 5 respectively. The wire 6 in the central portion of each side is omitted in the drawing because the drawing becomes complicated.

【０００７】回路基板１上のワイヤボンデイング用パッ
ド４に連成された円形状の部分は回路基板１の内層、ま
たは裏面層の回路導体パターンなどと接続される接続用
のビアホール７部分である。A circular portion connected to the wire bonding pad 4 on the circuit board 1 is a via hole 7 portion for connection which is connected to an inner layer of the circuit board 1 or a circuit conductor pattern on the back surface layer.

【０００８】図（ｂ）の拡大部分図に示されるように、
集積回路２のワイヤボンデイング用パッド５と接続され
る回路基板１上のワイヤボンデイング用パッド４との接
続関係は、たとえば、ワイヤボンデイング用パッド４−
１，４−３，４−６，４−８がそれぞれ信号回路との接
続用、４−２，４−５，４−９が接地回路との接続用、
４−４，４−７が電源回路との接続用、である。As shown in the enlarged partial view of FIG.
The connection relationship between the wire bonding pad 5 of the integrated circuit 2 and the wire bonding pad 4 on the circuit board 1 to be connected is, for example, the wire bonding pad 4-
1, 4-3, 4-6, 4-8 are for connection with the signal circuit, 4-2, 4-5, 4-9 are for connection with the ground circuit,
4-4 and 4-7 are for connection with a power supply circuit.

【０００９】以上のような接続構成とすることは、外部
からの雑音や回路基板１内の導体パターン間で生じる信
号回路への干渉などを効果的に防止させるため、電源回
路または接地回路を信号回路相互間に介在させるように
していることにある。The above-described connection configuration effectively prevents noise from the outside and interference with the signal circuit between the conductor patterns in the circuit board 1 so that the power supply circuit or the ground circuit is connected to the signal circuit. It is to interpose between the circuits.

【００１０】[0010]

【発明が解決しようとする課題】上記集積回路２のワイ
ヤボンデイング用パッド５は小形、高密度化などの理由
から、ピッチ間隔が１００μｍ程度の狭間隔で形成され
ている。したがって、上記したように各信号回路間に電
源回路や接地回路を介在させることからも、Ｉ／Ｏ（入
出力）用のワイヤボンデイング用パッド５数も増加させ
られるとともに、より小形化、狭間隔に形成されるよう
になってきている。The wire bonding pads 5 of the integrated circuit 2 are formed with a narrow pitch of about 100 .mu.m for reasons of miniaturization and high density. Therefore, since the power supply circuit and the ground circuit are interposed between the respective signal circuits as described above, the number of the wire bonding pads 5 for I / O (input / output) can be increased, and the size and the spacing can be reduced. Is being formed.

【００１１】回路基板１側のワイヤボンデイング用パッ
ド４は、印刷精度、ビアホール７の成形条件、表面の平
坦度などの制約から限度以上の狭間隔とすることができ
ず、現状では、たとえば４００μｍのピッチ間隔で、２
００μｍの導体幅、２００μｍの間隔幅で形成させるこ
とになっている。The wire bonding pads 4 on the side of the circuit board 1 cannot be made narrower than the limit due to restrictions such as printing accuracy, molding conditions of the via holes 7, and flatness of the surface. 2 at pitch intervals
The conductor width is 00 μm and the interval width is 200 μm.

【００１２】したがって、Ｉ／Ｏ数が増加すると回路基
板１のワイヤボンデイング用パッド４を集積回路２の周
辺に形成させることができなくなる。このようなことか
ら、図８では限度上１列上に形成することができずに、
２列としたものである。Therefore, when the number of I / O increases, it becomes impossible to form the wire bonding pad 4 of the circuit board 1 around the integrated circuit 2. For this reason, in FIG. 8, it cannot be formed in one row due to the limit,
There are two rows.

【００１３】しかも、図（ｂ）から明らかなようにワイ
ヤ６どうしが交差しないように彎曲迂回させるなどの配
慮がなされている。上記の印刷精度とは、位置誤差、形
状誤差などによる間隔を限度以上に接近させることがで
きないこと、あるいは狭幅とすることによる、かすれな
どを生じることである。ビアホールの成形条件とは、限
度以上に接近させると所定の絶縁抵抗値が得られないこ
とや、回路基板に亀裂などの不都合を生じるおそれがあ
ることである。表面の平坦度とは、ワイヤボンデイング
用パッド４の幅を限度以上に狭幅にすると山状に盛り上
がり、ワイヤボンデイングに必要な平坦面が得られない
ことになることである。Moreover, as is apparent from FIG. 6B, consideration is given to such a manner that the wires 6 are detoured so as not to intersect each other. The above-mentioned printing accuracy means that a gap due to a position error, a shape error, or the like cannot be made closer than a limit, or a narrow width causes a blur. The via hole forming conditions are that a predetermined insulation resistance value cannot be obtained and the circuit board may be inconveniently cracked when the via holes are brought closer than the limit. The flatness of the surface means that if the width of the wire bonding pad 4 is made narrower than the limit, it rises in a mountain shape and a flat surface necessary for wire bonding cannot be obtained.

【００１４】本発明は上記のような問題点にかんがみ
て、ワイヤボンデイングによるワイヤ接続の高密度化を
可能とするとともに、高品質かつワイヤ接続の容易化を
図ることで上記問題点の解消された新規なる集積回路モ
ジュールの提供を発明の課題とするものである。In view of the above problems, the present invention solves the above problems by making it possible to increase the density of wire connections by wire bonding and to achieve high quality and easy wire connections. It is an object of the invention to provide a new integrated circuit module.

【００１５】[0015]

【課題を解決するための手段】上記課題を達成するため
の本発明手段の構成要旨とするところは、第１には、回
路基板上の集積回路搭載領域に該集積回路よりも広面積
な導電層を形成するとともに該導電層の周辺に集積回路
のワイヤボンデイング用パッドとワイヤ接続されるべき
箇所に対応した凹凸が形成されてなり、上記集積回路の
ワイヤボンデイング用パッドと回路基板上の導電層の凹
凸箇所とを対応させてワイヤボンデイングによりワイヤ
接続される集積回路モジュールである。In order to achieve the above object, the gist of the present invention is as follows: First, a conductive area having a larger area than the integrated circuit is provided in the integrated circuit mounting region on the circuit board. Forming a layer and forming concavities and convexities on the periphery of the conductive layer in correspondence with the wire bonding pads of the integrated circuit and the portions to be wire-connected, and the wire bonding pad of the integrated circuit and the conductive layer on the circuit board. The integrated circuit module is wire-bonded by wire bonding in correspondence with the concave and convex portions.

【００１６】第２には、第１の集積回路モジュールの周
辺に形成される凹凸の凸部は集積回路のワイヤボンデイ
ング用パッドからワイヤ接続される回路基板上のワイヤ
ボンデイング用パッドの隣接間の中間部分に形成される
集積回路モジュールである。Second, the convex and concave portions formed on the periphery of the first integrated circuit module are formed between the adjacent wire bonding pads on the circuit board, which are wire-connected from the wire bonding pads of the integrated circuit. It is an integrated circuit module formed in a part.

【００１７】第３には、第１の集積回路モジュールの周
辺に凹凸の形成された導電層は電源パターンもしくは接
地パターンの少なくとも何れかである集積回路モジュー
ルである。Thirdly, the first integrated circuit module is an integrated circuit module in which the conductive layer having irregularities formed around the first integrated circuit module is at least one of a power supply pattern and a ground pattern.

【００１８】第４には、第１および第３の集積回路モジ
ュールの周辺に凹凸の形成される導電層は上記回路基板
を貫通する導体により該回路基板裏面の導電層と接続さ
れる集積回路モジュールである。Fourth, an integrated circuit module in which the conductive layer having irregularities formed around the first and third integrated circuit modules is connected to the conductive layer on the back surface of the circuit board by a conductor penetrating the circuit board. Is.

【００１９】第５には、第４の集積回路モジュールの回
路基板を貫通する導体は熱伝導体である集積回路モジュ
ールである。Fifth, the conductor penetrating the circuit board of the fourth integrated circuit module is a heat conductor, which is an integrated circuit module.

【００２０】[0020]

【作用】上記本発明の構成手段によると、第１の集積回
路モジュールでは、集積回路の周辺に形成された導電層
の凹凸箇所に対応させて、集積回路のワイヤボンデイン
グ用パッドとの間をワイヤ接続させることにより、導電
層である共通電位に対して最短距離で接続させることが
でき、その分信号回路領域のワイヤボンデイング用パッ
ドの増加あるいは、間隔を広げることが可能となる。ま
た、凹凸位置に合わせることでボンデイング位置が正確
となるとともに位置決めが容易に行なえる。According to the above construction means of the present invention, in the first integrated circuit module, the wire between the integrated circuit and the wire bonding pad of the integrated circuit is made to correspond to the uneven portion of the conductive layer formed around the integrated circuit. By making the connection, the connection can be made to the common potential which is the conductive layer in the shortest distance, and the number of wire bonding pads in the signal circuit region can be increased or the distance can be increased accordingly. In addition, the bonding position becomes accurate and the positioning can be easily performed by matching the uneven position.

【００２１】第２の集積回路モジュールでは、集積回路
のワイヤボンデイング用パッドと回路基板上のワイヤボ
ンデイング用パッドとのワイヤ接続に応じて、中間部分
の凹凸とのワイヤ接続を行なうことでワイヤどうしの交
差などがないことからボンデイング作業が逐次順序よく
能率的に行なえる。In the second integrated circuit module, the wires are connected to each other by making a wire connection with the unevenness of the intermediate portion in accordance with the wire connection between the wire bonding pad of the integrated circuit and the wire bonding pad on the circuit board. Since there are no intersections, the bonding work can be done sequentially and efficiently.

【００２２】第３の集積回路モジュールでは、回路基板
上の導電層は電源パターンおよび、もしくは接地パター
ンとすることで共通電位である導電層に任意箇所に設定
接続させることが可能である。In the third integrated circuit module, the conductive layer on the circuit board has a power supply pattern and / or a ground pattern, so that the conductive layer having a common potential can be set and connected at an arbitrary position.

【００２３】第４の集積回路モジュールでは、回路基板
上の導電層から延びて回路基板を貫通する導体であるビ
アホールによって回路基板裏面の導電層と接続されるこ
とで、電源回路あるいは接地回路との効率的な接続が行
なえ、その分信号回路のパターン配置などが容易とな
る。In the fourth integrated circuit module, a via hole, which is a conductor extending from the conductive layer on the circuit board and penetrating the circuit board, is connected to the conductive layer on the back surface of the circuit board, thereby forming a power circuit or a ground circuit. Efficient connection can be performed, and the pattern layout of the signal circuit can be facilitated accordingly.

【００２４】第５の集積回路モジュールでは、上記回路
基板を貫通する導体であるビアホールによって集積回路
からの発熱を回路基板裏面に伝導させることができるか
ら、裏面から適宜な放熱手段を介して効率よく熱放散を
させることができる。In the fifth integrated circuit module, the heat generated from the integrated circuit can be conducted to the back surface of the circuit board by the via hole which is a conductor penetrating the circuit board. Can dissipate heat.

【００２５】[0025]

【実施例】以下、本発明集積回路モジュールについて具
体的実施例により、それぞれに図を参照しながら詳細に
説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The integrated circuit module of the present invention will be described in detail below with reference to the accompanying drawings.

【００２６】図１に本発明の第１実施例が示される。図
１の図（ａ）は平面図、図（ｂ）はその要部拡大図、で
あり、側断面図が図２に示される。回路基板１１上には
集積回路１２搭載用の導電層である接地パターン（ダイ
パッド）１３が集積回路１２の下面よりも広く形成され
ており、その接地パターン１３面上に集積回路１２下面
の接地回路面がＡｇエポキシ系樹脂などの導電接着剤に
よって導電接続（ダイボンド）された状態に搭載接続さ
れている。FIG. 1 shows a first embodiment of the present invention. FIG. 1A is a plan view, FIG. 1B is an enlarged view of a main part thereof, and a side sectional view is shown in FIG. A ground pattern (die pad) 13, which is a conductive layer for mounting the integrated circuit 12, is formed on the circuit board 11 wider than the lower surface of the integrated circuit 12, and the ground circuit on the lower surface of the integrated circuit 12 is formed on the ground pattern 13 surface. The surfaces are mounted and connected in a state in which they are conductively connected (die-bonded) with a conductive adhesive such as Ag epoxy resin.

【００２７】接地パターン１３周囲の回路基板１１上に
はパターン形成された短冊状のワイヤボンデイング用パ
ッド１４が各辺に沿って１列状に形成されており、集積
回路１２上面の各辺に形成されたワイヤボンデイング用
パッド１５との間をワイヤ１６でそれぞれにボンデイン
グ接続される。On the circuit board 11 around the ground pattern 13, strip-shaped wire bonding pads 14 having a pattern are formed in one row along each side, and are formed on each side of the upper surface of the integrated circuit 12. Wires 16 are connected to the bonded wire bonding pads 15 by bonding.

【００２８】回路基板１１上のワイヤボンデイング用パ
ッド１４に連成された円形状の部分は回路基板１１の内
層の回路導体パターン１７と接続された接続用のビアホ
ール１８部分である。The circular portion connected to the wire bonding pad 14 on the circuit board 11 is a via hole 18 for connection which is connected to the circuit conductor pattern 17 in the inner layer of the circuit board 11.

【００２９】図１の図（ａ）では、ワイヤボンデイング
接続される各辺の中央部分のワイヤ１６は、図が煩雑と
なることから図示省略して示してある。集積回路１２周
囲の接地パターン１３の各辺には方形状の凹凸１９形状
が形成されている。In FIG. 1A, the wire 16 in the central portion of each side to be wire-bonded is omitted because it is complicated. Square-shaped irregularities 19 are formed on each side of the ground pattern 13 around the integrated circuit 12.

【００３０】図（ｂ）の拡大図によく示されるように、
集積回路１２のワイヤボンデイング用パッド１５とワイ
ヤ１６で接続される回路基板１１側のワイヤボンデイン
グ用パッド１４とは、信号回路と電源回路とが適宜位置
に設定されるものであり、接地回路と接続される集積回
路１２側のワイヤボンデイング用パッド１５は、接地パ
ターン１３の周辺に形成された凹凸１９の凸部分とワイ
ヤ１６で接続させることができるから、最短距離で効率
よく接続される。As is often shown in the enlarged view of FIG.
The wire bonding pad 15 of the integrated circuit 12 and the wire bonding pad 14 on the side of the circuit board 11 connected by the wire 16 are used to set the signal circuit and the power supply circuit at appropriate positions and are connected to the ground circuit. Since the wire bonding pad 15 on the integrated circuit 12 side can be connected to the protruding portion of the unevenness 19 formed around the ground pattern 13 by the wire 16, the wire bonding pad 15 is efficiently connected in the shortest distance.

【００３１】この凹凸１９形状の凸部分の位置の設定は
以下のようにして決められるものである。すなわち、図
（ｂ）から明らかなように、集積回路１２側のワイヤボ
ンデイング用パッド１５と接続される回路基板１１側の
ワイヤボンデイング用パッド１４の隣接して接続される
それぞれのワイヤ１６，１６間の中間部分、好ましくは
中央部分に凸部分１９、それも、凸部分１９の接地ワイ
ヤ１６の接続されるべき部分が凸部分１９の中央部に位
置するように設定する。したがって、それぞれの凸部分
１９の隣接間の距離間隔は僅かずつ異なることになる。The setting of the position of the convex portion of the irregularity 19 shape is determined as follows. That is, as is apparent from FIG. 2B, the wire bonding pad 15 on the side of the integrated circuit 12 and the wire bonding pad 14 on the side of the circuit board 11 connected between the wires 16 and 16 connected adjacent to each other. In the middle part, preferably in the central part of the convex part 19, the convex part 19 is also set so that the part of the convex part 19 to which the ground wire 16 is connected is located in the central part of the convex part 19. Therefore, the distance between the adjacent convex portions 19 is slightly different.

【００３２】このように位置決めすることで平面視直線
状にワイヤ１６を接続させることができるから、それぞ
れ最短距離で、しかも凸部分１９の中央部に位置を設定
することで接続位置を容易かつ正確に位置決めすること
が可能となり、ワイヤボンデイング作業能率が向上す
る。Since the wires 16 can be connected linearly in a plan view by positioning in this way, the connection position can be easily and accurately set by setting the position at the shortest distance and at the center of the convex portion 19. It is possible to position the wire in the position, and the wire bonding work efficiency is improved.

【００３３】図（ｂ）で回路基板１１上の接地パターン
１３は集積回路１２の下面の接地回路電極と導電接続
（ダイボンド）されることは、すでに述べたとおりであ
るが、この接地パターン１３は回路基板１１を貫通する
導体であるビアホール２１により、回路基板１１裏面に
形状された導電層である接地パターン２２と導電接続さ
れており、裏面を接地回路として任意の所定パターンに
よる接地回路面としている。As described above, the ground pattern 13 on the circuit board 11 is conductively connected (die-bonded) to the ground circuit electrode on the lower surface of the integrated circuit 12 in FIG. Via holes 21 which are conductors penetrating the circuit board 11 are conductively connected to a ground pattern 22 which is a conductive layer formed on the back surface of the circuit board 11, and the back surface serves as a ground circuit and serves as a ground circuit surface according to an arbitrary predetermined pattern. .

【００３４】このビアホール２１は導電性とともに熱伝
導路として集積回路１２の動作にともなって生じる発熱
を、裏面の接地パターン２２に伝達させる働きをする。
したがって、裏面の接地パターン２２を図示しない集積
回路モジュール収容筐体に接触させることで、筐体に熱
伝達させ筐体から放熱させることが可能となる。また
は、公知な別の放熱装置に熱伝達をさせることであって
もよいことである。The via hole 21 has conductivity and serves as a heat conduction path to transmit heat generated by the operation of the integrated circuit 12 to the ground pattern 22 on the back surface.
Therefore, by bringing the ground pattern 22 on the back surface into contact with an integrated circuit module accommodating housing (not shown), heat can be transferred to the housing and radiated from the housing. Alternatively, the heat may be transferred to another known heat dissipation device.

【００３５】上記導電層１３，２２などはセラミックス
などの回路基板１１上に厚膜形成手段、たとえば印刷法
などにより、Ａｕペースト、あるいは他の適宜な導電体
を焼成し形成することで可能である。The conductive layers 13, 22 and the like can be formed by forming an Au paste or another appropriate conductor on the circuit board 11 made of ceramics or the like by a thick film forming means such as a printing method. .

【００３６】上記実施例では導電層を接地パターン１３
として説明したが、本発明の要旨によれば、かならずし
もこのような実施例にかぎらず、電源パターン１３とす
ることも可能である。この場合には、回路基板１１側の
ワイヤボンデイング用パッド１４の適宜箇所を接地回路
とすることとなる。また、裏面の導電層２２は電気的絶
縁体を介して放熱させることになる。In the above embodiment, the conductive layer is connected to the ground pattern 13
However, according to the gist of the present invention, the power supply pattern 13 is not limited to such an embodiment, and may be a power supply pattern 13. In this case, an appropriate portion of the wire bonding pad 14 on the side of the circuit board 11 will be the ground circuit. Further, the conductive layer 22 on the back surface radiates heat through the electrical insulator.

【００３７】本発明の第２実施例を図３の要部拡大図で
説明する。図３の図（ａ）によると、導電層である接地
パターン１３の凹凸１９ａを図１の凹凸１９よりも凹凸
の高さの程度を小さくしたものである。A second embodiment of the present invention will be described with reference to FIG. According to FIG. 3A, the unevenness 19a of the ground pattern 13, which is a conductive layer, is smaller in height than the unevenness 19 of FIG.

【００３８】このようにすることで凸部分１９ａの内部
で接続することなく、位置合わせの基準として平面部分
で接続させることができるから、ボンデイング作業を確
実に位置決めし安定して行なうことが可能となり、確実
な接続状態が得られる。By doing so, it is possible to connect at the flat portion as a reference for alignment without connecting inside the convex portion 19a, so that the bonding work can be reliably positioned and performed stably. A reliable connection state can be obtained.

【００３９】接続箇所を集積回路１２の周辺部分により
接近して行なうことも可能となることから、実装領域の
縮小化を図ることができる。もちろん、凸部分１９ａの
左右方向の中央部をめどに位置決めすることなどは前実
施例と同様である。また、電源パターンに適用し得るこ
となどはいうまでもなく同様なことである。Since it is possible to make the connection location closer to the peripheral portion of the integrated circuit 12, the mounting area can be reduced. Of course, such positioning it plans a central portion in the lateral direction of the convex portion 19a is similar to the previous embodiment. Needless to say, the same can be applied to the power supply pattern.

【００４０】図３の図（ｂ）によると、導電層である接
地パターン１３の凹凸１９ｂを方形状ではなく円弧状の
波形としたものである。凹凸の高さは任意に設定し得る
ものであるが、ワイヤ１６の接続箇所が凹凸パターンの
広がる方向で行なえることから、やはり同様にボンデイ
ング作業の位置決めを確実かつ安定して行なうことが可
能となり、正確な接続状態が得られる。その他について
も上記と同様である。According to the diagram (b) of FIG. 3, the irregularities 19b of the ground pattern 13 which is a conductive layer are not arcuate but arcuate. Although the height of the unevenness can be set arbitrarily, since the connection location of the wire 16 can be performed in the direction in which the unevenness pattern spreads, it is possible to similarly perform the positioning of the bonding work reliably and stably. , Accurate connection status can be obtained. Others are the same as above.

【００４１】図３の図（ｃ）によると、導電層である接
地パターン１３の凹凸１９ｃを山形で形成したものであ
る。凹凸の高さは任意に設定し得るものであるが、ワイ
ヤ１６の接続箇所が凹凸パターンのより広がる方向で行
なえることから、同様にボンデイング作業の位置決めを
確実かつ安定して行なうことが可能となる。その他の点
については上述と同様である。According to FIG. 3C, the unevenness 19c of the ground pattern 13 which is a conductive layer is formed in a mountain shape. The height of the unevenness can be set arbitrarily, but since the connection location of the wire 16 can be performed in the direction in which the unevenness pattern spreads out, similarly, it is possible to position the bonding work reliably and stably. Become. The other points are the same as above.

【００４２】図３に示される発明内容は、本発明にかか
るすべての発明実施例に適用し得るものであり、その作
用、効果についても同様なことである。図４に本発明の
第３実施例が示され、図（ａ）に平面図、図（ｂ）に要
部の拡大断面図、が示される。本実施例では理解を容易
とするために、集積回路１２を二点鎖線で示すとともに
回路筐体１１側のワイヤボンデイング用パッド１４は図
示省略してあるが、実際には存在するものである。The content of the invention shown in FIG. 3 can be applied to all the embodiments of the present invention, and the operation and effects thereof are also the same. FIG. 4 shows a third embodiment of the present invention, FIG. 4 (a) is a plan view, and FIG. 4 (b) is an enlarged sectional view of a main part. In the present embodiment, for ease of understanding, the integrated circuit 12 is shown by a chain double-dashed line and the wire bonding pad 14 on the side of the circuit housing 11 is not shown, but it is actually present.

【００４３】回路基板１１上に集積回路１２の下面から
その周辺に形成された導電層である接地パターン１３上
に集積回路１２の周囲を囲むような絶縁体からなる枠体
２５を、たとえばガラスペーストを印刷法により形成し
焼成硬化させたものである。A frame body 25 made of an insulating material and surrounding the integrated circuit 12 is provided on the ground pattern 13 which is a conductive layer formed on the circuit board 11 from the lower surface of the integrated circuit 12 to the periphery thereof. Is formed by a printing method and baked and cured.

【００４４】この枠体２５の外側には接地パターン１３
周囲の凹凸１９が形成されていることから、集積回路１
２下面の導電層を接続させる接着工程時の導電接着剤２
６の流出を阻止し、凹凸１９部分への無用の流出が防止
され、ワイヤ１６の接続が確実なものとなる以外に、凹
凸１９部分をワイヤ１６接続を可能とし得る状態の限度
位置まで枠体２５に接近させることができる。The ground pattern 13 is provided outside the frame 25.
Since the peripheral unevenness 19 is formed, the integrated circuit 1
2 Conductive adhesive 2 at the time of the bonding process for connecting the conductive layers on the lower surface
In addition to preventing unnecessary outflow to the concave and convex portion 19 and ensuring reliable connection of the wire 16, the concave and convex portion 19 can be connected to the wire 16 to a limit position where the wire 16 can be connected. 25 can be approached.

【００４５】この枠体２５形成領域は接地回路または電
源回路など同電位の導電層１３上であることから、絶縁
体に限らず導電体であっても差し支えないことである。
いずれにしても、導電性接着剤の流出を阻止させる目的
を達成し得る範囲で、できる限り高さを高くするととも
に、狭幅であることが好ましいものである。Since the region where the frame 25 is formed is on the conductive layer 13 of the same potential such as a ground circuit or a power supply circuit, it is not limited to an insulator and may be a conductor.
In any case, it is preferable that the height is as high as possible and the width is narrow within the range in which the purpose of preventing the conductive adhesive from flowing out can be achieved.

【００４６】図４に示される内容は、本発明のすべての
発明実施例に任意に組み合わせ適用実施可能なものであ
ることはいうまでもないことである。図５は本発明の第
４実施例であり、図（ａ）は平面図、図（ｂ）はその要
部拡大図、であり、側断面図が図６に示される。また、
図７には側断面図の要部を拡大した状態で詳細が示され
る。It goes without saying that the contents shown in FIG. 4 can be applied in any combination to all the embodiments of the present invention. 5A and 5B show a fourth embodiment of the present invention, FIG. 5A is a plan view, FIG. 5B is an enlarged view of a main part thereof, and a side sectional view is shown in FIG. Also,
FIG. 7 shows the details in a state in which a main portion of the side sectional view is enlarged.

【００４７】回路基板１１上には集積回路１２の下面よ
りも広く形成された集積回路１２搭載用の導電層である
接地パターン１３の上層、その下面に接地パターン１３
よりも広い絶縁層３１の中間層、さらにその下面に絶縁
層３１よりも広い導電層である電源パターン３２の下
層、がそれぞれ形成されている。An upper layer of the ground pattern 13, which is a conductive layer for mounting the integrated circuit 12 and is formed wider than the lower surface of the integrated circuit 12 on the circuit board 11, and the ground pattern 13 on the lower surface thereof.
An intermediate layer of the wider insulating layer 31 and a lower layer of the power supply pattern 32, which is a conductive layer wider than the insulating layer 31, are formed on the lower surface thereof.

【００４８】上層の接地パターン１３をダイパッドとし
て、その面上に集積回路１２の集積回路面の接地回路面
が導電接着剤２６によって導電接続（ダイボンド）され
搭載されている。The ground pattern 13 of the upper layer is used as a die pad, and the ground circuit surface of the integrated circuit surface of the integrated circuit 12 is mounted on the surface thereof by conductive connection (die bonding) with a conductive adhesive 26.

【００４９】下層の電源パターン３２周囲の回路基板１
１上にはパターン形成された短冊状のワイヤボンデイン
グ用パッド１４が各辺に沿って１列状に形成されてお
り、集積回路１２の上面の各辺に形成されたワイヤボン
デイング用パッド１５との間をワイヤ１６でそれぞれに
ボンデイング接続させる。Circuit board 1 around the lower power supply pattern 32
A strip-shaped wire bonding pad 14 formed into a pattern is formed in a row along each side on the upper surface of the integrated circuit 1. The wire bonding pad 15 and the wire bonding pad 15 formed on each side of the upper surface of the integrated circuit 12 are connected to each other. Bonding connections are made to each other with wires 16.

【００５０】回路基板１１上のワイヤボンデイング用パ
ッド１４に連成された円形状の部分は、回路基板１１の
内層の信号回路導体パターン１７と接続される接続用の
ビアホール１８部分である。The circular portion connected to the wire bonding pad 14 on the circuit board 11 is a connection via hole 18 portion connected to the signal circuit conductor pattern 17 in the inner layer of the circuit board 11.

【００５１】図５の図（ａ）では、ワイヤボンデイング
接続される各辺の中央部分のワイヤ１６は、図が煩雑と
なることから図示省略して示してある。集積回路１２周
囲の接地パターン１３の各辺には方形状の凹凸１９形状
が形成されており、電源パターン３２の各辺にも同様な
方形状の凹凸３３形状が形成されている。In FIG. 5A, the wire 16 in the central portion of each side to be wire-bonded is omitted because it is complicated. A rectangular unevenness 19 shape is formed on each side of the ground pattern 13 around the integrated circuit 12, and a similar rectangular unevenness 33 shape is also formed on each side of the power supply pattern 32.

【００５２】図５の図（ｂ）の拡大図によく示されるよ
うに、集積回路１２のワイヤボンデイング用パッド１５
とワイヤ１６で接続される回路基板１１側のワイヤボン
デイング用パッド１４は、信号回路の接続を行なうもの
であり、接地回路と接続される集積回路１２側のワイヤ
ボンデイング用パッド１５は、接地パターン１３の周辺
に形成された凹凸１９の凸部分とワイヤ１６で接続させ
る。また、電源回路と接続される集積回路１２側のワイ
ヤボンデイング用パッド１５は電源パターン３２の周辺
に形成された凹凸３３の凸部分とワイヤ１６でそれぞれ
接続させるから、それぞれが最短距離で効率よく接続さ
れる。As best shown in the enlarged view of FIG. 5B, the wire bonding pad 15 of the integrated circuit 12 is shown.
The wire bonding pad 14 on the side of the circuit board 11 connected with the wire 16 is for connecting the signal circuit, and the wire bonding pad 15 on the side of the integrated circuit 12 connected to the ground circuit is the ground pattern 13 The wire 16 is connected to the convex portion of the unevenness 19 formed around the area. Further, since the wire bonding pad 15 on the integrated circuit 12 side connected to the power supply circuit is connected to the convex portion of the unevenness 33 formed around the power supply pattern 32 by the wire 16, each is efficiently connected at the shortest distance. To be done.

【００５３】これらの凹凸１９，３３形状の凸部分の位
置の設定は以下のようにして決められるものである。す
なわち、図（ｂ）から明らかなように、集積回路１２の
ワイヤボンデイング用パッド１５と接続される回路基板
１１側のワイヤボンデイング用パッド１４の、隣接して
接続されるそれぞれのワイヤ１６，１６間の中間部分に
対して均等位置、好ましくは凸部分１９，３３の中央部
分にワイヤ１６の接続されるべき部分が位置するように
設定する。したがって、それぞれの凸部分１９，３３の
隣接間の距離間隔は僅かずつ異なることになる。The setting of the positions of the convex portions of the concave and convex portions 19 and 33 is determined as follows. That is, as is apparent from FIG. 2B, between the adjacent wires 16 of the wire bonding pad 14 on the side of the circuit board 11 connected to the wire bonding pad 15 of the integrated circuit 12. It is set so that the portion to be connected of the wire 16 is located at an equal position with respect to the intermediate portion of the wire, preferably in the central portion of the convex portions 19 and 33. Therefore, the distance between the adjacent convex portions 19 and 33 is slightly different.

【００５４】このように位置決めすることで平面視直線
状にワイヤ１６を接続させることができるから、それぞ
れ最短距離で、しかも凸部分１９，３３の中央部に位置
を設定することで接続位置を容易に位置決めすることが
可能となり、正確にしてワイヤボンデイング作業能率が
向上する。Since the wires 16 can be connected linearly in a plan view by positioning in this manner, the connection positions can be easily set by setting the positions at the shortest distances and in the central portions of the convex portions 19 and 33. It is possible to accurately position the wire to improve the wire bonding work efficiency.

【００５５】図５の図（ｂ）で回路基板１１上層の接地
パターン１３は集積回路１２の下面の接地回路電極と導
電接続されることは、すでに述べたとおりであるが、こ
の接地パターン１３は回路基板１１を貫通するビアホー
ル２１により、回路基板１１裏面に形成された接地パタ
ーン２２と導電接続されており、裏面を接地回路として
任意の所定パターンによる接地回路面としている。As described above, the ground pattern 13 on the upper layer of the circuit board 11 is conductively connected to the ground circuit electrode on the lower surface of the integrated circuit 12 in FIG. 5B. A via hole 21 penetrating the circuit board 11 is conductively connected to a ground pattern 22 formed on the back surface of the circuit board 11, and the back surface serves as a ground circuit and serves as a ground circuit surface having an arbitrary predetermined pattern.

【００５６】このビアホール２１は導電性とともに熱伝
導体として集積回路１２の動作にともなって生じる発熱
を裏面の接地パターン２２に伝達させる働きを示す。し
たがって、裏面の接地パターン２２を図示しない集積回
路モジュール収容筐体に接触させることで、筐体に熱伝
達させて筐体から放熱させることが可能となる。また
は、公知な別の放熱装置に熱伝達をさせることであって
もよいことである。The via hole 21 has a function of transmitting heat to the ground pattern 22 on the back surface as a heat conductor as well as being electrically conductive. Therefore, by bringing the ground pattern 22 on the back surface into contact with an unillustrated integrated circuit module housing, it is possible to transfer heat to the housing and dissipate heat from the housing. Alternatively, the heat may be transferred to another known heat dissipation device.

【００５７】図７から明らかなように、回路基板１１上
の下層の電源パターン３２は上層の接地パターン１３と
接触しないように、接地回路のビアホール２１の周囲は
絶縁層３１で囲まれ隔離されている。As is apparent from FIG. 7, the periphery of the via hole 21 of the ground circuit is surrounded and isolated by the insulating layer 31 so that the lower power supply pattern 32 on the circuit board 11 does not contact the upper ground pattern 13. There is.

【００５８】電源パターン３２は回路基板１１内部に延
びるビアホール３５により内層の電源回路パターン３６
と回路接続されている。上記それぞれの接地パターン１
３，２２、電源パターン３２などの導電層はセラミック
スなどの回路基板１１上に厚膜形成手段、たとえば印刷
法などにより、Ａｕペースト、あるいは他の適宜な導電
体を焼成することで可能であり、絶縁層についてもガラ
スペーストなどの絶縁体を印刷法で形成したものを焼成
することで可能である。これらを順次焼成積層しパター
ン形成させる。The power supply pattern 32 is a power supply circuit pattern 36 in the inner layer by a via hole 35 extending inside the circuit board 11.
It is connected to the circuit. Ground pattern 1 for each of the above
The conductive layers such as 3, 22 and the power supply pattern 32 can be formed by firing Au paste or another appropriate conductor on the circuit board 11 such as ceramics by a thick film forming means, for example, a printing method, The insulating layer can also be formed by baking an insulating material such as glass paste formed by a printing method. These are sequentially fired and laminated to form a pattern.

【００５９】上記実施例では上層を接地パターン１３、
下層を電源パターン３２として説明したが、本発明の要
旨によれば、かならずしもこのような実施例にかぎら
ず、上層を電源パターン３２、下層を接地パターン１３
とすることも可能である。この場合には、回路基板１１
裏面の接地パターンを電源パターン２２とすることにな
り、放熱に筐体を利用するためには熱伝導性が良好な電
気絶縁対策を施すことが必要である。In the above embodiment, the upper layer is the ground pattern 13,
Although the lower layer is described as the power supply pattern 32, according to the gist of the present invention, the upper layer is the power supply pattern 32 and the lower layer is the ground pattern 13 according to the present invention.
It is also possible to In this case, the circuit board 11
The ground pattern on the back surface is used as the power supply pattern 22, and in order to use the case for heat dissipation, it is necessary to take measures for electrical insulation with good thermal conductivity.

【００６０】本発明にかかる回路基板は多層基板に限定
されることなく、最低限両面基板に適用可能なものであ
る。The circuit board according to the present invention is not limited to a multi-layer board, but can be applied to at least a double-sided board.

【００６１】[0061]

【発明の効果】以上詳細に説明したように本発明の集積
回路モジュールによれば、ワイヤボンデイングによるワ
イヤ接続の高密度化を可能とするとともに、高品質かつ
ワイヤ接続の容易化を図り得る。As described in detail above, according to the integrated circuit module of the present invention, it is possible to increase the density of wire connection by wire bonding, and to achieve high quality and easy wire connection.

【００６２】第１の集積回路モジュールでは、回路基板
上の集積回路搭載領域に該集積回路よりも広面積な導電
層を形成させ、該導電層の周辺に集積回路のワイヤボン
デイング用パッドとワイヤ接続されるべき箇所に対応し
た凹凸を形成させ、該集積回路のワイヤボンデイング用
パッドと回路基板上の導電層の凹凸箇所とを対応させて
ワイヤボンデイングによりワイヤ接続させることによ
り、導電層である共通電位に対して最短距離で接続させ
ることができ、その分信号回路領域のワイヤボンデイン
グ用パッドの増加あるいは、間隔を広げることが可能で
あり、平坦面を十分に確保形成し得る。ワイヤの接続位
置は、凹凸位置に合わせることでボンデイング位置が正
確となるとともに位置決めが容易に行なえる。In the first integrated circuit module, a conductive layer having a larger area than that of the integrated circuit is formed in the integrated circuit mounting region on the circuit board, and the wire bonding pad and the wire connection of the integrated circuit are formed around the conductive layer. By forming unevenness corresponding to a portion to be formed and connecting the wire bonding pad of the integrated circuit and the uneven portion of the conductive layer on the circuit board by wire bonding by wire bonding, a common potential which is a conductive layer is formed. Can be connected at the shortest distance, and the number of wire bonding pads in the signal circuit area can be increased or the distance can be increased accordingly, and a sufficient flat surface can be formed. The bonding position of the wire can be adjusted accurately by aligning with the concavo-convex position so that the wire can be positioned easily.

【００６３】第２の集積回路モジュールでは、第１の集
積回路モジュールの周辺に形成される凹凸の凸部は、集
積回路のワイヤボンデイング用パッドからワイヤ接続さ
れる回路基板上のワイヤボンデイング用パッドの隣接間
の中間部分に形成させることで、集積回路のワイヤボン
デイング用パッドと回路基板上のワイヤボンデイング用
パッドとのワイヤ接続に応じて、中間部分の凹凸とのワ
イヤ接続を行なうことから、ワイヤどうしの交差などが
なくなりボンデイング接続が逐次順序よく能率的に行な
える。In the second integrated circuit module, the convex and concave portions formed around the first integrated circuit module have wire bonding pads on the circuit board which are wire-connected from the wire bonding pads of the integrated circuit. By forming it in the intermediate portion between adjacent wires, the wire connection between the wire bonding pad of the integrated circuit and the wire bonding pad on the circuit board is performed to connect the unevenness of the intermediate portion. Bonding connection can be done sequentially and efficiently without any crossing.

【００６４】第３の集積回路モジュールでは、第１の集
積回路モジュールの周辺に形成される導電層は電源パタ
ーンまたは接地パターンの少なくとも何れかであること
により、導電層は電源パターンおよび、もしくは接地パ
ターンとし得ることから共通電位である導電層の任意箇
所に設定接続させることが可能である。In the third integrated circuit module, the conductive layer formed around the first integrated circuit module is at least one of the power supply pattern and the ground pattern, so that the conductive layer has the power supply pattern and / or the ground pattern. Therefore, it is possible to set and connect to an arbitrary portion of the conductive layer having a common potential.

【００６５】第４の集積回路モジュールでは、第１およ
び第３の集積回路モジュールの周辺に凹凸の形成される
導電層は回路基板を貫通する導体により回路基板裏面の
導体層に接続されることから、電源回路あるいは接地回
路との効率的な接続が行なえ、その分信号回路のパター
ン配置が容易ないしは高密度かつ高品質な配置が行なえ
る。In the fourth integrated circuit module, the conductive layer having irregularities formed around the first and third integrated circuit modules is connected to the conductor layer on the back surface of the circuit board by the conductor penetrating the circuit board. Further, efficient connection with the power supply circuit or the ground circuit can be performed, and the pattern arrangement of the signal circuit can be facilitated by that much, or high-density and high-quality arrangement can be performed.

【００６６】第５の集積回路モジュールでは、第４の集
積回路モジュールの回路基板を貫通する導体は熱伝導体
とすることにより、集積回路からの発熱を回路基板裏面
から適宜な放熱手段を介して効率よく熱放散させること
ができる。In the fifth integrated circuit module, the conductor penetrating the circuit board of the fourth integrated circuit module is a heat conductor, so that the heat generated from the integrated circuit is transferred from the back surface of the circuit board through an appropriate heat dissipation means. It can dissipate heat efficiently.

【００６７】以上のように本発明によると種々の構成と
ともに集積回路モジュールの態様に応じ、きわめてすぐ
れた効果を奏するものである。As described above, according to the present invention, extremely excellent effects can be obtained depending on various configurations and aspects of the integrated circuit module.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明集積回路モジュールの第１実施例FIG. 1 is a first embodiment of an integrated circuit module of the present invention.

【図２】図１の側断面図FIG. 2 is a side sectional view of FIG.

【図３】本発明の第２実施例FIG. 3 is a second embodiment of the present invention.

【図４】本発明の第３実施例FIG. 4 is a third embodiment of the present invention.

【図５】本発明の第４実施例FIG. 5 is a fourth embodiment of the present invention.

【図６】図５の側断面図6 is a side sectional view of FIG.

【図７】第４実施例における回路基板の要部拡大断面図FIG. 7 is an enlarged cross-sectional view of a main part of a circuit board according to a fourth embodiment.

【図８】従来の集積回路モジュールの平面図FIG. 8 is a plan view of a conventional integrated circuit module.

【符号の説明】[Explanation of symbols]

１１ 回路基板 １２ 集積回路 １３ 導電層，接地パターン １４ ワイヤボンデイング用パッド １５ ワイヤボンデイング用パッド １６ ワイヤ １７ 内層の回路パターン，信号パターン １８ ビアホール １９ 凹凸，凸部分 ２１ ビアホール ２２ 導電層，接地パターン ２５ 枠体 ２６ 接着剤 ３１ 絶縁層 ３２ 導体層，電源パターン ３３ 凹凸，凸部分 ３５ ビアホール ３６ 電源回路パターン 11 Circuit Board 12 Integrated Circuit 13 Conductive Layer, Ground Pattern 14 Wire Bonding Pad 15 Wire Bonding Pad 16 Wire 17 Inner Layer Circuit Pattern, Signal Pattern 18 Via Hole 19 Concavo-convex and Convex 21 Via Hole 22 Conductive Layer, Ground Pattern 25 Frame Body 26 Adhesive 31 Insulating Layer 32 Conductor Layer, Power Supply Pattern 33 Concavities and Convexities 35 Via Hole 36 Power Supply Circuit Pattern

フロントページの続き (72)発明者 中島 奈々 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内Continued Front Page (72) Nana Nakajima Nana Nakajima 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 回路基板上の集積回路搭載領域に該集積
回路よりも広面積な導電層を形成するとともに該導電層
の周辺に集積回路のワイヤボンデイング用パッドとワイ
ヤ接続されるべき箇所に対応した凹凸が形成されてな
り、 上記集積回路のワイヤボンデイング用パッドと回路基板
上の導電層の凹凸箇所とを対応させてワイヤボンデイン
グによりワイヤ接続されることを特徴とした集積回路モ
ジュール。1. A conductive layer having a larger area than that of the integrated circuit is formed in an integrated circuit mounting region on a circuit board, and a portion to be wire-connected to a wire bonding pad of the integrated circuit is formed around the conductive layer. The integrated circuit module is characterized in that the wire bonding pads of the integrated circuit are connected to the bumps of the conductive layer on the circuit board by wire bonding. 【請求項２】 上記周辺に形成される凹凸の凸部は集積
回路のワイヤボンデイング用パッドからワイヤ接続され
る回路基板上のワイヤボンデイング用パッドの隣接間の
中間部分に形成されることを特徴とした請求項１に記載
の集積回路モジュール。2. The convex and concave portions formed on the periphery are formed in an intermediate portion between adjacent wire bonding pads on a circuit board which is wire-connected from the wire bonding pads of the integrated circuit. The integrated circuit module according to claim 1. 【請求項３】 上記周辺に凹凸の形成される導電パター
ンは電源パターンもしくは接地層の少なくとも何れかで
あることを特徴とした請求項１に記載の集積回路モジュ
ール。3. The integrated circuit module according to claim 1, wherein the conductive pattern having irregularities formed on the periphery is at least one of a power supply pattern and a ground layer. 【請求項４】 上記周辺に凹凸の形成される導電層は上
記回路基板を貫通する導体により該回路基板裏面の導電
層と接続されることを特徴とした請求項１および３に記
載の集積回路モジュール。4. The integrated circuit according to claim 1, wherein the conductive layer having irregularities formed on the periphery thereof is connected to the conductive layer on the back surface of the circuit board by a conductor penetrating the circuit board. module. 【請求項５】 上記回路基板を貫通する導体は熱伝導体
であることを特徴とした請求項４に記載の集積回路モジ
ュール。5. The integrated circuit module according to claim 4, wherein the conductor penetrating the circuit board is a heat conductor.
JP6181520A 1994-08-02 1994-08-02 Integrated circuit module Withdrawn JPH0845977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6181520A JPH0845977A (en) 1994-08-02 1994-08-02 Integrated circuit module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6181520A JPH0845977A (en) 1994-08-02 1994-08-02 Integrated circuit module

Publications (1)

Publication Number Publication Date
JPH0845977A true JPH0845977A (en) 1996-02-16

Family

ID=16102201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6181520A Withdrawn JPH0845977A (en) 1994-08-02 1994-08-02 Integrated circuit module

Country Status (1)

Country Link
JP (1) JPH0845977A (en)

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