JPH08340103A - Power semiconductor device - Google Patents

Abstract

PURPOSE: To improve the on-voltage, the safe-operating region and ratch-up strength of a power semiconductor device with IGBT. CONSTITUTION: A plurality of IGBT are provided on a power semiconductor device, and a gate electrode 6 and a source electrode 8 are arranged alternately. On the two adjacently located IGBT 101 and 102, the gate electrode 6 is located between the sources 8 and 8, and the sources 8 are located between the gate electrodes 6 and 6 in the two adjacently located IGBTs 102 and 103. When the width of the gate electrodes 6 is set at LC, the depth of a P-type base layer 3 is set at DB, the width of the N-type base layer 1 on the part where it is pitched by the P-type base layer 3 and the P-type emitter layer 1 is set at WB and the distance between the adjacent gate electrodes 6 is set at LS, and the condition of 60μm<=LG, 5<=LG/LS and 1<=LG<2> /(DB.WB)<=9 are satisfied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device for controlling high power.

[0002]

IG as a semiconductor circuit element for power control
There is BT (Insulated Gate Bipolar Transistor).
The IGBT is a new high breakdown voltage circuit element having both the high-speed switching characteristic of a power MOSFET and the high output characteristic of a bipolar transistor, and has been widely used in the field of power electronics such as an inverter and a switching power supply in recent years.

FIG. 18 is a sectional view showing a conventional IGBT. In FIG. 18, the P-type base layer 83 is selectively formed in the surface of the high-resistance N-type base layer 81. A low-resistance N-type source layer 84 is selectively formed in the surface of the P-type base layer 83. A gate electrode 86 is provided on the P-type base layer 83 sandwiched between the N-type source layer 84 and the N-type base layer 81 with the gate insulating film 85 interposed therebetween. The gate electrode 86 is a combination of the gate electrodes of two adjacent IGBTs. Further, the source electrode 88 is provided so as to contact both the N-type source layer 84 and the P-type base layer 83. On the other hand, a P-type emitter layer 82 is formed on the back surface of the N-type base layer 81. P-type emitter layer 82
A drain electrode 87 is provided on the top.

The operation of the IGBT thus constructed is as follows.
It is as follows. That is, at turn-on, a positive voltage (positive bias voltage) is applied to the gate electrode 86 with respect to the source electrode 88. When a positive bias voltage is applied to the gate electrode 86, the P-type base layer 8 below the gate electrode 86
N-type channels are formed in the surface of 3. This allows
The N-type source layer 84 and the N-type base layer 81 are short-circuited.

As a result, electrons are injected from the N-type source layer 84 into the N-type base layer 81, and an electron current flows, so that holes corresponding to the electron current flow from the P-type emitter layer 82 to the N-type base layer. Implanted in layer 81. As a result, the N-type base layer 81 undergoes conductivity modulation to have a low resistance, and a main current flows between the source and drain.

On the other hand, when turned off, the gate electrode 85
A zero or negative voltage (negative bias voltage) is applied to the source electrode 88. As a result, the N-type channel disappears, and electrons are no longer injected from the N-type emitter layer 84 into the N-type base layer 81. As a result, the N-type base layer 81
Does not cause conduction modulation, and eventually the IGBT becomes non-conductive.

By the way, this kind of IGBT has the following problems. That is, compared to a thyristor or the like, the IGBT has a smaller amount of carriers (electrons) injected from the cathode (source) side, and therefore has a higher on-voltage. The higher the breakdown voltage is, the thicker the substrate is, and the higher the on-voltage is.
When the thickness exceeds a certain level, the on-voltage becomes extremely high and the power loss becomes large. Therefore, the conventional I
The breakdown voltage of GBT is about 2 kV at most. Further, the distance between the gate electrodes is about the same as the width of the gate electrodes, and the saturation current is large, so that there is a problem that the IGBT is likely to latch up and become out of control.

[0008]

As described above, the conventional I
In the GBT, since the injection of carriers from the source side is small, the on-voltage is high. Further, since the distance between the gate electrodes is about the same as the gate electrode width, the latch-up withstand capability (current at which latch-up starts) decreases.

Therefore, an object of the present invention is to provide a power semiconductor device having a lower on-voltage than ever before. Another object of the present invention is to provide a power semiconductor device having improved on-voltage, safe operation area and latch-up withstanding capability as compared with the prior art. The invention also has a high breakdown voltage, especially 3 kV.
It is an object of the present invention to provide a power semiconductor device that can be used with the above withstand voltage specifications.

[0010]

The first aspect of the present invention is as follows.
A power semiconductor device having a plurality of circuit elements arranged in parallel, wherein each of the circuit elements has a first conductivity type emitter layer and a second conductivity type provided on the first conductivity type emitter layer. A base layer; a first conductivity type base layer formed in the surface of the second conductivity type base layer; a second conductivity type source layer formed in the surface of the first conductivity type base layer; Two
A gate electrode portion disposed on the first conductive type base layer sandwiched between the conductive type source layer and the second conductive type base layer with a gate insulating film interposed therebetween, the second conductive type source layer, and the A source electrode portion contacting the first conductivity type base layer; and a drain electrode portion contacting the first conductivity type emitter layer, wherein the gate electrode portion is integrated for every two circuit elements of the circuit element. To form a gate electrode, the width of the gate electrode is L _G , the depth of the first conductivity type base layer is D _B , and the gate electrode is sandwiched between the first conductivity type base layer and the first conductivity type emitter layer. The second part of the broken part
When the thickness of the conductive type base layer is W _B and the distance between the gate electrodes is L _S , 60 μm ≦ L _G , 5 ≦ L _G / L _S , and 1 ≦ L _G ² / (D _B · W _B ) ≦ 9 is satisfied.

A second aspect of the present invention is, in the power semiconductor device according to the first aspect, a second low resistance formed in the surface of the second conductivity type base layer and under the gate electrode. It is characterized by further comprising a conductive type semiconductor layer.

A third aspect of the present invention is a power semiconductor device having a plurality of circuit elements arranged in parallel, wherein each of the circuit elements has a first conductivity type emitter layer and the first conductivity type. A second conductivity type base layer disposed on the emitter layer, a first conductivity type base layer formed in the surface of the second conductivity type base layer, and a surface formed of the first conductivity type base layer. A second conductive type source layer, and a gate disposed on the first conductive type base layer sandwiched between the second conductive type source layer and the second conductive type base layer via a gate insulating film. An electrode portion, a source electrode portion contacting the second conductive type source layer and the first conductive type base layer, and a drain electrode portion contacting the first conductive type emitter layer,
A high mobility semiconductor layer formed in the surface of the first conductivity type base layer sandwiched between the second conductivity type base layer and the second conductivity type source layer.

A fourth aspect of the present invention is the power semiconductor device according to the third aspect, wherein the gate electrode portion is integrated with every two circuit elements of the circuit element to form a gate electrode, When the width of the gate electrode is L _G and the distance between the gate electrodes is L _S , 60 μm ≦ L _G , and 5
It is characterized in that the condition of ≦ L _G / L _S is satisfied.

A fifth aspect of the present invention is the power semiconductor device according to the fourth aspect, wherein the depth of the first conductive type base layer is D _B , the first conductive type base layer and the first conductive type base layer. When the thickness of the second conductivity type base layer sandwiched by the type emitter layer is W _B , 1 ≦ L _G ² / (D _B · W _B ) ≦
It is characterized in that the condition 9 is satisfied.

The peak value of the impurity concentration of the low-resistance second conductivity type semiconductor layer may be 3 × 10 ¹⁴ cm ⁻³ or more, and more preferably 1 × 10 ¹⁵ cm ⁻³ or more.
In addition, the depth (thickness) of the low resistance second conductivity type semiconductor layer
May be 1/2 or more of the depth (thickness) of the first conductivity type base layer, but is preferably the same as the depth (thickness) of the first conductivity type base layer.

According to the research conducted by the present inventor, 60 μm ≦ L
_G, by setting ^{_{1 ≦ L G 2 / (D}} B · W B) ≦ 9, it was found that attained a decrease in the ON voltage. Also,
By using the recent fine processing technology, L _G can be sufficiently reduced L _S against _{(5 ≦ L G / L S} ), thereby, without increasing the on-voltage, a latch-up current saturation current It has been found that the following can be suppressed and the safe operation area can be expanded. Therefore, according to the first and second aspects of the present invention based on the above findings,
The on-voltage decreases and the safe operating area expands.

Further, according to the third to fifth aspects of the present invention, the carrier on the source side is injected into the first conductivity type base layer through the high mobility semiconductor layer, so that the carrier is conventionally formed. Is rapidly injected into the first conductive type base layer. Therefore, the amount of carriers injected into the first conductive type base layer per unit time increases, and the carrier injection efficiency increases, so that the on-voltage can be lowered as compared with the conventional case.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the first conductivity type is P type and the second conductivity type is N type. FIG.
FIG. 3 is a sectional view showing a main part (IGBT part) of a power semiconductor device according to an embodiment of the present invention. The power semiconductor device of this embodiment includes a plurality of IGBTs (circuit elements) arranged side by side. Gate electrodes 6 of these IGBTs
The source electrodes 8 are alternately arranged. As shown in FIG. 1, when attention is paid to one IGBT 102, its gate electrode portion 6b is adjacent to another IGBT 101 on one side.
The gate electrode 6 is formed integrally with the gate electrode portion 6a of the above, and the source electrode portion 8b is formed integrally with the source electrode portion 8c of another IGBT 103 adjacent to the other side to form the source electrode 8. Therefore, two adjacent IGs
In the BTs 101 and 102, the gate electrode 6 is the IGB.
In two adjacent IGBTs 102, 103 located between the source electrodes 8, 8 of T101, 102, the source electrode 8 is the gate electrode 6, of the IGBTs 102, 103,
It will be located between 6.

In FIG. 1, a P-type emitter layer 2 is selectively formed in the back surface of a high-resistance N-type base layer 1. A low resistance N-type diffusion layer 9 is formed in the surface of the N-type base layer 1. The P-type base layer 3 is selectively formed in the surface of the N-type diffusion layer 9. In other words, the low resistance N-type diffusion layer 9 is formed in the surface of the N-type base layer 1 immediately below the gate electrode 6 between the adjacent P-type base layers 3.

It is appropriate that the depth of the low resistance N type diffusion layer 9 is the same as that of the P type base layer 3 as shown in FIG. However, this may be at least deeper than half the depth of the P-type base layer 3.

Within the surface of the P-type base layer 3, N of low resistance is
The mold source layer 4 is selectively formed. On the P-type base layer 3 sandwiched between the N-type source layer 4 and the N-type base layer 1 (N-type diffusion layer 9), the gate electrode 6 is provided via the gate insulating film 5.
Is arranged. Further, the source electrode 8 is arranged so as to contact both the N-type source layer 4 and the P-type base layer 3.

Here, one gate electrode 6 shown in the center of FIG. 1 functions as a gate electrode of two adjacent IGBTs 101 and 102. That is, the IGBTs 101, 1
The gate electrodes 6a and 6b of 02 extend from the P-type base layer 3 to the N-type base layer 1 (N-type diffusion layer 9) and are integrated.

On the other hand, the drain electrode 7 is arranged so as to contact the P-type emitter layer 2. According to the power semiconductor device having such a configuration, the N-type diffusion layer 9 promotes injection of electrons, so that the on-voltage can be lowered.

Here, the peak value of the impurity concentration of the N-type diffusion layer 9 is preferably 3 × 10 ¹⁴ cm ^-3 or more. In particular, in the case of an N-type channel IGBT as in this embodiment, 1
× 10 ¹⁵ cm ^-3 or more is desirable. Further, the impurity concentration should not exceed the peak value of the impurity concentration of the P-type base layer 3 immediately below the N-type source layer 4.

The above value (1 × 10 ¹⁵ cm ^-3 ) is obtained from the following equation. The hole density n _h inside the N-type base layer 1 can be expressed by the following equation. n _h = N _p · exp (W _B / (D _h · τ) ^1/2 ), where N _p is the peak value of the impurity concentration of the P-type emitter layer 2, and W _B is the P-type base layer 3 and P-type The thickness of the N-type base layer 1 in the portion sandwiched by the emitter layer 2, D _h is the diffusion coefficient of holes, and τ is the carrier lifetime in the high injection state.

If the peak value of the impurity concentration of the N-type diffusion layer 9 is not higher than the hole density n _h , the N-type diffusion layer 9 will be filled with holes. Therefore, when the peak value of the impurity concentration of the N-type diffusion layer 9 is smaller than the hole density n _h , carriers cannot be sufficiently injected, and the conduction characteristics of the IGBT cannot be improved.

On the other hand, when the peak value of the impurity concentration of the N-type diffusion layer 9 is higher than the hole density n _h , the N-type diffusion layer 9 acts as an emitter for holes and the electron injection efficiency. Will increase. Each parameter is almost uniquely determined by the device structure and usage conditions, but its value is about 1 × 10 ¹⁵ cm ^-3.
And the above value is obtained.

In the case of a P-type channel IGBT, the low-resistance N-type diffusion layer 9 becomes a low-resistance P-type diffusion layer, and the peak value of the impurity concentration is preferably 3 × 10 ¹⁴ cm ^-3 or more. .

The width L _G of the gate electrode 6 is an important parameter for determining the conduction characteristics of the IGBT. If the width L _G of the gate electrode 6 is too long, not only the channel density of the IGBT is lowered and the conduction characteristics are deteriorated, but also problems such as an increase in gate capacitance, an increase in cost, and deterioration of controllability may occur. is there.

On the other hand, if the width L _G of the gate electrode 6 is too short, the holes injected from the P-type drain layer 2 are bypassed to the P-type base layer 3 and are not accumulated in the high-resistance N-type base layer 1. , The conduction characteristics deteriorate.

According to the research conducted by the present inventor, in order to improve the channel density and carrier accumulation and lower the ON voltage,
Regardless of the presence or absence of the N-type diffusion layer 9, the width L _{G of the} gate electrode 6
It has been found that it suffices to design so as to satisfy the following inequalities.

1 ≦ L _G ² / (D _B · W _B ), where D _B represents the depth of the P-type base layer 3. This inequality is obtained as follows.

IGBT in the state where conductivity modulation occurs
The density of the current i is expressed by _{i = q · n · V F} · (μ e + μ h) / W B ... (1).

Here, q is the elementary charge amount, n is the carrier density of electrons and holes, V _F is the on-voltage, μ _e is the electron mobility, and μ _h is the hole mobility. The sheet resistance R of the effective P-type base layer 3 at the time of conduction is expressed by R = 1 / (q · μ h · n · D B) ... (2).

[0035] Since the voltage drop of the positive hole current due to the sheet resistance R may be equal to or higher than the junction voltage _{V j, i · R · L} G 2/32 ≧ V j ... (3) become.

By using the equations (1) to (3), it is expressed as L _G ² / (D _B · W _B ) ≧ 32 V _j · μ _h / (V _F · (μ _e + μ _h )). (4) If silicon is used as the device material, μ
Considering that _h / (μ _e + μ _h ) is about 0.25, V _j is about 0.6 V, and V _F is about 4 V in the range where a power semiconductor device is normally used, (4) is 1 ≦ L _G ² / (D _B · W _B ).

On the other hand, if the value of L _G ² / (D _B · W _B ) is too large, the number of channels decreases and the conduction characteristic also deteriorates, as shown in FIG. According to the presently obtained knowledge according to FIG. 10, it is necessary to prevent L _G ² /
The value of (D _B · W _B ) should be set so as not to exceed 9. Therefore, it is preferable to set 1 ≦ L _G ² / (D _B · W _B ) ≦ 9.

If L _G is too short, holes are easily bypassed and carriers are less likely to accumulate. In particular, in the case of a device having a withstand voltage exceeding 3 kV, this is a fatal defect in terms of energization characteristics. According to the experiments conducted by the present inventor, it has been found that carrier accumulation occurs in combination with the above conditions when L _G has a length of about 60 μm or more. Furthermore, according to the experiments of the present inventor, 2 ≦ L _G /
It has been found that latch-up is unlikely to occur when L _S , preferably 5 ≦ L _G / L _S is set. Here, L _S represents the distance between adjacent gate electrodes 6. This means that the semiconductor device is resistant to breakage and the safe operation area can be expanded, so that the protection circuit can be simplified.

In the present embodiment, unlike the conventional case, since L _G is considerably larger than L _S , the saturation current can be easily suppressed to be lower than the latch-up current. Although this is not possible with the process technology of the element such as IGBT which has been frequently used conventionally, such a design is possible by the fine processing technology using the step device which has been remarkably developed in recent years.

Further, in this embodiment, since the ON voltage and the safe operation area are improved by optimizing the parameters, it is not necessary to introduce a new structure. Therefore, the number of steps does not increase, the process does not become complicated, and the manufacturing cost does not increase.

FIG. 2 is a sectional view showing a main part (IGBT part) of a power semiconductor device according to another embodiment of the present invention. In the following drawings, the same symbols as those in FIG. 1 indicate the same parts, and detailed description thereof will be omitted.

The feature of this embodiment is that the thickness of the central portion 10 of the gate insulating film 5 is thicker than the other portions. As a result, the gate capacitance can be reduced, and the gate drive circuit can be simplified and operated at high speed.

It is desirable that the N-type diffusion layer 9 is uniformly provided under the gate electrode 6 as in the embodiment shown in FIG. However, if this is difficult due to process restrictions, it can be changed as in the embodiment shown in FIG. Here, the N-type diffusion layer 9 is not formed below the center of the gate electrode 6 apart from the N-type channel region, but is formed only near the N-type channel region. Even with this, the effect of lowering the on-voltage can be obtained.

FIG. 3 is a sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. This embodiment is different from the embodiment shown in FIG. 2 in that the N-type diffusion layer 9 is formed under the entire gate electrode 6. However, the N-type diffusion layer 9 is not arranged uniformly unlike the case of the embodiment shown in FIG. That is, N
The thickness of the central portion of the mold diffusion layer 9 is thinner than the other portions.

Such a structure is obtained as follows, for example. That is, the width of the central portion 10 of the gate insulating film 5 is narrowed, N-type impurities are ion-implanted using the gate insulating film 5 as a mask, and then heat treatment (annealing treatment) is performed. By doing so, the N-type impurity is diffused even under the central portion 10 of the gate insulating film 5, so that the N-type diffusion layer 9 can be formed under the entire gate electrode 6.

In the embodiment shown in FIG. 3, compared with the embodiment shown in FIG. 2, the gate capacitance is slightly increased as the width of the central portion 10 of the gate insulating film 5 is narrower. However, according to the research conducted by the present inventor, even in this case, it has been found that if the N-type diffusion layer 9 is provided under the entire gate electrode 6, the conduction characteristic is improved.

FIG. 4 is a sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. In order to secure a high breakdown voltage, for example, a breakdown voltage of 2 kV or more, the width L _G of the gate electrode 6 is 30 μm or more and 3 k or more.
To secure a withstand voltage of V or more, the width L of the gate electrode 6
_G is set to 60 μm or more. When the area of the gate electrode 6 is increased in this way, it becomes easy to form the metal electrode 12 such as an Al electrode on the gate electrode 6 as shown in FIG.

Therefore, the gate electrode 6 is usually formed only of polysilicon, but the metal electrode 12 is formed on the gate electrode 6.
By providing, the gate resistance is reduced and high speed operation becomes possible. Also, the gate drive circuit can be simplified.

FIG. 5 is a sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. This embodiment is different from the embodiment shown in FIG. 1 in that a part of the N-type base layer 1 is selectively connected to the drain electrode 7. That is, in the present embodiment, the anode short structure is adopted.

According to the present embodiment, the injection of holes from the drain side can be suppressed by the anode short structure, so that the tail current at turn-off can be particularly reduced,
The turn-off loss can be reduced. As a result, the power loss can be kept small even if the switching frequency is increased, and the device such as the inverter can be efficiently operated. Moreover, noise can be reduced by increasing the switching frequency.

Even if the efficiency of carrier injection from the drain side is lowered due to the anode short structure, the efficiency of carrier injection from the source side is higher than before due to the parameter optimization and the N-type diffusion layer 9. Therefore, the on-voltage is kept low.

FIG. 6 is a sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. This embodiment is different from the embodiment shown in FIG. 1 in that the lifetime reduction layer 13 is formed. The lifetime reduction layer 13 can be formed by, for example, diffusing a heavy metal such as Au or Pt or irradiating with radiation such as H or He. Also, lifetime reduction using electron beam irradiation may be used in combination therewith. As shown in FIG. 6, especially P
If the lifetime reduction layer 13 is formed in the N-type base layer 1 in the vicinity of the boundary between the N-type base layer 1 and the N-type emitter layer 2,
Injection of holes from the drain side can be effectively suppressed, and the same effect as that of the embodiment shown in FIG. 5 that employs the anode short structure can be obtained.

FIG. 7 is a sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. The present embodiment differs from the embodiment shown in FIG. 6 in that a low resistance N type buffer layer 14 is provided between the P type emitter layer 2 and the high resistance N type base layer 1. By disposing the N-type buffer layer 14, the N-type base layer 1
Can be thinned. Thereby, discharge of carriers at the time of switching can be accelerated, and switching can be performed at high speed. It is desirable that the total amount of impurities in the N-type buffer layer 14 is 1 × 10 ¹⁴ cm ⁻² or less. If the amount of impurities is larger than this, injection of holes from the drain is significantly suppressed, and the current-carrying characteristics are deteriorated.

Further, the lifetime reduction layer 13 is formed in the N-type base layer 1 in the vicinity of the boundary between the N-type buffer layer 14 and the N-type base layer 1. This makes it possible to suppress injection of holes from the drain side, reduce switching loss without deteriorating energization characteristics, and perform high-speed switching.

FIG. 8 is a sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. The present embodiment differs from the embodiment shown in FIG. 1 in that the low resistance N-type diffusion layer 9 is not formed under the gate electrode 6. Even when the N-type diffusion layer 9 is not provided, the above-mentioned 1 ≦ L _G ² / (D _B · W _B ) ≦ 9 and 2 ≦ L _G
By designing to satisfy the condition of / L _S , preferably 5 ≦ L _G / L _S , the on-voltage, safe operation area and latch-up withstand capability of the device can be improved.

FIG. 9 is a sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. This embodiment is different from the embodiments shown in FIGS. 1 to 8 in that the parameters are optimized and the low resistance N-type diffusion layer 9 is used.
Instead, the high mobility semiconductor layer 11 is used to increase the injection of electrons on the source side and lower the on-voltage.

The high-mobility semiconductor layer 11 is formed in advance on the surface of the N-type base layer 1 by a film-forming method such as an epitaxial growth method before forming layers such as the P-type base layer 3 and the N-type source layer 4. Form.

As the material of the high mobility semiconductor layer 11, for example, when Si is used as the material of the N-type base layer 1,
Examples include SiGe, amorphous Si, and SiC. According to the present embodiment, since the high mobility semiconductor layer 11 exists in the N type channel region, the electrons on the source side are injected into the N type base layer 1 through the high mobility semiconductor layer 11. .

Therefore, electrons are injected into the N-type base layer 1 faster than in the conventional case, and the amount of electrons injected into the N-type base layer 1 per unit time increases, so that the electron injection efficiency increases, The on-voltage drops.

In this embodiment, the N-type base layer 1
The high-mobility semiconductor layer 11 is formed on the entire surface of the substrate, but this is not necessary.
It only needs to exist within the surface of the P-type base layer 3 sandwiched between the type source layer 4 and the N-type base layer 1, that is, in the N-type channel region. Further, the impurity concentration of the high mobility semiconductor layer 11 at this time is preferably lower than 1 × 10 ¹⁸ cm ⁻³ for channel formation. Furthermore, the film thickness of the high-mobility semiconductor layer 11 is 0.05 μm in consideration of problems such as lattice mismatch.
The following is preferred.

In addition, after using the high-mobility semiconductor layer 11, the above-mentioned 1 ≦ L _G ² / (D _B · W _B ) ≦ 9 and
By designing to satisfy the condition of 2 ≦ L _G / L _S , preferably 5 ≦ L _G / L _S , the ON voltage can be further lowered, and the safe operation area can be widened because the IGBT does not latch up. You can

Next, the planar layout of the power semiconductor device according to the present invention will be described with reference to FIGS. The layout shown in FIGS. 11 to 16 is similar to that shown in FIG.
9 to any of the cross sections shown in FIG. Therefore, as in the embodiment shown in FIGS. 8 and 9,
When the low resistance N type diffusion layer 9 does not exist, the portion indicated by reference numeral 9 in FIGS. 11 to 16 should be understood as the high resistance N type base layer 1.

FIG. 11 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. The feature of this embodiment is that the N-type source layer 4 is formed in a comb shape. The thin portion of the N-type source layer 4 corresponding to the teeth of the comb contacts the source electrode 8, and the portion corresponding to the back of the comb forms the MOSFET region together with the gate electrode 6.

According to the present embodiment, the portion of the N-type source layer 4 corresponding to the teeth of the comb acts as a resistor, so that the resistor is provided between the source electrode 8 and the MOSFET. , The operation of the MOSFET becomes stable.

Further, by using the comb shape as the pattern of the N-type source layer 4, the area of the N-type source layer 4 can be made smaller than that in the case of using the stripe-shaped pattern of the normal size, and the latch-up resistance can be improved. Can be raised.

FIG. 12 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. The present embodiment differs from the embodiment shown in FIG. 11 in that the N-type source layer 4 is formed in a ladder shape. Even if the pattern of the N-type source layer 4 is formed in a ladder shape in this way, the latch-up withstand capability can be increased as in the embodiment shown in FIG. In addition, the N-type source layer 4 is the source electrode 8
As a result, the contact between the N-type source layer 4 and the source electrode 8 becomes more reliable than in the embodiment shown in FIG.

Further, in the present embodiment, the width of the source electrode 8 is narrowed and the distance L _S between the gate electrodes is shortened, so that the element region can be effectively utilized. FIG. 13 shows a main part (IG) of a power semiconductor device according to still another embodiment of the present invention.
It is a top view which shows the (BT part).

The present embodiment differs from the embodiment shown in FIG. 12 in that the N-type source layer 4 formed as an independent island is used.
It is because there are a plurality of ladders corresponding to each step of the ladder. Even if the N-type source layer 4 is formed in this way,
As with the embodiment shown in FIG. 12, the latch-up withstand capability can be increased. Moreover, since the distance L _S between the adjacent gate electrodes 6 can be reduced, the element region can be effectively used.

FIG. 14 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. This embodiment is different from the embodiment shown in FIG. 11 in that the N-type source layer 4 is formed in a stripe shape having an extremely narrow width by using a recent fine processing technique (fine dry etching technique). . According to this embodiment,
Since the width of the N-type source layer 4 is narrow, a high latch-up resistance can be realized even in the stripe shape.

FIG. 15 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. A feature of this embodiment is that a plurality of P-type base layers 3 formed as independent rectangular islands are arranged periodically and in a matrix. The N-type source layer 4 is formed in a cross shape so as not to easily cause latch-up, and an opening is provided in the center thereof, and the source electrode 8 contacts the P-type base layer 3 through this opening. are doing. With such a layout, the device can be highly integrated and the conduction characteristics can be improved.

FIG. 16 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention. A feature of this embodiment is that a plurality of P-type base layers 3 formed as independent hexagonal islands are arranged periodically and in a matrix. The N-type source layer 4 is formed in a star shape so as not to easily cause latch-up, and an opening is provided in the center thereof, and the source electrode 8 contacts the P-type base layer 3 through this opening. are doing. With such a layout, the device can be highly integrated and the conduction characteristics can be improved.

FIG. 17 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention. The present embodiment has an IGBT 105 according to the present invention, and a freewheel diode 106 and a junction terminating portion 107 arranged adjacent to the IGBT 105. By forming the switching element 105 and the diode 106 on the same substrate at the same time, inductance and capacitance due to wiring can be reduced, and switching can be performed at high speed and stably.

The diode 106 has a P-type anode layer 16 and an N-type cathode layer 18 connected to the source electrode 8 and the drain electrode 7 of the IGBT 105, respectively. The P-type anode layer 16 and the N-type cathode layer 18 are connected via the high-resistance N-type layer 1 and the low-resistance N-type buffer layer 14.

At the end of the junction termination portion 107, the N-type stopper layer 19 is diffused and formed in the surface of the N-type layer 1. P
An insulating film 20 is formed on the surface of the junction terminating portion 107 from the type anode layer 16 to the N type stopper layer 19.

It is necessary that the IGBT 105 and the diode 106 have a sufficient distance (length longer than the diffusion length of carriers). Therefore, the electric field may be concentrated on the surface of the region between the IGBT 105 and the diode 106, and the breakdown voltage may deteriorate. To address this issue, the IGBT 105
A high resistance P-type diffusion layer 17 is disposed between the P-type base layer 3 and the P-type anode layer 16 of the diode 106. P
The type diffusion layer 17 can be formed at the same time as the P-type diffusion layer 17 of the junction terminating portion 107, and therefore, it is not necessary to add an extra forming step.

The total amount of impurities in the P type diffusion layer 17 is 1 × 10 ^14.
It is preferably cm ⁻² or less. As a result, the breakdown voltage in the junction termination portion 107 is maintained good and the IGB
The T105 and the diode 106 can be sufficiently separated.

As described above, according to the present invention, it is possible to provide the power semiconductor device having the excellent current-carrying characteristics by the optimum design of the structure and the concentration. In particular, currently GTO (Ga
te Turn-off Thyristor) is used withstand voltage 3kV
In the above, a device that can be controlled by MOS driving can be provided.

This device has a parasitic thyristor structure,
Since it does not latch up and is strong against destruction, GTO
The protection circuit can be simplified as compared with. Since the gate circuit and the protection circuit can be simplified as compared with the GTO, the system size can be reduced, and for example, when an inverter device is created, the size can be half that of the conventional one. Further, since the device structure is a planar (planar) type, it is easy to form a current take-out portion, and the device can be incorporated into various packages.

[0079]

According to the present invention, 60 μm ≦ L _G , 5 ≦
By designing to satisfy the conditions of L _G / L _S and 1 ≦ L _G ² / (D _B · W _B ) ≦ 9, the on-voltage of the device is reduced, the safe operation area is expanded, and the latch-up withstand capability is increased. It is possible to increase.

Further, according to the present invention, by forming the high mobility semiconductor layer in the surface of the first conductivity type base layer sandwiched between the second conductivity type base layer and the second conductivity type source layer,
It is possible to increase the carrier injection efficiency by increasing the amount of carriers injected into the first conductivity type base layer per unit time and reduce the on-voltage of the device.

[Brief description of drawings]

FIG. 1 is a sectional view showing a main part of a power semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a main part of a power semiconductor device according to another embodiment of the present invention.

FIG. 3 is a sectional view showing an essential part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 4 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 5 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 6 is a sectional view showing an essential part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 7 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 8 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 9 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 10 is a characteristic diagram showing a relationship between {L _G ² / (D _B · W _B )} ^1/2 and ON voltage V _F.

FIG. 11 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 12 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 13 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 14 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 15 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 16 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 17 is a sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.

FIG. 18 is a sectional view showing a conventional IGBT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... N type base layer (2nd conductivity type base layer) 2 ... P type emitter layer (1st conductivity type emitter layer) 3 ... P type base layer (1st conductivity type base layer) 4 ... N type source Layer (second conductive type source layer) 5 ... Gate insulating film 6 ... Gate electrode 7 ... Drain electrode 8 ... Source electrode 9 ... N-type diffusion layer (second conductive type semiconductor layer) 10 ... Thick film portion 11 ... High Mobility semiconductor layer

Claims (5)

[Claims] 1. A power semiconductor device having a plurality of circuit elements arranged in parallel, wherein each of the circuit elements is disposed on a first conductivity type emitter layer and on the first conductivity type emitter layer. A second conductive type base layer, a first conductive type base layer formed in the surface of the second conductive type base layer, and a second conductive type source formed in the surface of the first conductive type base layer. A layer, a gate electrode portion disposed on the first conductivity type base layer sandwiched between the second conductivity type source layer and the second conductivity type base layer via a gate insulating film, and the second A source electrode portion in contact with the conductive type source layer and the first conductive type base layer; and a drain electrode portion in contact with the first conductive type emitter layer, wherein the gate electrode portion includes 2 of the circuit element. Integrated into each circuit element Constitutes an electrode, the width of the gate electrode L _G, the depth of the first conductivity type base layer D _B,
The thickness of the second conductive type base layer sandwiched between the first conductive type base layer and the first conductive type emitter layer is W.
_B , 60 μm when the distance between the gate electrodes is L _S
≤ L _G , 5 ≤ L _G / L _S , and 1 ≤ L _G ² / (D _B · W
_B ) A power semiconductor device, which satisfies the condition of ≤9. 2. The low-resistance second-conductivity-type semiconductor layer formed in the surface of the second-conductivity-type base layer and below the gate electrode, according to claim 1. Power semiconductor devices. 3. A power semiconductor device having a plurality of circuit elements arranged in parallel, wherein each of the circuit elements is arranged on a first conductivity type emitter layer and on the first conductivity type emitter layer. A second conductive type base layer, a first conductive type base layer formed in the surface of the second conductive type base layer, and a second conductive type source formed in the surface of the first conductive type base layer. A layer, a gate electrode portion disposed on the first conductivity type base layer sandwiched between the second conductivity type source layer and the second conductivity type base layer via a gate insulating film, and the second A source electrode portion contacting the conductive type source layer and the first conductive type base layer, a drain electrode portion contacting the first conductive type emitter layer, the second conductive type base layer and the second conductive type source layer. Of the first conductivity type base layer sandwiched between Power semiconductor device characterized by comprising a high mobility semiconductor layer formed in the plane, the. 4. The gate electrode portion is formed of 2 of the circuit element.
Each circuit element is integrated to form a gate electrode,
4. The condition of 60 μm ≦ L _G and 5 ≦ L _G / L _S are satisfied, where L _{G is} the width of the gate electrode and L _S is the distance between the gate electrodes. Power semiconductor devices. 5. The depth of the first-conductivity-type base layer is D _B , and the thickness of the second-conductivity-type base layer sandwiched between the first-conductivity-type base layer and the first-conductivity-type emitter layer. is a when a ^{_{W B, 1 ≦ L G 2}} / (D B · W B) the power semiconductor device according to claim 4, wherein the condition is satisfied in ≦ 9.