JPH08340081A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To provide an inexpensive, highly reliable, and high-added-value semiconductor device having a composite function by combining single-function semiconductor chips in a small-sized package. CONSTITUTION: After semiconductor chips 2 and 3 are stacked upon another with an organic insulating film 12 in between and the chips 2 and 3 are fixed to the die pad 9 of a lead frame, electrode terminals 5 on the main surfaces of the chips 2 and 3 are connected to the inner leads 7 of the lead frame and to each other through metallic thin wires 8 and the chips 2 and 3, lead frame, and leads 7 are encapsulated with a sealing resin into the external size of a package 4. Then outer leads 11 are plated and molded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor chips are stacked to have a composite function and a manufacturing method thereof.

[0002]

2. Description of the Related Art A one-chip design method and a multi-chip design method are known as design methods for giving a semiconductor device a composite function.

According to the one-chip design method, for example, PR
In an OM-mounted microcomputer or a BiCMOS type semiconductor device, various electronic circuit blocks including oscillation, frequency division, step-up / down, voltage division, smoothing, shaping, control, calculation, storage, etc. are provided on the main surface of one silicon substrate. By arranging in combination,
The desired composite function is obtained. However, the area of the single semiconductor chip thus obtained is gradually increasing.

An outline of a method of manufacturing a semiconductor device based on a one-chip design method will be described. A semiconductor chip cut out from a wafer by dicing is bonded to a die pad of a lead frame with a silver paste, and a metal thin wire is used on the main surface of the semiconductor chip. The electrode terminal and the inner lead of the lead frame are connected to each other, and the resin is molded with a sealing resin to complete a resin-sealed semiconductor device.

According to the multi-chip design method, a desired composite function can be obtained by combining a plurality of semiconductor chips each having a single function.

FIG. 11A is an exploded perspective view showing the structure of a conventional semiconductor device having a plurality of semiconductor chips.
(B) is the sectional view. 11A and 11B, two semiconductor chips 1 each having an electrode terminal 5 on the main surface, a wiring board 6 having the electrode terminal 5 on the main surface, an inner lead 7, A lead frame having an outer lead 11 and a die pad 9, a thin metal wire 8,
A sealing resin 10 for encapsulating them and molding them into a predetermined package 4 is provided. On the main surface of each of the two semiconductor chips 1, in addition to the electrode terminals 5, a circuit for realizing a single function, a power supply circuit, and an input / output circuit are arranged, and each semiconductor chip 1 has a small area. It has a specific independent function. Wiring covered with an insulating film is provided on the main surface of the wiring board 6, and two semiconductor chips 1 are two-dimensionally arranged at a predetermined position on the insulating film and bonded with an adhesive. ing. And between the electrode terminals 5 of the two semiconductor chips 1, the electrode terminals 5 of each semiconductor chip 1
And the electrode terminal 5 of the wiring board 6, and the electrode terminal 5 of each semiconductor chip 1 and the upper surface near the tip of the inner lead 7 of the lead frame are connected by metal thin wires 8.

The method of manufacturing the semiconductor device shown in FIGS. 11A and 11B will be described in detail. First, the wiring board 6 made of glass epoxy or polyimide having the wiring covered with the insulating film and the electrode terminals 5. The quality of the electrical characteristics of the circuit pattern above is tested in advance by a circuit function tester to classify the circuit function, and then the size of the wiring board 6 is obtained by punching or cutting. Next, the quality of the electrical characteristics of the wafer on which the semiconductor chip 1 is formed is tested in advance by a circuit function tester, the quality of the circuit function is sorted on the wafer, and then the wafer is separated into the size of the semiconductor chip 1 by dicing. To do. Then, the wiring board 6 is placed at a predetermined position on the die pad 9 of the lead frame made of a copper alloy or an iron-nickel alloy with a silver paste or a thermoplastic adhesive based on a resin such as thermosetting epoxy or polyimide. Pasting,
Bonding is performed by heating at a temperature of 100 to 400 ° C. for 30 seconds to 60 minutes. Each semiconductor chip 1 is similarly bonded to a predetermined position on the wiring board 6. The electrical connection between the two semiconductor chips 1, the wiring board 6 and the inner leads 7 of the lead frame is performed at a temperature of 200 to 280 ° C. by the ultrasonic thermocompression wire bonding method. Furthermore,
After molding the resin-sealed package 4 having a predetermined outer shape with the sealing resin 10, the outer leads 11 protruding to the outside of the package 4 are solder-plated, and the outer leads 11 are bent into a desired shape to form a resin. The sealed semiconductor device is completed.

[0008]

The above-described one-chip design method is a problem that cannot be ignored, such as a reduction in yield and a reduction in manufacturing condition margin due to an increase in the area of a semiconductor chip, an increase in circuit pattern processing steps, and complexity. was there. As a means for overcoming these problems, expensive capital investment has been made in order to develop circuit pattern miniaturization technology. On the other hand, from the viewpoint of the performance of the semiconductor device, an increase in impedance caused by the narrow wiring width of the power supply lines and the interval between the signal lines arranged over the entire main surface of the semiconductor chip, and the increase in impedance between the signal lines of different nodes are considered. Signal interference occurs, which has been an impeding factor for obtaining sufficient performance such as operating speed, operating voltage margin, and electrostatic breakdown strength of the semiconductor chip.

Further, in the conventional semiconductor device adopting the above-mentioned multi-chip designing method, since the semiconductor chips are arranged two-dimensionally, the packaging density as the semiconductor device of one package can be increased as planned. It wasn't done.

An object of the present invention is to provide a low-cost, highly reliable, high-value-added multi-function semiconductor device by adopting a three-dimensional arrangement of single-function semiconductor chips in a small package, and a manufacturing method thereof. To provide.

[0011]

In order to achieve the above-mentioned object, a semiconductor device according to the invention of claim 1 is constituted by stacking a plurality of semiconductor chips in two or more layers, the main surface of the lower semiconductor chip and the upper layer. An insulating film is provided between the semiconductor chip and the back surface of the semiconductor chip, and the upper layer semiconductor chip and the lower layer semiconductor chip are joined together via the insulating film.

According to a second aspect of the present invention, a semiconductor device is formed by stacking a plurality of semiconductor chips in two or more layers, and has an insulating layer between the main surface of the lower semiconductor chip and the back surface of the upper semiconductor chip. The insulating layer has a wiring made of a conductive material on at least one of the front surface and the back surface,
The upper-layer semiconductor chip and the lower-layer semiconductor chip adopt a configuration in which they are joined via an insulating layer having the wiring.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the back surface of the lowermost semiconductor chip among the stacked semiconductor chips is the front surface of the die pad of the lead frame. It uses a fixed structure.

According to a fourth aspect of the present invention, in the semiconductor device according to the first or second aspect of the present invention, the back surface of the lowermost semiconductor chip among the plurality of semiconductor chips stacked is the lead through the insulating film. The structure is fixed to the inner lead surface of the frame.

According to a fifth aspect of the present invention, there is provided a semiconductor device according to the first or second aspect of the present invention, in which the back surface of the lowermost semiconductor chip among a plurality of stacked semiconductor chips is a hollow die-attach package. The structure is fixed to the part.

According to a sixth aspect of the present invention, there is provided a semiconductor device according to the first or second aspect of the present invention, in which a back surface of a lowermost semiconductor chip among a plurality of semiconductor chips stacked is a die attach of a printed wiring board. The structure is fixed to the part.

According to a seventh aspect of the present invention, there is provided a semiconductor device in which a plurality of semiconductor chips are stacked in two or more layers, and a semi-curing type is provided between the main surface of the lower layer semiconductor chip and the back surface of the upper layer semiconductor chip. An upper layer semiconductor chip and a lower layer semiconductor chip have an organic layer, and a structure in which the organic layer is joined by heating is adopted.

According to an eighth aspect of the present invention, in the semiconductor device according to the seventh aspect, the back surface of the lowermost semiconductor chip among the plurality of stacked semiconductor chips is fixed to the die pad surface of the lead frame. It adopts a different configuration.

According to a ninth aspect of the present invention, in the semiconductor device according to the seventh aspect of the present invention, the back surface of the lowermost semiconductor chip among the plurality of semiconductor chips stacked is a lead frame via an insulating film. This is a structure that is fixed to the surface of the inner lead.

According to a tenth aspect of the present invention, in the semiconductor device according to the seventh aspect, the back surface of the lowermost semiconductor chip of the plurality of semiconductor chips stacked is the die attach portion of the hollow package. It uses a fixed structure.

A semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to the seventh aspect, wherein the back surface of the lowermost semiconductor chip among the stacked semiconductor chips is the die attach portion of the printed wiring board. It uses a fixed structure.

According to a twelfth aspect of the present invention, a semiconductor device is formed by stacking a plurality of semiconductor chips in two or more layers, and a lead frame is formed between the main surface of the lower layer semiconductor chip and the back surface of the upper layer semiconductor chip. The upper layer semiconductor chip and the lower layer semiconductor chip each have a portion (die pad or inner lead) and are joined to a part of the lead frame through an insulating film.

A thirteenth aspect of the present invention is a method for manufacturing the semiconductor device according to any one of the first to twelfth aspects, wherein a printed wiring having a pattern formed on a metal foil laminated on an insulating film. Is connected to the electrode terminals of the plurality of semiconductor chips by thermocompression bonding to realize the electrical connection of the semiconductor device.

Further, the invention of claim 14 relates to claims 1 to 1.
A method for manufacturing a semiconductor device according to any one of 2 above, wherein at least the plurality of semiconductor chips are resin-sealed.

[0025]

According to the present invention, by adopting a three-dimensional structure in which a plurality of single-function semiconductor chips are stacked in two or more layers, a small-sized, inexpensive and highly-reliable compound-function semiconductor composed of these semiconductor chips is mixed. The device can be realized. Further, unlike the conventional one-chip design method, each semiconductor chip does not need to be miniaturized, a wide wiring interval can be secured, and electrical characteristics can be improved.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention having a structure in which a plurality of semiconductor chips are stacked in two layers will be described below with reference to the accompanying drawings. However, a plurality of semiconductor chips may be stacked in three layers or more.

(Embodiment 1) FIG. 1A is an exploded perspective view showing a structure of a semiconductor device according to a first embodiment of the present invention.
(B) is the sectional view. The semiconductor device shown in FIGS. 1A and 1B has two upper layer semiconductor chips 2 each having an electrode terminal 5 on the main surface, an organic insulating film 12, and a lower layer semiconductor having an electrode terminal 5 on the main surface. A chip 3, a lead frame having an inner lead 7, an outer lead 11 and a die pad 9, a thin metal wire 8 and a sealing resin 10 for encapsulating the thin wire 8 and forming the outer shape of a predetermined package 4. There is.

The method for manufacturing the semiconductor device shown in FIGS. 1A and 1B will be described in detail. First, the quality of the electrical characteristics of the wafer on which the upper semiconductor chip 2 is formed is tested in advance by a circuit function tester, After the quality of the circuit function is classified on the wafer, the wafer is separated into units of the upper semiconductor chip 2 by dicing. Similarly, the electrical characteristics of the wafer on which the lower semiconductor chip 3 is formed are inspected, the semiconductor chips 3 in the wafer are classified into pass and fail, and the electrode terminals 5 on the main surface of the acceptable semiconductor chip 3 are excluded. An organic insulating film 12 made of glass epoxy, polyimide, polyester or the like having a thickness of 20 to 150 μm is formed in the region 15
In a high temperature atmosphere of 0 to 400 ° C., they are laminated with a thermosetting or thermoplastic adhesive (conductive or non-conductive) made of polyimide, epoxy resin or the like. The organic insulating film 12 may be processed by a photolithography process. The wafer that has undergone such processing is separated into units of lower layer semiconductor chips 3 by dicing.

The lead frame is made of copper alloy or iron-nickel alloy and has inner lead 7, outer lead 11 and die pad 9. 1 to 5 μm near the tips of the inner leads 7 and on the surface of the die pad 9.
It is plated with silver, gold or copper with a thickness of m. The separated lower semiconductor chip 3 is a thermosetting or thermoplastic adhesive (conductive or non-conductive) made of polyimide, epoxy resin or the like on the die pad 9 of the lead frame in a high temperature atmosphere of 150 to 400 ° C. Fixed). Further, two separated upper layer semiconductor chips 2 are formed on the organic insulating film 12 attached on the lower layer semiconductor chip 3 by using a thermosetting or thermoplastic adhesive (conductive layer) made of polyimide, epoxy resin or the like. It is electrically conductive or non-conductive) and sticks in a high temperature atmosphere.

Furthermore, between the electrode terminals 5 of the three semiconductor chips 2 and 3, between the electrode terminals 5 of the upper layer semiconductor chip 2 and the tips of the inner leads 7, and between the electrode terminals 5 of the lower layer semiconductor chip 3 and the inner leads 7. Connect the tip of each with a metal wire 8 made of gold or copper with a wire bonder,
The upper-layer semiconductor chip 2, the lower-layer semiconductor chip 3, the organic insulating film 12, and the thin metal wires 8 are molded with the thermosetting encapsulating resin 10 into the desired outer shape of the package 4. Then, the surface of the outer lead 11 protruding from the resin portion of the package 4 is plated with tin-lead eutectic solder, palladium or the like to form the outer lead 11.

According to the first embodiment, a structure in which a plurality of single function semiconductor chips 2 and 3 which are stacked and attached in two steps with the organic insulating film 12 sandwiched therebetween are bonded to the die pad 9 of the lead frame is used. Since it is adopted, it is possible to realize a small-sized, low-priced and highly reliable resin-encapsulated compound function semiconductor device which is a hybrid of these semiconductor chips 2 and 3. Further, unlike the conventional one-chip design method, the semiconductor chips 2 and 3 do not need to be miniaturized, a wide wiring interval can be secured, and the electrical characteristics are improved.

(Embodiment 2) FIG. 2A is an exploded perspective view showing a structure of a semiconductor device according to a second embodiment of the present invention.
(B) is the sectional view. The semiconductor device of FIGS. 2A and 2B has two upper layer semiconductor chips 2 each having an electrode terminal 5 on the main surface and an organic insulating material having wirings and electrode terminals 5 on the front surface or the back surface or both surfaces. A wiring board 6, a lower layer semiconductor chip 3 having electrode terminals 5 on its main surface, a lead frame having inner leads 7, outer leads 11 and die pads 9, metal wires 8, and a predetermined package in which they are sealed. 4, and a sealing resin 10 for molding into the outer shape of No. 4.

In the second embodiment, the organic insulating film 12 in the first embodiment is replaced with the wiring board 6, and the lower layer semiconductor chip 3, the wiring board 6 and the upper layer semiconductor are placed on the die pad 9 of the lead frame. The chip 2 is joined in this order. Detailed description of the manufacturing method is omitted. In addition to the case of the first embodiment, the connection by the thin metal wire 8 is performed between the electrode terminal 5 of the upper layer semiconductor chip 2 and the electrode terminal 5 of the wiring board 6, and between the electrode terminal 5 of the wiring board 6 and the lower layer semiconductor. It is performed between the electrode terminal 5 of the chip 3 and between the electrode terminal 5 of the wiring board 6 and the tip of the inner lead 7.

According to the second embodiment, a structure is employed in which a plurality of single-function semiconductor chips 2 and 3 stacked and attached in two steps with the wiring board 6 sandwiched therebetween are bonded to the die pad 9 of the lead frame. Therefore, it is possible to realize a small-sized, low-priced and highly reliable resin-encapsulated composite function semiconductor device which is a hybrid of these semiconductor chips 2 and 3. Moreover, the wiring of the wiring board 6 is composed of a plurality of semiconductor chips 2, 3
It is possible to partially bear the wiring between them. Further, unlike the conventional one-chip design method, the semiconductor chips 2 and 3 do not need to be miniaturized, a wide wiring interval can be secured, and the electrical characteristics are improved.

(Embodiment 3) FIG. 3A is an exploded perspective view showing the structure of a semiconductor device according to a third embodiment of the present invention.
(B) is the sectional view. The semiconductor device shown in FIGS. 3A and 3B has two upper layer semiconductor chips 2 each having an electrode terminal 5 on the main surface, a first organic insulating film 12, and an electrode terminal 5 on the main surface. In order to form the lower layer semiconductor chip 3 having the second organic insulating film 22, the lead frame having the inner leads 7 and the outer leads 11, the fine metal wires 8 and the external shape of the predetermined package 4 by encapsulating them. And the sealing resin 10.

According to FIGS. 3A and 3B, the lower semiconductor chip 3 is fixed onto the inner lead 7 of the lead frame having no die pad via the frame-shaped organic insulating film 22. The other points are similar to those of the first embodiment.

According to the third embodiment, a plurality of single-function semiconductor chips 2 and 3 stacked and attached in two steps with the organic insulating film 12 sandwiched therebetween are attached to the inner lead 7 of the lead frame to form a frame-shaped organic insulating film. Since the structure in which the film 22 is sandwiched is used for bonding, it is possible to realize a small-sized, low-priced and highly reliable resin-encapsulated multifunctional semiconductor device in which these semiconductor chips 2 and 3 are mixed. In particular, since a lead frame having no die pad is adopted, miniaturization is remarkable. Further, unlike the conventional one-chip design method, the semiconductor chips 2 and 3 do not need to be miniaturized, a wide wiring interval can be secured, and the electrical characteristics are improved.

The first organic insulating film 12 in the third embodiment can be replaced with the same wiring board 6 as in the second embodiment.

(Embodiment 4) FIG. 4A is an exploded perspective view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.
(B) is the sectional view. The semiconductor device shown in FIGS. 4A and 4B has two upper layer semiconductor chips 2 each having an electrode terminal 5 on the main surface, an organic insulating film 12, and a lower layer semiconductor having the electrode terminal 5 on the main surface. Chip 3, thin metal wire 8,
A hollow package 14a having an outer lead 11 and a die attach portion 13 is provided.

The hollow package 14a is a pre-mold type resin package having a desired outer shape. In the fourth embodiment, the semiconductor chips 2 and 3 stacked and attached in two steps with the organic insulating film 12 of the first embodiment sandwiched therebetween are replaced by the die pad 9 of the lead frame and die-attached to the hollow package 14a. It is fixed to the portion 13. Fine metal wire 8
After wire bonding using
The package 14a is sealed with a liquid resin or transfer molding resin of the same material as a. Then, the surface of the outer lead 11 protruding from the hollow package 14a is plated and the outer lead 11 is molded, whereby a small area resin-sealed semiconductor device having a composite function is completed.

According to the fourth embodiment, a plurality of single-function semiconductor chips 2 and 3 stacked and attached in two steps with the organic insulating film 12 sandwiched therebetween are fixed to the die attach portion 13 of the hollow package 14a. Since such a structure is adopted, it is possible to realize a small-sized, low-priced and highly reliable resin-encapsulated multi-function semiconductor device in which these semiconductor chips 2 and 3 are mixed. Further, unlike the conventional one-chip design method, the semiconductor chips 2 and 3 do not need to be miniaturized, a wide wiring interval can be secured, and the electrical characteristics are improved.

The organic insulating film 1 in the fourth embodiment
2 can be replaced with the same wiring board 6 as in the second embodiment. The hollow package 14a having the die attach portion 13 may be a package made of an insulator sintered body (ceramic) such as aluminum oxide or aluminum nitride.

(Embodiment 5) FIG. 5A is an exploded perspective view showing the structure of a semiconductor device according to a fifth embodiment of the present invention.
(B) is the sectional view. The semiconductor device shown in FIGS. 5A and 5B has two upper layer semiconductor chips 2 each having an electrode terminal 5 on the main surface, an organic insulating film 12, and a lower layer semiconductor having the electrode terminal 5 on the main surface. Chip 3, thin metal wire 8,
Sealing resin 10 for encapsulating them to form a predetermined module outer shape, electrode terminal 5, and die attach portion 1
And a printed wiring board 14b having the number 3 of FIG.

The printed wiring board 14b is made of resin such as glass epoxy or polyimide. In the fifth embodiment,
The semiconductor chips 2 and 3 stacked and attached in two steps with the organic insulating film 12 of the first embodiment sandwiched therebetween are fixed to the die attach portion 13 of the printed wiring board 14b instead of the die pad 9 of the lead frame. After the wire bonding using the fine metal wires 8, the resin is molded into a desired module outer shape with the molding resin 10 to complete a small area resin-sealed semiconductor device having a composite function.

According to the fifth embodiment, a plurality of single-function semiconductor chips 2 and 3 stacked and attached in two steps with the organic insulating film 12 sandwiched therebetween are fixed to the die attach portion 13 of the printed wiring board 14b. Since such a structure is adopted, it is possible to realize a small-sized, low-priced and highly reliable resin-encapsulated multi-function semiconductor device in which these semiconductor chips 2 and 3 are mixed. Further, unlike the conventional one-chip design method, the semiconductor chips 2 and 3 do not need to be miniaturized, a wide wiring interval can be secured, and the electrical characteristics are improved.

The organic insulating film 1 in the fourth embodiment
2 can be replaced with the same wiring board 6 as in the second embodiment. The printed wiring board 14b having the die attach portion 13 may be a board made of an insulator sintered body (ceramic) such as aluminum oxide or aluminum nitride.

(Sixth Embodiment) FIG. 6A is an exploded perspective view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.
(B) is the sectional view. The sixth embodiment is an upper layer semiconductor chip 2 and a lower layer semiconductor chip 3 in the first embodiment.
The joining method with is changed.

According to FIGS. 6A and 6B, the surface of the lower semiconductor chip 3 is covered with an insulating inorganic glass film on the main surface except for the electrode terminals 5, and a predetermined size is set in advance. An adhesive (conductive or non-conductive) made of semi-cured resin cut into pieces is placed as the organic layer 15. The size of the organic layer 15 is the same as or smaller by 0.5 mm than the upper layer semiconductor chips 2 stacked on top. Then, the upper layer semiconductor chip 2 is placed on the organic layer 15 and the organic layer 15 is cured in a high temperature atmosphere of 150 ° C. to 400 ° C., so that the upper layer semiconductor chip 2 and the lower layer semiconductor chip 3 are fixed to each other. The other points are similar to those of the first embodiment.

According to the sixth embodiment, a plurality of single function semiconductor chips 2 and 3 which are stacked and attached in two steps with the organic layer 15 which is a semi-curing adhesive agent sandwiched therebetween are attached to the die pad 9 of the lead frame. Since the structure formed by joining is adopted, it is possible to realize a small-sized, inexpensive and highly reliable resin-encapsulated multi-function semiconductor device in which these semiconductor chips 2 and 3 are mixed. Further, each semiconductor chip 2 and 3 does not need to be miniaturized unlike the conventional one-chip design method,
A wide wiring interval can be secured, which leads to improvement in electrical characteristics.

An adhesive made of a semi-curable resin (organic layer) of a required size can also be used to bond the lower semiconductor chip 3 and the die pad 9 of the lead frame.

(Embodiment 7) FIG. 7A is an exploded perspective view showing the structure of a semiconductor device according to a seventh embodiment of the present invention.
(B) is the sectional view. The seventh embodiment is the same as the upper semiconductor chip 2 and the lower semiconductor chip 3 in the third embodiment.
The joining method with is changed. The joining method using the organic layer 15 is the same as in the sixth embodiment.

According to the seventh embodiment, a plurality of single-function semiconductor chips 2 and 3 which are stacked and attached in two steps with the organic layer 15 which is a semi-curing adhesive agent sandwiched therebetween are attached to the inner lead 7 of the lead frame. Since the structure in which the frame-shaped organic insulating film 22 is sandwiched between the semiconductor chips 2 and 3 is adopted, a compact, inexpensive and highly reliable resin-encapsulated multi-function semiconductor device formed by mixing these semiconductor chips 2 and 3 is provided. realizable. In particular, since a lead frame having no die pad is adopted, miniaturization is remarkable. Further, unlike the conventional one-chip design method, the semiconductor chips 2 and 3 do not need to be miniaturized, a wide wiring interval can be secured, and the electrical characteristics are improved.

(Embodiment 8) FIG. 8A is an exploded perspective view showing the structure of a semiconductor device according to an eighth embodiment of the present invention.
(B) is the sectional view. The eighth embodiment is the same as the upper semiconductor chip 2 and the lower semiconductor chip 3 in the fourth embodiment.
The joining method with is changed. The joining method using the organic layer 15 is the same as in the sixth embodiment.

According to the eighth embodiment, a plurality of single-function semiconductor chips 2 and 3 which are stacked and attached in two steps with the organic layer 15 which is a semi-curing adhesive agent sandwiched therebetween are attached to the die of the hollow package 14a. Since the structure fixed to the touch portion 13 is adopted, it is possible to realize a small-sized, low-priced and highly reliable resin-encapsulated multi-function semiconductor device in which these semiconductor chips 2 and 3 are mixed. In addition, each semiconductor chip 2, 3
Unlike the conventional one-chip design method, there is no need for miniaturization, a wide wiring interval can be secured, and electrical characteristics are improved. The hollow package 14a having the die attach portion 13 may be either a resin package or a ceramic package.

(Embodiment 9) FIG. 9A is an exploded perspective view showing the structure of a semiconductor device according to a ninth embodiment of the present invention.
(B) is the sectional view. The ninth embodiment is the same as the upper semiconductor chip 2 and the lower semiconductor chip 3 in the fifth embodiment.
The joining method with is changed. The joining method using the organic layer 15 is the same as in the sixth embodiment.

According to the ninth embodiment, a plurality of single-function semiconductor chips 2 and 3 which are stacked and attached in two steps with the organic layer 15 which is a semi-curable adhesive sandwiched therebetween are attached to the diamond of the printed wiring board 14b. Since the structure fixed to the touch portion 13 is adopted, it is possible to realize a small-sized, low-priced and highly reliable resin-encapsulated multi-function semiconductor device in which these semiconductor chips 2 and 3 are mixed. In addition, each semiconductor chip 2, 3
Unlike the conventional one-chip design method, there is no need for miniaturization, a wide wiring interval can be secured, and electrical characteristics are improved. The printed wiring board 14b having the die attach portion 13 may be either a resin board or a ceramic board.

(Embodiment 10) FIG. 10A is an exploded perspective view showing the structure of a semiconductor device according to a tenth embodiment of the present invention, and FIG. 10B is a sectional view thereof. The semiconductor device shown in FIGS. 10A and 10B has two upper layer semiconductor chips 2 each having an electrode terminal 5 on the main surface, and a first organic insulating film 1.
2, a lead frame having an inner lead 7, an outer lead 11 and a die pad 9, a second organic insulating film 22, a lower layer semiconductor chip 3 having an electrode terminal 5 on a main surface thereof, a thin metal wire 8, and A sealing resin 10 for encapsulating and molding the outer shape of a predetermined package 4 is provided. The die pad 9 of the lead frame is divided into two parallel to the long side direction so as to be used as two bus bars 16 for supplying power to the semiconductor chips 2 and 3. The power supply terminal of the electrode terminals 5 of the semiconductor chips 2 and 3 is connected to the bus bar 16 by the thin metal wire 8. The back surface of the upper layer semiconductor chip 2 is on the front surface of the die pad 9 divided into two via the first organic insulating film 12, and the main surface of the lower layer semiconductor chip 3 is on the back surface of the die pad 9 divided into the second organic insulating film. They are fixed via 22 respectively. The fixing method and other points are the same as those in the first embodiment.

According to the tenth embodiment, the die pad 9 divided into two and the two organic insulating films 12 and 22 are sandwiched between the two.
Since a structure having a plurality of single-function semiconductor chips 2 and 3 which are stacked and attached in stages is adopted, a compact, inexpensive and highly reliable resin-sealed type which is a mixture of these semiconductor chips 2 and 3 A multi-function semiconductor device can be realized. Especially, since the die pad 9 divided into two is used as the bus bar 16, the miniaturization is remarkable. Further, unlike the conventional one-chip design method, the semiconductor chips 2 and 3 do not need to be miniaturized, a wide wiring interval can be secured, and the electrical characteristics are improved.

A lead frame having no die pad is adopted according to the third embodiment, and the organic insulating film 12,
It is also possible to adopt a structure in which the inner lead 7 of the lead frame is sandwiched between the upper layer semiconductor chip 2 and the lower layer semiconductor chip 3 while maintaining insulation at 22.

In the first to tenth embodiments described above, the electrical connection between the respective parts is realized by the thin metal wires 8, but some or all of them can be replaced with foil-like wiring. This foil-like wiring is obtained by bonding a metal foil on an insulating film and patterning the wiring as seen in a film carrier. The terminal portion of such a foil-like wiring is connected to the electrode terminal 5 of each portion by thermocompression bonding.

Further, in the resin sealing in each of the embodiments, the liquid resin is cast-molded in the heating die, the semi-curable resin is cast-molded, the liquid resin is dropped into the potting mold, and the pelletized solid resin is used. A method such as heat melt molding can be adopted.

[0062]

As described above, according to the present invention, a resin-encapsulated semiconductor package having a small mounting area can be realized by combining a plurality of single-function semiconductor chips of different types into a multi-function semiconductor device. The circuit design is simplified and the development period is shortened. The electrical performance is improved, and by using the single-function semiconductor chip, the process standardization of the semiconductor chip can be realized and the cost can be reduced. In addition, there is an effect that semiconductor devices having various functions can be realized by combining single-function semiconductor chips.

[Brief description of drawings]

1A and 1B are diagrams showing a configuration of a semiconductor device according to a first exemplary embodiment of the present invention, in which FIG. 1A is an exploded perspective view and FIG.

2A and 2B are diagrams showing a configuration of a semiconductor device according to a second exemplary embodiment of the present invention, in which FIG. 2A is an exploded perspective view and FIG.

FIG. 3 is a diagram showing a configuration of a semiconductor device according to a third embodiment of the present invention, (a) is an exploded perspective view and (b) is a sectional view.

FIG. 4 is a diagram showing a configuration of a semiconductor device according to a fourth exemplary embodiment of the present invention, in which (a) is an exploded perspective view and (b) is a sectional view.

5A and 5B are diagrams showing a configuration of a semiconductor device according to a fifth exemplary embodiment of the present invention, in which FIG. 5A is an exploded perspective view and FIG.

6A and 6B are diagrams showing a configuration of a semiconductor device according to a sixth embodiment of the present invention, wherein FIG. 6A is an exploded perspective view and FIG. 6B is a sectional view.

7A and 7B are diagrams showing a configuration of a semiconductor device according to a seventh embodiment of the present invention, wherein FIG. 7A is an exploded perspective view and FIG. 7B is a sectional view.

8A and 8B are diagrams showing a configuration of a semiconductor device according to an eighth embodiment of the present invention, wherein FIG. 8A is an exploded perspective view and FIG. 8B is a sectional view.

9A and 9B are diagrams showing a configuration of a semiconductor device according to a ninth embodiment of the present invention, in which FIG. 9A is an exploded perspective view and FIG. 9B is a sectional view.

10A and 10B are diagrams showing a configuration of a semiconductor device according to a tenth embodiment of the present invention, wherein FIG. 10A is an exploded perspective view and FIG.

FIG. 11 is a diagram showing a configuration of a conventional semiconductor device including a plurality of semiconductor chips, in which (a) is an exploded perspective view;
(B) is a sectional view.

[Explanation of symbols]

 1,2,3 Semiconductor chip 4 Package 5 Electrode terminal 6 Wiring board 7 Inner lead 8 Metal fine wire 9 Die pad 10 Sealing resin 11 Outer lead 12,22 Organic insulating film 13 Die attach part 14a Hollow type package 14b Printed wiring board 15 Organic Layer (semi-curable adhesive) 16 Bus bar

Claims (14)

[Claims] 1. A plurality of semiconductor chips are stacked to form two or more layers, and an insulating film is provided between a main surface of the lower layer semiconductor chip and a back surface of the upper layer semiconductor chip, and the upper layer semiconductor chip and the lower layer semiconductor chip. Is bonded via the insulating film. 2. A plurality of semiconductor chips are stacked to form two or more layers, and an insulating layer is provided between the main surface of the lower semiconductor chip and the back surface of the upper semiconductor chip. In at least one of the above, there is provided a wiring made of a conductive material, and the upper layer semiconductor chip and the lower layer semiconductor chip are joined via an insulating layer having the wiring. 3. The semiconductor device according to claim 1, wherein the back surface of the lowermost semiconductor chip is fixed to the die pad surface of the lead frame. 4. The semiconductor device according to claim 1, wherein the back surface of the lowermost semiconductor chip is fixed to the inner lead surface of the lead frame via an insulating film. 5. The semiconductor device according to claim 1, wherein the back surface of the lowermost semiconductor chip is fixed to the die attach portion of the hollow package. 6. The semiconductor device according to claim 1, wherein the bottom surface of the lowermost semiconductor chip is fixed to a die attach portion of a printed wiring board. 7. A plurality of semiconductor chips are stacked to form two or more layers, and a semi-curable organic layer is provided between the main surface of the lower semiconductor chip and the back surface of the upper semiconductor chip. A semiconductor device characterized by being bonded to a lower semiconductor chip by heating the organic layer. 8. The semiconductor device according to claim 7, wherein the bottom surface of the lowermost semiconductor chip is fixed to the front surface of the die pad of the lead frame. 9. The semiconductor device according to claim 7, wherein the back surface of the lowermost semiconductor chip is fixed to the inner lead surface of the lead frame via an insulating film. 10. The semiconductor device according to claim 7, wherein the bottom surface of the lowermost semiconductor chip is fixed to the die attach portion of the hollow package. 11. The semiconductor device according to claim 7, wherein the back surface of the lowermost semiconductor chip is fixed to the die attach portion of the printed wiring board. 12. A plurality of semiconductor chips are stacked to form two or more layers, and a part of a lead frame is provided between the main surface of the lower semiconductor chip and the back surface of the upper semiconductor chip.
The semiconductor device according to claim 1, wherein the upper layer semiconductor chip and the lower layer semiconductor chip are respectively joined to a part of the lead frame via an insulating film. 13. A method for manufacturing the semiconductor device according to claim 1, wherein a printed wiring having a pattern formed on a metal foil laminated on an insulating film is formed by thermocompression bonding. A method of manufacturing a semiconductor device, comprising electrically connecting the semiconductor device by connecting to electrode terminals of the plurality of semiconductor chips. 14. A method for manufacturing the semiconductor device according to claim 1, wherein at least the plurality of semiconductor chips are resin-sealed. Production method.