JPH08340076A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08340076A
JPH08340076A JP14604495A JP14604495A JPH08340076A JP H08340076 A JPH08340076 A JP H08340076A JP 14604495 A JP14604495 A JP 14604495A JP 14604495 A JP14604495 A JP 14604495A JP H08340076 A JPH08340076 A JP H08340076A
Authority
JP
Japan
Prior art keywords
semiconductor chip
synthetic resin
package
resin material
inner leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14604495A
Other languages
Japanese (ja)
Inventor
Naohisa Okumura
尚久 奥村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP14604495A priority Critical patent/JPH08340076A/en
Publication of JPH08340076A publication Critical patent/JPH08340076A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To suppress the formation of cavities and development of warps, cracks, etc., by burying a thermosetting synthetic resin which does not remelt until the surface of the resin becomes flush with the front ends of inner leads in the surface of a semiconductor chip between the front ends of adjacent inner leads. CONSTITUTION: A rectangular semiconductor chip 12 is formed of a silicon semiconductor substrate. A plurality of inner leads 13 arranged along the long side of the chip 12 is fixed to the upper surface of the chip 12. The leads 13 are made of Cu or an Ni-Fe alloy and arranged at 0.1-3.0mm intervals. For fixing the front end sections 13a of the leads 13 to the upper surface of the chip 12, a polyimide adhesive tape 14 is used. The front end sections 13a are respectively connected to pads 15 through bonding wires 16. A burying agent 17 composed of a thermosetting resin is buried and a package 18 is formed by injection-molding a synthetic resin for setting and sealing. Therefore, the development of cavities and cracks can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
にインナーリードを半導体チップの表面に固定した樹脂
封止型の半導体装置に好適する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and is particularly suitable for a resin-sealed semiconductor device having inner leads fixed to the surface of a semiconductor chip.

【0002】[0002]

【従来の技術】従来、インナーリードを半導体チップの
表面に固定し合成樹脂製パッケージ内に封止するように
したLOC(Lead On Chip)タイプの半導
体装置は、インナーリードを半導体チップの略中央部に
設けたパッドとボンディングワイヤにより接続している
ために、パッドを半導体チップの周辺部に設けたものよ
り幅寸法を大きくすることができ、図3に断面図、図4
にインナーリードを固定した半導体チップの平面図を示
すように構成されている。
2. Description of the Related Art Conventionally, in a LOC (Lead On Chip) type semiconductor device in which an inner lead is fixed on the surface of a semiconductor chip and sealed in a synthetic resin package, the inner lead is formed in a substantially central portion of the semiconductor chip. Since the pad is connected to the pad by the bonding wire, the width dimension of the pad can be made larger than that of the pad provided in the peripheral portion of the semiconductor chip.
It is configured as shown in a plan view of a semiconductor chip having inner leads fixed thereto.

【0003】図3及び図4において、1は樹脂封止型の
半導体装置であり、2は長方形状の半導体チップであ
る。3は半導体チップ2の上面に接着テープ4を介して
接着された複数のインナーリードであり、このインナー
リード3は互いに所定間隔を設け半導体チップ2の両長
辺に沿って配列され、それらの先端が半導体チップ2の
中央部近傍に位置するまで延在するものとなっている。
そしてインナーリード3は、その先端部と半導体チップ
2の略中央部に長辺方向に配列された対応するパッド5
とがボンディングワイヤ6により接続されている。
In FIGS. 3 and 4, 1 is a resin-sealed semiconductor device, and 2 is a rectangular semiconductor chip. Reference numeral 3 denotes a plurality of inner leads adhered to the upper surface of the semiconductor chip 2 via an adhesive tape 4, and the inner leads 3 are arranged along a long side of the semiconductor chip 2 with a predetermined interval therebetween, and their tips are provided. Extend to the vicinity of the central portion of the semiconductor chip 2.
The inner lead 3 has a corresponding pad 5 arranged in the long side direction at the tip portion and the substantially central portion of the semiconductor chip 2.
And are connected by a bonding wire 6.

【0004】7はインナーリード3が接着された半導体
チップ2を封止用の合成樹脂材料による射出成形によっ
て形成され封止するパッケージである。このパッケージ
7は、例えば半導体チップ2の厚さが約0.3mm程
度、インナーリード3の厚さが約0.1mm程度である
のに対し、略1mm程度の厚さとなっている。
A package 7 is formed by injection molding the semiconductor chip 2 to which the inner leads 3 are bonded by injection molding with a synthetic resin material for sealing. The package 7 has a thickness of about 1 mm, while the semiconductor chip 2 has a thickness of about 0.3 mm and the inner leads 3 have a thickness of about 0.1 mm.

【0005】このように構成された半導体装置1では、
パッケージ7の成形型内にインナーリード3が接着され
た半導体チップ2を保持し、成形型のゲート部分から型
内部に加熱、加圧注入された溶融状態の封止用の合成樹
脂材料が半導体チップ2の両面を流動し、固化すること
でパッケージ7の成形が行われる。
In the semiconductor device 1 thus constructed,
The semiconductor chip 2 to which the inner leads 3 are adhered is held in the molding die of the package 7, and the synthetic resin material for sealing in a molten state, which is heated and pressure-injected from the gate portion of the molding die to the inside of the die, is the semiconductor chip. The package 7 is molded by flowing and solidifying both surfaces of No. 2.

【0006】しかし、パッケージ7にはパッケージ7内
部に封じ込まれた状態の内部巣や一部外部に開口する外
部巣が生じたり、成形に際し成形型内に注入された封止
用の合成樹脂材料の流動によって、半導体チップ2が浮
き沈みして良好な成形が行えないなどの問題を引き起こ
したり、さらに、パッケージ7の反りやクラック等の発
生によって半導体装置1の信頼性に悪影響を与える虞が
あるものとなっていた。
[0006] However, the package 7 has internal cavities in a state of being sealed inside the package 7 or external cavities that are partially open to the outside, or a synthetic resin material for sealing injected into a molding die at the time of molding. Flow of the semiconductor chip 2 may cause problems such as ups and downs of the semiconductor chip 2 such that good molding cannot be performed, and further, warpage or cracks of the package 7 may adversely affect the reliability of the semiconductor device 1. It was.

【0007】これら内部巣や外部巣等の発生について原
因を調べたところ、パッケージ7の成形の際、溶融状態
の封止用の合成樹脂材料が半導体チップ2の上下両面を
不均等に流動することに起因して発生することが明かと
なった。すなわち、溶融状態の封止用の合成樹脂材料
は、半導体チップ2のインナーリード3が接着されてい
ない半導体チップ2の下面側では比較的円滑に流れるも
のの、上面側では長辺部分から中央部近傍にまで延在す
るインナーリード3の先端部によって流れが妨げられて
円滑とはならず、所定間隔で設けられたインナーリード
3間の半導体チップ2表面上には流れ難くなり、未充填
状態のままとなってしまう部分が生じて内部巣や外部巣
が形成される。
The cause of these internal cavities and external cavities was investigated, and it was found that the synthetic resin material for sealing in the molten state flows unevenly on both upper and lower surfaces of the semiconductor chip 2 when the package 7 is molded. It has become clear that this is caused by. That is, the synthetic resin material for sealing in a molten state flows relatively smoothly on the lower surface side of the semiconductor chip 2 to which the inner leads 3 of the semiconductor chip 2 are not bonded, but on the upper surface side from the long side portion to the vicinity of the central portion. The flow of the inner leads 3 extending to the upper end prevents the flow from being smooth, and it becomes difficult for the inner leads 3 provided at a predetermined interval to flow on the surface of the semiconductor chip 2. The inner nest and the outer nest are formed due to the part that becomes

【0008】そして内部巣や外部巣を介して導電部と外
表面とが連通されたり、吸蔵されていた水分が内部巣等
で膨張してクラックを発生させる。また溶融状態の封止
用の合成樹脂材料の流れが半導体チップ2の下面側では
比較的円滑であり、上面側では円滑ではないために、上
下両面での流速の差から半導体チップ2が浮き沈みして
しまう。さらに封止用の合成樹脂材料の未充填状態が上
面側に生じると、半導体チップ2の上下両面側における
パッケージ7の熱膨脹量が所定通りとならず全体に反り
が生じてしまうものであった。
Then, the conductive portion and the outer surface are communicated with each other through the inner cavity or the outer cavity, or the stored moisture expands in the inner cavity or the like to generate cracks. Further, the flow of the synthetic resin material for sealing in a molten state is relatively smooth on the lower surface side of the semiconductor chip 2 and not smooth on the upper surface side, so that the semiconductor chip 2 rises and falls due to the difference in flow velocity between the upper and lower surfaces. Will end up. Further, if the unfilled state of the synthetic resin material for encapsulation occurs on the upper surface side, the amount of thermal expansion of the package 7 on the upper and lower surface sides of the semiconductor chip 2 does not become a predetermined amount, and the whole warps.

【0009】[0009]

【発明が解決しようとする課題】上記のようにパッケー
ジを成形する際に、溶融した封止用の合成樹脂材料がイ
ンナーリードが固定された半導体チップの上面側では円
滑に流動せず、封止用の合成樹脂材料の未充填部分がパ
ッケージに内部巣や外部巣を形成し、さらに、パッケー
ジに反りやクラック等が生じて信頼性が低くなる虞があ
り、また比較的円滑に流動する下面側との流速の差から
半導体チップが浮き沈みして良好な成形が行えない状況
にあった。このような状況に鑑みて本発明はなされたも
ので、その目的とするところはパッケージにおける巣の
形成が抑制され、さらに反りやクラック等の発生も抑制
された信頼性の高い半導体装置を提供することにある。
When molding a package as described above, the molten synthetic resin material for sealing does not flow smoothly on the upper surface side of the semiconductor chip to which the inner leads are fixed, and the sealing is performed. The unfilled portion of the synthetic resin material for molding may form internal cavities or external cavities in the package, and there is a possibility that the package may be warped or cracked, resulting in low reliability, and the lower surface side that flows relatively smoothly. Due to the difference in flow rate between the semiconductor chip and the semiconductor chip, the semiconductor chip was up and down, and good molding could not be performed. The present invention has been made in view of such a situation, and an object thereof is to provide a highly reliable semiconductor device in which formation of cavities in a package is suppressed and further warpage, cracks, and the like are suppressed. Especially.

【0010】[0010]

【課題を解決するための手段】本発明の半導体装置は、
複数の所定間隔で設けられたインナーリードの先端部を
半導体チップの表面に固定して合成樹脂製パッケージ内
に封止してなる半導体装置において、少なくとも隣接す
るインナーリードの先端部間の半導体チップの表面に、
合成樹脂材料による埋め込みを行った後にパッケージに
よる封止がなされていることを特徴とするものであり、
さらに、合成樹脂材料による埋め込みが、インナーリー
ドの先端部と略同一平面となるまでおこなわれてている
ことを特徴とするものであり、さらに、埋め込みを行う
合成樹脂材料が、パッケージを形成する際の成形条件の
もとでは再溶融しないものであることを特徴とするもの
であり、さらに、埋め込みを行う合成樹脂材料が、熱硬
化性の合成樹脂材料であることを特徴とするものであ
る。
According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device in which the tips of inner leads provided at a plurality of predetermined intervals are fixed on the surface of a semiconductor chip and sealed in a synthetic resin package, at least the semiconductor chips between the tips of adjacent inner leads are On the surface,
It is characterized by being sealed with a package after being embedded with a synthetic resin material,
Further, it is characterized in that the filling with the synthetic resin material is performed until it becomes substantially flush with the tip portion of the inner lead, and further, when the synthetic resin material to be embedded forms the package. It is characterized in that it is not re-melted under the molding conditions of No. 1, and the synthetic resin material to be embedded is a thermosetting synthetic resin material.

【0011】[0011]

【作用】上記のように構成された半導体装置は、半導体
チップの表面に固定された複数のインナーリードの間に
合成樹脂材料による埋め込みを行った後で合成樹脂製の
パッケージによる封止をおこなうよう構成したので、半
導体チップ等を封止するようパッケージを成形する際
に、半導体チップのインナーリードが固定された表面側
の凸凹状態が合成樹脂材料による埋め込みを行うことで
解消され、全体表面が平坦なものとなって合成樹脂製の
パッケージを成形する際、成形型内における材料の流れ
が円滑となって材料の未充填状態がなくなり、成形され
たパッケージにおける巣の形成が抑制され、反りやクラ
ック等の発生も抑制されて信頼性が向上する。
In the semiconductor device configured as described above, a synthetic resin material is embedded between a plurality of inner leads fixed to the surface of a semiconductor chip, and then sealed by a synthetic resin package. Since it is configured, when molding the package to seal the semiconductor chip, the unevenness on the surface side where the inner leads of the semiconductor chip are fixed is eliminated by embedding with a synthetic resin material, and the entire surface is flat. When molding a synthetic resin package, the flow of the material in the mold becomes smooth and the unfilled state of the material disappears, the formation of cavities in the molded package is suppressed, and warpage and cracks occur. The occurrence of such a phenomenon is suppressed and the reliability is improved.

【0012】[0012]

【実施例】以下、本発明の一実施例を図1乃至図3を参
照して説明する。図1は断面図であり、図2はインナー
リードを固定した半導体チップの平面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view, and FIG. 2 is a plan view of a semiconductor chip to which inner leads are fixed.

【0013】図1及び図2において、11は樹脂封止型
の半導体装置であり、12は長方形状の半導体チップで
あり、この半導体チップ12はシリコン半導体基板によ
って形成された1辺が数mm程度で厚さが約0.3mm
程度のものである。また13は半導体チップ12の上面
に固定された複数のインナーリードで、半導体チップ1
2の両長辺に沿って配列され、それらの先端が半導体チ
ップ12の中央部近傍に位置するまで延在するものとな
っている。
In FIGS. 1 and 2, 11 is a resin-sealed semiconductor device, 12 is a rectangular semiconductor chip, and this semiconductor chip 12 has a side of several mm formed by a silicon semiconductor substrate. And the thickness is about 0.3mm
It is of a degree. Further, 13 is a plurality of inner leads fixed to the upper surface of the semiconductor chip 12,
2 are arranged along both long sides and extend until their tips are located near the center of the semiconductor chip 12.

【0014】インナーリード13は銅(Cu)あるいは
ニッケル(Ni)−鉄(Fe)合金の42alloy等
の導電材料で形成された幅が0.1mm〜0.2mm程
度のもので、隣接するインナーリード13の相互間には
0.1mm〜0.2mm程度の間隔が設けられている。
またインナーリード13の半導体チップ12上面への固
定は、半導体チップ12の上面に厚さが約0.1mm程
度で両面に粘着剤が設けられたポリイミド系絶縁フィル
ムの接着テープ14により、インナーリード13の先端
部13aを接着することによって行われている。
The inner lead 13 is made of a conductive material such as 42 alloy of copper (Cu) or nickel (Ni) -iron (Fe) alloy and has a width of about 0.1 mm to 0.2 mm. An interval of about 0.1 mm to 0.2 mm is provided between the 13 members.
Further, the inner lead 13 is fixed to the upper surface of the semiconductor chip 12 by an adhesive tape 14 of a polyimide insulating film having a thickness of about 0.1 mm on the upper surface of the semiconductor chip 12 and adhesives provided on both sides. It is performed by adhering the tip portion 13a of the.

【0015】そして半導体チップ12の上面に固定され
たインナーリード13の先端部13aは、半導体チップ
12の略中央部に長辺方向に配列された対応するパッド
15とがボンディングワイヤ16により接続されてい
る。
The tip portion 13a of the inner lead 13 fixed to the upper surface of the semiconductor chip 12 is connected by a bonding wire 16 to a corresponding pad 15 arranged in the long side direction at a substantially central portion of the semiconductor chip 12. There is.

【0016】また、隣接するインナーリード13の先端
部13a間の半導体チップ12の上面には、ポリイミド
系の合成樹脂材料や二液性エポキシ樹脂、もしくはシリ
コン樹脂、熱硬化性樹脂などでなる埋め込み材料17
が、隣接するインナーリード13の先端部13a上面と
埋め込み表面17aとが略一致するように埋め込まれて
いる。あるいは埋め込み材料17がインナーリード13
の先端部13aを覆い、埋め込み後の全体表面が平坦面
となるように埋め込みが行われている。
On the upper surface of the semiconductor chip 12 between the tip portions 13a of the adjacent inner leads 13, an embedding material made of a polyimide-based synthetic resin material, a two-component epoxy resin, a silicon resin, a thermosetting resin, or the like. 17
However, it is embedded so that the upper surface of the tip portion 13a of the adjacent inner lead 13 and the embedded surface 17a are substantially aligned with each other. Alternatively, the embedding material 17 is the inner lead 13
Embedding is performed so as to cover the tip portion 13a of the and to make the entire surface after the embedding flat.

【0017】そして、インナーリード13の先端部13
a間が埋め込み材料17で埋め込まれた半導体チップ1
2は、成形型内にセットされ、けい素入りのエポキシ系
樹脂等の封止用の合成樹脂材料による射出成形によって
略1mm程度の厚さのパッケージ18が形成され封止が
行われる。パッケージ18が形成された後、図示しない
フレームとパッケージ18の成形時まで接続しておくた
めの吊りピンの切断を行うと共に、パッケージ18から
延出したアウターリードを所定のJ字形状等に成形し、
単体の半導体装置11とする。
The tip portion 13 of the inner lead 13
The semiconductor chip 1 in which the space between a and is filled with the filling material 17.
2 is set in a molding die, and a package 18 having a thickness of about 1 mm is formed by injection molding with a synthetic resin material for sealing such as silicon-containing epoxy resin, and sealing is performed. After the package 18 is formed, the hanging pins for connecting to the frame (not shown) until the package 18 is formed are cut, and the outer leads extending from the package 18 are formed into a predetermined J-shape or the like. ,
The semiconductor device 11 is a single unit.

【0018】このように半導体装置11が構成されてい
るので、その形成工程のうちのパッケージ18を形成し
て半導体チップ12を封止する際、パッケージ18の成
形型内に半導体チップ12を保持し、その後、成形型の
ゲート部分から型内部に加熱された溶融状態の封止用の
合成樹脂材料が加圧注入される。注入された溶融状態の
封止用の合成樹脂材料は、半導体チップ12のインナー
リード13が固定された面側とその裏面側の両面に沿っ
て流動する。
Since the semiconductor device 11 is configured as described above, when the package 18 is formed and the semiconductor chip 12 is sealed in the forming process, the semiconductor chip 12 is held in the mold of the package 18. Then, the molten synthetic resin material for sealing is pressurized and injected from the gate portion of the mold into the mold. The injected molten synthetic resin material for sealing flows along both the surface of the semiconductor chip 12 to which the inner leads 13 are fixed and the back surface thereof.

【0019】流下するにしたがって温度が下がり溶融状
態にあった封止用の合成樹脂材料は固化し始める。この
時、半導体チップ12のインナーリード13が固定され
た面側を流動する封止用の合成樹脂材料は、インナーリ
ード13の先端部13aが固定され凸凹状態となってい
て埋め込み材料17の埋め込みで平坦化した埋め込み表
面17aに沿って流動することになる。
As it flows down, the temperature lowers and the synthetic resin material for sealing, which was in a molten state, begins to solidify. At this time, the synthetic resin material for sealing, which flows on the surface side of the semiconductor chip 12 to which the inner leads 13 are fixed, is in a concave-convex state with the tip portions 13a of the inner leads 13 fixed, so that the embedding material 17 is embedded. It will flow along the flattened embedded surface 17a.

【0020】このため、インナーリード13が固定され
た面側を流動する封止用の合成樹脂材料もその裏面側を
流れるものと同様、円滑に両面側で速度差が生じないよ
う略等速度で流れる。その結果、半導体チップ12が成
形時に浮き沈みすることがない。また封止用の合成樹脂
材料の流れがインナーリード13の先端部13aによる
凸凹状態がなくなって妨げられないために、未充填状態
が発生する虞がなくなり、内部巣や外部巣が発生し難く
なってパッケージ18の成形が良好なものとなる。そし
て封止用の合成樹脂材料の未充填状態がなくなること
で、半導体チップ12の両面側においてパッケージ18
の熱膨脹量が略同一となり、全体に反りが生じてしまう
ことも抑制される。
For this reason, the synthetic resin material for sealing, which flows on the surface side to which the inner lead 13 is fixed, like the material flowing on the back surface side, has a substantially constant speed so that a speed difference does not occur smoothly on both surface sides. Flowing. As a result, the semiconductor chip 12 does not rise or fall during molding. Further, since the flow of the synthetic resin material for sealing is not disturbed by the unevenness due to the tip end portion 13a of the inner lead 13, there is no possibility of the unfilled state, and it becomes difficult for internal cavities and external cavities to occur. As a result, the package 18 can be molded well. Then, since the unfilled state of the synthetic resin material for sealing disappears, the package 18 is provided on both sides of the semiconductor chip 12.
The thermal expansion amounts of are substantially the same, and the occurrence of warpage is suppressed.

【0021】さらに、内部巣や外部巣が発生し難くなる
ため、これらの巣を介して延出するアウターリードを除
く半導体チップ12等の導電部と外表面とが連通してし
まうことがなくなり、またパッケージ18に吸蔵されて
いた水分が内部巣等で膨張してクラックを発生する虞も
なくなり、半導体装置11の信頼性も向上し高いものと
なる。
Furthermore, since it becomes difficult for internal cavities and external cavities to occur, the conductive parts of the semiconductor chip 12 and the like excluding the outer leads extending through these cavities do not communicate with the outer surface, In addition, there is no possibility that the moisture occluded in the package 18 will expand due to internal voids or the like and cracks will occur, and the reliability of the semiconductor device 11 will be improved and will be high.

【0022】[0022]

【発明の効果】以上の説明から明らかなように、本発明
は、半導体チップの表面に固定された複数のインナーリ
ードの間に合成樹脂材料による埋め込みを行った後で合
成樹脂製のパッケージによる封止がなされるよう構成し
たことにより、パッケージにおける巣の形成が抑制さ
れ、反りやクラック等の発生も抑制されて信頼性が向上
する等の効果を奏する。
As is apparent from the above description, according to the present invention, a synthetic resin material is embedded between a plurality of inner leads fixed to the surface of a semiconductor chip and then sealed by a synthetic resin package. By being configured so as to be stopped, formation of cavities in the package is suppressed, occurrence of warpage and cracks is also suppressed, and reliability is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】本発明の一実施例に係るインナーリードを固定
した半導体チップの平面図である。
FIG. 2 is a plan view of a semiconductor chip having an inner lead fixed according to an embodiment of the present invention.

【図3】従来例を示す断面図である。FIG. 3 is a cross-sectional view showing a conventional example.

【図4】従来例に係るインナーリードを固定した半導体
チップの平面図である。
FIG. 4 is a plan view of a semiconductor chip having inner leads fixed according to a conventional example.

【符号の説明】[Explanation of symbols]

12…半導体チップ 13…インナーリード 13a…先端部 17…埋め込み材料 18…パッケージ 12 ... Semiconductor chip 13 ... Inner lead 13a ... Tip part 17 ... Embedding material 18 ... Package

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/29 H01L 23/30 B 23/31 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 23/29 H01L 23/30 B 23/31

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 複数の所定間隔で設けられたインナーリ
ードの先端部を半導体チップの表面に固定して合成樹脂
製パッケージ内に封止してなる半導体装置において、少
なくとも隣接する前記インナーリードの先端部間の前記
半導体チップの表面に、合成樹脂材料による埋め込みを
行った後に前記パッケージによる封止がなされているこ
とを特徴とする半導体装置。
1. A semiconductor device having a plurality of predetermined inner lead tips fixed to the surface of a semiconductor chip and sealed in a synthetic resin package, wherein at least the tips of adjacent inner leads are provided. A semiconductor device characterized in that the surface of the semiconductor chip between the parts is filled with a synthetic resin material and then sealed with the package.
【請求項2】 合成樹脂材料による埋め込みが、インナ
ーリードの先端部と略同一平面となるまでおこなわれて
ていることを特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the burying with the synthetic resin material is performed until it becomes substantially flush with the tip portion of the inner lead.
【請求項3】 埋め込みを行う合成樹脂材料が、パッケ
ージを形成する際の成形条件のもとでは再溶融しないも
のであることを特徴とする請求項1又は請求項2記載の
半導体装置。
3. The semiconductor device according to claim 1, wherein the synthetic resin material to be embedded does not remelt under the molding conditions for forming the package.
【請求項4】 埋め込みを行う合成樹脂材料が、熱硬化
性の合成樹脂材料であることを特徴とする請求項1又は
請求項2記載の半導体装置。
4. The semiconductor device according to claim 1, wherein the synthetic resin material to be embedded is a thermosetting synthetic resin material.
JP14604495A 1995-06-13 1995-06-13 Semiconductor device Pending JPH08340076A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14604495A JPH08340076A (en) 1995-06-13 1995-06-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14604495A JPH08340076A (en) 1995-06-13 1995-06-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH08340076A true JPH08340076A (en) 1996-12-24

Family

ID=15398840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14604495A Pending JPH08340076A (en) 1995-06-13 1995-06-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH08340076A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999041783A1 (en) * 1998-02-12 1999-08-19 Siemens Aktiengesellschaft Semiconductor module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999041783A1 (en) * 1998-02-12 1999-08-19 Siemens Aktiengesellschaft Semiconductor module

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