JPH08340049A - Integrated circuit correction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To bring mounting of fuses on an integrated circuit into the higher density state by a method, wherein a photoresist covering a conductive link is made selectively to be exposed to light and the exposed photoresist is dissolved with a developing solution, which dissolves the photoresist made to be exposed. SOLUTION: An organic polymer 36, which is called a photoresist, is spin- coated uniformly on a conductive link. Then, the photoresist 36 is exposed with a laser system 40, and the photoresist is solubilized into a solvent, whereby a pattern is formed. A region covering a lead 30 to be removed is made to be exposed with a laser beam of a proper wavelength using the photoresist 36, which is actually sensitive to light. The photoresist 36 is exposed and is developed. As the result of this process, an opening 42 is retained on the metallic lead 30. An etching of the pattern is executed by a chemical etching or a plasma etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuit manufacturing, and more particularly to a method of isolating defective portions of an integrated circuit to increase the yield of integrated circuit wafers.

[0002]

2. Description of the Related Art Integrated circuit wafers are manufactured with additional spare memory circuits so that defects may occur at a low rate during manufacture. The circuit is tested to determine if any of the "first choice" circuits are defective. Then, if there is a defective circuit, it is replaced by operating the "backup" circuit. If all the "first candidate" circuits are not defective, the backup circuit becomes an extra circuit.

At the end of the test, the defective circuit will be disconnected and the logic associated with that portion of the circuit will replace the failed memory cell with a "backup" cell.

Using standard techniques, polycrystals
Explosion of a silicon line by a laser beam (exp
coded). Appropriate wavelengths are used to heat the silicon and cause a blast or a half blast, which causes the silicon to melt or evaporate, breaking the line.

Polysilicon is used in the prior art. To remove the defective memory cell, the polyline leads are heated to a high temperature and evaporated. Any remaining silicon reacts with the atmosphere to silicon dioxide.
Silicon dioxide is non-conductive in this process. If you perform the same type of treatment to heat aluminum with a laser, aluminum oxide is formed,
It is a semiconductor. What cannot be really removed by laser burning is a conductive ceramic. Conductive ceramics cannot be used as a complete high resistance path because there is always a small amount of current or potential leakage.

If laser burning is not used,
The use of polyfuses in multilevel metal lines requires extensive oxide etch to provide the required oxide removal from the polysilicon fuses. For devices with four levels of metal wiring, the oxide thickness can be on the order of 4 microns or 5 microns. In that case, a very complicated etching process including an additional patterning step is required to solve this problem. In addition, a large area is needed for the pattern and etch bias to perform such an etch.

If the oxide thickness is less than 1 to 2 microns, the method described above is sufficient. Problems with this method occur when patterning multilevel metallizations with four or more metal layers on the circuit. The result of such patterning is a large amount of oxide overlying the polyfuse. The design process would use the top metal layer to make the fuse.

Referring to FIG. 1, there is shown a simplified side view of an integrated circuit 10 made according to the prior art. In the prior art, the polysilicon line is the fuse link 12, which is the surface 14 of crystalline silicon.
In the vicinity, the wafer surface 16 is arranged at a deep depth. According to the process flow, the line covered by the thick insulating oxide layer 18 is obtained. For each level of metal being stacked, 10,000 Angstroms or 1 micron of oxide is added and stacked. This process forms a mask and holes 20 are formed above each fuse (FIG. 2). A timed etch is performed to etch a significant amount of oxide layer 18. Wet or plasma etches are typically used. This pattern is formed before all circuits are tested, so that all fuse links are exposed. As the process flow progresses, metal bond pads emerge during this special etch, as shown. The circuit can now be tested electrically and it can be decided which fuse should be blown.

[0009]

FIG. 2 illustrates a timed etch of oxide layer 1 until each polysilicon fuse link 12 at 20 locations is nearly exposed.
Figure 8 shows a side view of integrated circuit 10 after it has been subjected to etching 8; The oxide layer 18 above each fuse link 12 is etched over the entire wafer. Problems occur when there are four or more levels of metal layer. The thickness of the oxide layer 18 can be as high as 5 to 10 microns, thus making etching very practical, if not impossible, to control.

In making integrated circuits, pattern definition and circuit etching are done at several levels, some of which include metal as a circuit component. When a repair is to be performed, a laser beam is used for the specific fuse blowing needed. However, if metal links are used, the laser beam will leave the semiconductive metal slug associated with typical high energy laser ablation fuses.

[Means for Solving the Problems]

In the method of the present invention, holes are formed only on the fuse to be cut, and no holes are formed on fuses that do not need to be cut.

The present invention combines the use of metal fuses and a laser repair system to form the required fuse opening pattern. This eliminates the patterning of all conventional fuses and the consequent difficulty in controlling the fuse oxide etch over the area required for the fuse opening. This also means that slugs are not generated during laser exposure, and that the laser spot size can be easily controlled to a spot size of at least 2 microns, resulting in higher density fuse mounting on integrated circuits. Allow to change.

The present invention relates to connecting links to defective circuits, preferably SiO, all covered by photoresist.
_2. A method for isolating defective circuits on an integrated circuit having a base layer with a conductor having a coating. The method includes selectively exposing a photoresist overlying the conductive links to light and dissolving the exposed photoresist with a developer that dissolves the exposed photoresist. The coated conductor is dissolved or etched with a second predetermined liquid. The melted coated conductor is washed away to remove the conductive path to the defective circuit.

The present invention provides a solution to the problem of defective circuit isolation, and provides a laser repair method and fuse patterning in one.
They are assembled into one process. When making integrated circuits,
Pattern definition and circuit etching are done at several levels, some of which include metal as a circuit component. After pattern definition and top level metal etching,
A typical suppression oxide is deposited. Patterning and etching are performed to expose the test bonding pads of the chip. After the test, the wafer is coated with a photosensitive resist. A laser is used to expose the photoresist to expose the fuse. Depending on where the defect is in the circuit, the corresponding fuse is etched, disconnecting that particular circuit part from and connecting to another part. Etching is performed to blow the metal fuse, which avoids the metal slugs associated with typical high energy laser ablation type fuses. In fact, this method is being used to repair integrated circuits.

[0015]

DETAILED DESCRIPTION OF THE INVENTION As already mentioned, when making integrated circuits, pattern definition and circuit etching are done at several levels, some of which include metal as a circuit component. The method of the present invention is described as a one level device for simplicity. The method includes the following steps.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIGS. 3A-3E, the method of the present invention is shown. The first step in the wafer fabrication shown in FIG. 3A is the placement of aluminum leads 30 on an insulating layer or base 32. A metal line, on the order of 1 to 2 microns wide (1 micron is 10 ^-8 cm), is placed on the insulating base.

In the second step, as shown in FIG. 3B,
Silicon dioxide or equivalent insulating layer 34 leads 30
Is added over. Insulating layer 34 is typically deposited by plasma enhanced chemical vapor deposition. In the preferred embodiment,
The insulating layer 34 is silicon dioxide, but any similar insulating material currently used in the art can be used. Additional insulating layers 34, also preferably based on silicon dioxide, may be deposited on the metal leads 30.

The third step is shown in FIG. 3C, in which an organic polymer 36 called photoresist is uniformly coated over the aluminum leads 30 covered with an insulating layer 34 deposited by plasma enhanced chemical vapor deposition. Is spun on. In the present invention, the resist is a photosensitive polymeric material that is spin coated onto the wafer. Photoresist 3
6 is spin-coated to cover the entire surface of the wafer, and thus the entire surface of the wafer is covered. A chunk of photoresist material is placed in the center of the wafer and the wafer is spun at high speed.
By doing so, the photoresist 36 is applied thinly so as to cover the entire surface of the wafer. After wafer application, a laser system 40 is used to expose the photosensitive resist covering the fuses that need to be blown.

In the fourth step, as shown in FIG. 3D,
Laser system 40 exposes photoresist 36, rendering it soluble in a solvent, thereby forming a pattern. The photopolymer is an organic resin containing a photoactive compound. The exposure to the laser beam causes a chemical reaction in the exposed area, increasing the solubility in the developing solution. After exposure, the resist is developed.

A photoresist 36, which is actually light sensitive, is used to expose the area over the leads 30 to be removed to a laser beam of the appropriate wavelength. In the preferred embodiment, photoresist 36 is typically 436 nanometer sensitive or 365 nanometer sensitive.
Laser system 40 need not match its peak energy with either of the two wavelengths above, as long as it can deliver sufficient energy at either of those wavelengths. The laser can be any type of laser currently used in the art as long as it is sufficient to drive the reaction of the photoactive compound in the resist material.

Through this process, photoresist 3
6 is exposed and developed. The result of this process is an opening 42 left over the metal lead 30. An essentially rectangular exposure is performed, leaving areas in the photoresist 36 to be removed by development. The light actually breaks the bonds in the photoresist 36, creating a portion of the photoresist 36 that is soluble in the predetermined solvent. The portion exposed to light of the appropriate wavelength can then be rinsed and washed away. After this process, the oxide insulating layer 34 covering the metal leads 30 is left, leaving the mask with the openings 42.

In the fifth step, as shown in FIG. 3E,
This pattern of etching is performed by chemical or plasma etching. That is, the oxide insulating layer 3
A conventional etch can be used to etch both 4 and the metal leads 30. When performing the etch, this etch does not etch the polymeric material of photoresist 36. This polymer blocks etch everywhere except where it was exposed and developed. This allows for very high resistance open circuits and does not generate slugs that can cause deposition or shorts at undesired locations on the chip. This results in holes and after everything is etched away, it leaves a circuit open to defective memory or other circuitry. In the preferred embodiment, a plasma etch was used to etch both the oxide insulation layer 34 and the metal leads 30. This etching may be plasma etching or wet etching. Any type of etch chemistry can be used as long as it etches both the oxide insulating layer 34 and the metal leads 30. The final product is a structure with metal leads 30 cut in openings 42 and including photoresist 36 on oxide or insulating layer 34. A wet or reactive ion etch was applied to remove this material. Typically,
By removing the metal leads 30 that connect the memory circuit, the conductive path to the memory circuit is removed. By using the method of the present invention, accurate and clean cutting of the metal leads 30 is achieved.

While particular embodiments of the present invention have been illustrated and described, it will be appreciated by those skilled in the art that numerous changes and modifications can be made, and the scope of the appended claims should be construed as such true of the invention. It is to be understood that it should be construed to include all changes and modifications included in the spirit and perspective.

With respect to the above description, the following items will be further disclosed. (1) A method for isolating a defective circuit on an integrated circuit, comprising the steps of: providing a base layer to the defective circuit, the base layer having a conductor connector covered by an insulating layer. Providing a base layer in which the layers, conductors, and insulating layers are covered by a photoresist material, and applying a laser beam to a location to cover a predetermined portion of the photoresist to cover the conductor of the photoresist material. Selectively exposing a portion to high-energy light, and at the same time avoiding the formation of slugs at the location of the conductor, developing the exposed photoresist material with a predetermined liquid, Rinsing the exposed photoresist material and dissolving the conductor covered by the insulating layer by a predetermined chemical reaction to cause the defects The method comprising removing a conductive path to the road, essentially providing the opening with no metal slug in the photoresist, the.

(2) The method according to item 1, wherein the melting step includes a wet etching process.

(3) The method according to item 1, wherein the melting step includes a dry etching process.

(4) The method according to item 1, wherein the laser light has a wavelength of about 436 nanometers.

(5) The method according to item 1, wherein the laser light has a wavelength of about 365 nanometers.

(6) A method for isolating a defective circuit on an integrated circuit having a base layer with conductor connections to the defective circuit, all covered by a photoresist material and covered by an insulating layer. Next step: selectively exposing the photoresist material covering the conductor to light by exposing the coating of the photoresist material to laser light having a wavelength of 436 nanometers, the exposing. Developing the photoresist material with a predetermined liquid, washing away the exposed photoresist material, and dissolving the conductor coated with the insulating layer in a wet etch process to conduct to the defective circuit. Removing the sexual pathway.

(7) The method according to item 1, wherein the laser beam is focused to a maximum width of about 2 microns.

(8) The method of claim 7, wherein the laser beam is capable of exposing a predetermined portion of the photoresist without producing a slight amount of metal slug at the location of the conductor. The way it became.

(9) To isolate a defective circuit on an integrated circuit having a base layer 32 with an oxide insulating layer 34 covering a conductor connection 30 to the defective circuit, all covered by a photo-sensitive polymer 36. Selectively exposing the polymer 36 covering the conductor to light.
Developing the exposed polymer 36 with a predetermined liquid to wash away the exposed polymer;
Melting the oxide insulating layer 34 overlying it by a second predetermined chemical reaction and removing the conductive path to the defective circuit.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a circuit manufactured by a conventional technique.

FIG. 2 is a cross-sectional view showing a conventional circuit isolation method by interrupting a fuse.

3A to 3E are cross-sectional views showing a circuit isolation method of the present invention.

[Explanation of symbols]

 10 Integrated Circuit 12 Fuse Link 14 Surface of Silicon Crystal 16 Wafer Surface 18 Oxide Layer 20 Hole 30 Aluminum Lead 32 Base Layer 34 Insulating Layer 36 Photoresist Layer 40 Laser System 42 Opening

Continuation of the front page (72) Inventor Ricky A. Jackson 3303 Fox Creek, Richardson, Texas, United States

Claims (1)

[Claims] 1. A method for isolating defective circuits on an integrated circuit, the method comprising the steps of: providing a base layer with a conductor connector covered by an insulating layer to the defective circuits, Providing a base layer in which the base layer, a conductor, and an insulating layer are covered by a photoresist material; applying a laser beam to a location to cover a predetermined portion of the photoresist, the conductor of the photoresist material Selectively exposing the portion covering the to high-energy light, and at the same time avoiding the generation of slugs at the location of the conductor, developing the exposed photoresist material with a predetermined liquid. Washing away the exposed photoresist material, and dissolving the conductor covered by the insulating layer by a predetermined chemical reaction, How the serial removal of the conductive path to the defective circuit, comprising, providing an essentially free of metal slug opening in the photoresist.