JPH08339971A - Manufacture of electronic part - Google Patents

Manufacture of electronic part

Info

Publication number
JPH08339971A
JPH08339971A JP7144607A JP14460795A JPH08339971A JP H08339971 A JPH08339971 A JP H08339971A JP 7144607 A JP7144607 A JP 7144607A JP 14460795 A JP14460795 A JP 14460795A JP H08339971 A JPH08339971 A JP H08339971A
Authority
JP
Japan
Prior art keywords
film
electrode
sio2
resist pattern
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7144607A
Other languages
Japanese (ja)
Inventor
宗子 ▲高▼橋
Muneko Takahashi
Toshio Sugawa
俊夫 須川
Keizaburo Kuramasu
敬三郎 倉増
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7144607A priority Critical patent/JPH08339971A/en
Publication of JPH08339971A publication Critical patent/JPH08339971A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Formation Of Insulating Films (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

PURPOSE: To simplify the formation of electrodes by forming a photoresist layer on a SiO2 -based film formed on a substrate, removing the film and the photoresist from electrode formation areas to obtain electrodes, and then dissolving the SiO2 film in HF solution. CONSTITUTION: A porous SiO2 -based film 2 is formed on the surface of a piezoelectric substrate 1 by CVD at relatively low temperature. A resist pattern 3a is formed on the film 2, and the film 2 is etched using the resist pattern as a mask so that the SiO2 film 2 will be smaller than the area of the resist pattern 3a. Au/Cr electrodes 4 are evaporated using the resist pattern 3a and the SiO2 film 2 as an evaporation mask. Then the workpiece is immersed in HF solution, and the SiO2 film is thereby dissolved to obtain electrodes 4. The porous quality of the SiO2 film 2 facilitates the osmosis of HF and makes the SiO film 2 easily soluble even in HF of low concentration.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、基板上に電極パターン
を形成する電子部品の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic component in which an electrode pattern is formed on a substrate.

【０００２】[0002]

【従来の技術】従来、基板上に電極パターンを形成する
一般的な方法として、基板上にレジストパターンを形成
し、電極を蒸着により形成し、次にレジストを除去する
リフトオフ法が用いられていた。2. Description of the Related Art Conventionally, as a general method for forming an electrode pattern on a substrate, a lift-off method has been used in which a resist pattern is formed on a substrate, electrodes are formed by vapor deposition, and then the resist is removed. .

【０００３】[0003]

【発明が解決しようとする課題】上記方法では、レジス
トパターンを逆テーパー型に形成するのが難しく、電極
膜を形成する際に電極材料がレジスト膜をおおい囲み、
レジストを溶解させるのが困難であるという問題点を有
していた。In the above method, it is difficult to form the resist pattern in the inverse taper type, and when the electrode film is formed, the electrode material surrounds the resist film,
It has a problem that it is difficult to dissolve the resist.

【０００４】そこで本発明は電極が形成しやすい電子部
品の製造方法を提供することを目的とするものである。Therefore, an object of the present invention is to provide a method of manufacturing an electronic component in which electrodes are easily formed.

【０００５】[0005]

【課題を解決するための手段】この目的を達成するため
に、本発明は基板上にＳｉＯ2を主成分とする膜を形成
し、次にこの膜上にフォトレジストを形成し、その後こ
の基板上の電極を形成しようとする部分の前記膜とフォ
トレジストを除去し、次に少なくともこの膜を除去した
部分に電極を形成し、その後ＳｉＯ2を主成分とする膜
を、ＨＦ溶液により溶解させることによりこの膜とフォ
トレジストを除去するものである。To achieve this object, the present invention forms a SiO 2 -based film on a substrate, then forms a photoresist on the film, and then forms the substrate. The film and the photoresist in the portion where the upper electrode is to be formed are removed, and then the electrode is formed in at least the portion where the film is removed, and then the film containing SiO 2 as a main component is dissolved by an HF solution. By this, this film and the photoresist are removed.

【０００６】[0006]

【作用】この構成によると、電極を形成する際レジスト
マスクを電極材料がおおい囲むことがないので、レジス
ト膜の除去が容易にできる。According to this structure, the resist mask is not covered with the electrode material when the electrode is formed, so that the resist film can be easily removed.

【０００７】[0007]

【実施例】以下、本発明の一実施例であるＳＡＷフィル
ターについて図面を参照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A SAW filter which is an embodiment of the present invention will be described below with reference to the drawings.

【０００８】まず、図１に示すごとく圧電性基板１の表
面に、ＣＶＤ法によりＳｉＯ2を主成分とする膜２を形
成した。この膜２の膜厚が、後に設けようとする電極の
膜厚よりも薄いと、電極材料を蒸着した場合、フォトレ
ジスト３と膜２をおおい囲みリフトオフが出来ないの
で、この膜２の膜厚は後に設けようとする電極４の膜厚
よりも厚くした。この膜２は、ＣＶＤの形成条件として
基板温度を２００℃前後の比較的低温条件で形成するこ
とにより、ポーラスな膜質となるよう形成した。次にこ
の膜２の上にフォトレジスト３を形成した。次に図２に
示すようにレジストパターン３ａを設け、このレジスト
パターン３ａをマスクとして図３のごとくＳｉＯ2より
なる膜２のエッチングを行い、ＳｉＯ2のパターン形成
を行った。このエッチングは、逆テーパー型になるよう
等方性エッチングまたはそれに近い方法で行い、ＳｉＯ
2の膜２がレジストパターン３ａの面積よりも小さくな
るようにした。次に、このような方法で形成したレジス
トパターン３ａとＳｉＯ2膜２のパターンを蒸着マスク
として、Ａｕ／Ｃｒの電極４を図４のように蒸着法で形
成した。この電極４の膜厚は先に形成したＳｉＯ2の膜
２の厚みよりも薄くし、電極４がレジストパターン３ａ
とＳｉＯ2の膜２をおおい囲まないようにした。次にＨ
Ｆの水溶液に基板１ごと浸漬してＳｉＯ2の膜２を溶解
し、図５の電極４を形成した。先に形成されたＳｉＯ2
の膜２は、膜質がポーラスであるのでＨＦが浸透しやす
く低濃度のＨＦにも容易に溶解し、簡単に除去できる。
また、基板１と電極４はＨＦ溶液に溶けない。First, as shown in FIG. 1, a film 2 containing SiO 2 as a main component was formed on the surface of a piezoelectric substrate 1 by a CVD method. If the film thickness of this film 2 is smaller than the film thickness of an electrode to be provided later, when the electrode material is vapor-deposited, the photoresist 3 and the film 2 cannot be covered and lift-off cannot be performed. Was made thicker than the film thickness of the electrode 4 to be provided later. The film 2 was formed so as to have a porous film quality by forming it under a relatively low temperature condition of a substrate temperature of about 200 ° C. as a CVD forming condition. Next, a photoresist 3 was formed on this film 2. Then provided the resist pattern 3a as shown in FIG. 2, the resist pattern 3a the etched film 2 made of SiO 2 as in FIG. 3 as a mask, a pattern was formed SiO 2. This etching is performed by isotropic etching or a method close to it so as to form a reverse taper type, and
Second film 2 was set to be smaller than the area of the resist pattern 3a. Next, using the resist pattern 3a and the pattern of the SiO 2 film 2 formed by such a method as an evaporation mask, an Au / Cr electrode 4 was formed by an evaporation method as shown in FIG. The film thickness of this electrode 4 is made thinner than that of the SiO 2 film 2 previously formed, and the electrode 4 is formed into the resist pattern 3a.
And the SiO 2 film 2 was not covered. Then H
The substrate 1 was immersed in an aqueous solution of F to dissolve the SiO 2 film 2 to form an electrode 4 in FIG. SiO 2 formed earlier
Since the membrane 2 has a porous film quality, it is easily permeated by HF, is easily dissolved in low-concentration HF, and can be easily removed.
Moreover, the substrate 1 and the electrode 4 are not dissolved in the HF solution.

【０００９】なお、本実施例においてはＳＡＷフィルタ
ーを例に説明したが、誘電体フィルター等他の電極パタ
ーン形成を必要とする電子部品においても同じ効果が得
られる。また、今回例に挙げたＡｕ／Ｃｒの電極４の他
に、ＰｔやＣｕ電極についても同様に形成できる。Although the SAW filter has been described as an example in the present embodiment, the same effect can be obtained in an electronic component such as a dielectric filter which requires electrode pattern formation. Further, in addition to the Au / Cr electrode 4 given in this example, Pt and Cu electrodes can be similarly formed.

【００１０】[0010]

【発明の効果】以上本発明によると、基板上にフォトレ
ジストとＳｉＯ2の膜を形成するので、逆テーパーのパ
ターンが形成しやすく、電極形成の際電極材料がレジス
トパターンをおおい囲むことがないのでＳｉＯ2の膜が
容易に除去できる。As described above, according to the present invention, since the photoresist and the SiO 2 film are formed on the substrate, an inverse taper pattern is easily formed, and the electrode material does not surround the resist pattern during electrode formation. Therefore, the SiO 2 film can be easily removed.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例において基板上にフォトレジ
ストとＳｉＯ2の膜を形成する工程を説明する断面図FIG. 1 is a cross-sectional view illustrating a step of forming a photoresist and a SiO 2 film on a substrate according to an embodiment of the present invention.

【図２】本発明の一実施例においてレジストパターン形
成を説明する断面図FIG. 2 is a cross-sectional view illustrating formation of a resist pattern in one embodiment of the present invention.

【図３】本発明の一実施例においてＳｉＯ2パターン形
成を説明する断面図FIG. 3 is a cross-sectional view illustrating SiO 2 pattern formation in one example of the present invention.

【図４】本発明の一実施例において電極を形成する工程
を説明する断面図FIG. 4 is a cross-sectional view illustrating a step of forming an electrode in one embodiment of the present invention.

【図５】本発明の一実施例においてＳｉＯ2を溶解して
除去する工程を説明する断面図FIG. 5 is a cross-sectional view illustrating a step of dissolving and removing SiO 2 in one example of the present invention.

【符号の説明】[Explanation of symbols]

１ 基板 ２ ＳｉＯ2の膜 ３ フォトレジスト ４ 電極1 substrate 2 SiO 2 film 3 photoresist 4 electrode

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 基板上にＳｉＯ2を主成分とする膜を形
成し、次にこの膜上にフォトレジストを形成し、その後
この基板上の電極を形成しようとする部分の前記膜とフ
ォトレジストを除去し、次に少なくともこの膜を除去し
た部分に電極を形成し、その後ＳｉＯ2を主成分とする
膜を、ＨＦ溶液により溶解させることによりこの膜とフ
ォトレジストを除去する電子部品の製造方法。1. A film comprising SiO 2 as a main component is formed on a substrate, then a photoresist is formed on the film, and then the film and the photoresist on a portion of the substrate where an electrode is to be formed. Is removed, and then an electrode is formed at least in a portion where the film is removed, and then the film containing SiO 2 as a main component is dissolved in an HF solution to remove the film and the photoresist. . 【請求項２】 ＳｉＯ2を主成分とする膜はＣＶＤ法に
よりポーラスな膜質となるように形成する請求項１記載
の電子部品の製造方法。2. The method of manufacturing an electronic component according to claim 1, wherein the film containing SiO 2 as a main component is formed by a CVD method so as to have a porous film quality. 【請求項３】 ＳｉＯ2を主成分とする膜は、形成しよ
うとする電極の厚みよりも厚くする請求項１記載の電子
部品の製造方法。3. The method of manufacturing an electronic component according to claim 1, wherein the film containing SiO 2 as a main component is thicker than the thickness of the electrode to be formed. 【請求項４】 形成しようとする電極と、その基板は、
ＨＦ溶液により溶解されない材料を用いる請求項１記載
の電子部品の製造方法。4. The electrode to be formed and its substrate are
The method of manufacturing an electronic component according to claim 1, wherein a material that is not dissolved by the HF solution is used. 【請求項５】 ＳｉＯ2を主成分とする膜が、上のレジ
ストパターンの面積よりも小さくなるようにエッチング
する請求項１記載の電子部品の製造方法。5. The method of manufacturing an electronic component according to claim 1, wherein etching is performed such that the film containing SiO 2 as a main component is smaller than the area of the resist pattern above.
JP7144607A 1995-06-12 1995-06-12 Manufacture of electronic part Pending JPH08339971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7144607A JPH08339971A (en) 1995-06-12 1995-06-12 Manufacture of electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7144607A JPH08339971A (en) 1995-06-12 1995-06-12 Manufacture of electronic part

Publications (1)

Publication Number Publication Date
JPH08339971A true JPH08339971A (en) 1996-12-24

Family

ID=15365966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7144607A Pending JPH08339971A (en) 1995-06-12 1995-06-12 Manufacture of electronic part

Country Status (1)

Country Link
JP (1) JPH08339971A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002031974A1 (en) * 2000-10-12 2002-04-18 Fujitsu Limited Surface acoustic wave device and method of producing the same
WO2019171476A1 (en) * 2018-03-06 2019-09-12 新日本無線株式会社 Method for manufacturing surface acoustic wave element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002031974A1 (en) * 2000-10-12 2002-04-18 Fujitsu Limited Surface acoustic wave device and method of producing the same
WO2019171476A1 (en) * 2018-03-06 2019-09-12 新日本無線株式会社 Method for manufacturing surface acoustic wave element
JPWO2019171476A1 (en) * 2018-03-06 2021-02-18 新日本無線株式会社 Manufacturing method of surface acoustic wave element

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