JPH08335777A - Multilayer thin film wiring board - Google Patents

Multilayer thin film wiring board

Info

Publication number
JPH08335777A
JPH08335777A JP7140502A JP14050295A JPH08335777A JP H08335777 A JPH08335777 A JP H08335777A JP 7140502 A JP7140502 A JP 7140502A JP 14050295 A JP14050295 A JP 14050295A JP H08335777 A JPH08335777 A JP H08335777A
Authority
JP
Japan
Prior art keywords
film
circuit wiring
wiring
insulating
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7140502A
Other languages
Japanese (ja)
Inventor
Naohito Ide
尚人 井手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP7140502A priority Critical patent/JPH08335777A/en
Publication of JPH08335777A publication Critical patent/JPH08335777A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE: To provide a multilayer thin film wiring board in which the outer lead terminals are secured rigidly to an insulating board while preventing the delamination of an insulating film from the insulating board or the fluctuation of characteristics by fusion and each electronic device, connected with the circuit wiring film, can be electrically connected reliably and rigidly with other external electric circuit board through outer lead terminals. CONSTITUTION: An insulating film 3 of organic high polymer material and a circuit wiring film 2 of metal material are laminated alternately in multilayer on an insulating board 1 having a metallization layer 4 by thin film preparation technology. The metallization layer 4 is connected electrically with the circuit wiring film 2 and bonded with outer lead terminals 5 by ultrasonic bonding.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は混成集積回路装置や半導
体素子収納用パッケージ等に用いられる多層薄膜配線基
板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer thin film wiring board used in a hybrid integrated circuit device, a package for accommodating semiconductor elements, and the like.

【0002】[0002]

【従来の技術】従来、混成集積回路装置や半導体素子収
納用パッケージ等に使用される配線基板はその回路配線
がMoーMn法等の厚膜形成技術によって形成されてい
る。
2. Description of the Related Art Conventionally, a wiring board used for a hybrid integrated circuit device, a package for accommodating a semiconductor element, or the like has its circuit wiring formed by a thick film forming technique such as a Mo--Mn method.

【0003】このMoーMn法は、タングステン、モリ
ブデン、マンガン等の高融点金属から成る金属粉末に有
機溶剤、溶媒を添加し、ペースト状となした金属ペース
トを生もしくは焼結セラミック体の外表面にスクリーン
印刷法により回路配線としての所定パターンに印刷塗布
し、次にこれを還元雰囲気中で焼成し、高融点金属粉末
とセラミック体とを焼結一体化させる方法である。
In the Mo-Mn method, an organic solvent and a solvent are added to a metal powder made of a refractory metal such as tungsten, molybdenum, and manganese to form a paste-like metal paste on the outer surface of a green or sintered ceramic body. In this method, a predetermined pattern as a circuit wiring is printed and applied by a screen printing method, and then this is baked in a reducing atmosphere to sinter and integrate the high melting point metal powder and the ceramic body.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このM
oーMn法を用いて回路配線を形成した場合、回路配線
は金属ペーストをスクリーン印刷することにより形成さ
れることから回路配線の微細化が困難であり、回路配線
の高密度化ができないという欠点を有していた。
However, this M
When the circuit wiring is formed by using the o-Mn method, it is difficult to miniaturize the circuit wiring because the circuit wiring is formed by screen-printing a metal paste, and the circuit wiring cannot be densified. Had.

【0005】そこで上記欠点を解消するために回路配線
を従来の厚膜形成技術により形成するのに替えて微細化
が可能な薄膜形成技術を用いて形成した多層薄膜配線基
板が使用されるようになってきた。
Therefore, in order to solve the above-mentioned drawbacks, instead of forming the circuit wiring by the conventional thick film forming technique, a multilayer thin film wiring substrate formed by using a thin film forming technique capable of miniaturization is used. It's coming.

【0006】この回路配線を薄膜形成技術により形成し
た多層薄膜配線基板は、通常、酸化アルミニウム質焼結
体やムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスセラミックス焼結体等から成
り、上面から下面にかけてタングステン、モリブデン、
マンガン等から成るメタライズ配線層が被着されている
絶縁基板上にアルミニウム、銅、クロム、ニッケル等か
ら成る回路配線膜とポリイミド等の有機高分子材料から
成る絶縁膜とを交互に多層に被着させ、前記回路配線膜
の一部をメタライズ配線層に電気的に接続させるととも
に絶縁基板下面に導出するメタライズ配線層に外部リー
ド端子を銀ロウ材(銀ー銅合金)を介し取着させた構造
を有しており、回路配線膜に半導体素子やコンデンサ等
の電極を半田を介し接続させれば、半導体素子やコンデ
ンサ等の各電子部品はその各々が回路配線膜を介して互
いに電気的に接続され、また外部リード端子を他の外部
電気回路基板に接続すれば、回路配線膜に接続されてい
る各電子部品は回路配線膜、メタライズ配線層及び外部
リード端子を介し外部電気回路基板に電気的に接続され
るようになっている。尚、前記多層薄膜配線基板は絶縁
基板の上面にアルミニウム、銅、クロム、ニッケル等か
ら成る回路配線膜とポリイミド等の有機高分子材料から
成る絶縁膜とを交互に多層に被着させた後、絶縁基板下
面に導出するメタライズ配線層に外部リード端子を取着
している。これは絶縁基板上に回路配線膜を所定パター
ンに被着させるのにエッチング加工が採用されており、
該エッチング加工の際のエッチング液が絶縁基板の下面
に取着されている外部リード端子を不必要に腐食してし
まうのを防止するためである。
The multilayer thin film wiring substrate formed with this circuit wiring by the thin film forming technique is usually an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, or a glass ceramic. It consists of a sintered body, etc., and tungsten, molybdenum,
A circuit wiring film made of aluminum, copper, chromium, nickel, etc. and an insulating film made of an organic polymer material such as polyimide are alternately applied in multiple layers on an insulating substrate on which a metallized wiring layer made of manganese or the like is applied. A structure in which a part of the circuit wiring film is electrically connected to the metallized wiring layer and external lead terminals are attached to the metallized wiring layer led out to the lower surface of the insulating substrate through a silver brazing material (silver-copper alloy). By connecting electrodes such as semiconductor elements and capacitors via solder to the circuit wiring film, each electronic component such as semiconductor elements and capacitors is electrically connected to each other through the circuit wiring film. If the external lead terminal is connected to another external electric circuit board, each electronic component connected to the circuit wiring film will pass through the circuit wiring film, the metallized wiring layer and the external lead terminal. It is adapted to be electrically connected to the part an electrical circuit board. Incidentally, the multilayer thin film wiring board, after the circuit wiring film made of aluminum, copper, chromium, nickel or the like and the insulating film made of an organic polymer material such as polyimide are alternately laminated on the upper surface of the insulating substrate, External lead terminals are attached to the metallized wiring layer leading out to the lower surface of the insulating substrate. This is an etching process that is used to deposit a circuit wiring film in a predetermined pattern on an insulating substrate.
This is to prevent unnecessary etching of the external lead terminals attached to the lower surface of the insulating substrate by the etching solution during the etching process.

【0007】しかしながら、前記多層薄膜配線基板にお
いては絶縁膜を形成するポリイミド等、有機高分子材料
の耐熱性が劣ること、絶縁基板の熱膨張係数と絶縁膜の
熱膨張係数に大きな差を有していること等から上面に回
路配線膜と絶縁膜を交互に多層に被着させた絶縁基板の
下面に外部リード端子を銀ロウ材(銀ー銅合金)を介し
て取着する際、銀ロウ材を加熱溶融させるための熱が絶
縁膜と絶縁基板との両者に印加されると絶縁膜が絶縁基
板より剥離したり、絶縁膜が溶融して特性に変化をきた
してしまい、その結果、多層薄膜配線基板としての機能
が喪失してしまうという欠点が誘発される。
However, in the above-mentioned multilayer thin film wiring board, the heat resistance of the organic polymer material such as polyimide for forming the insulating film is poor, and there is a large difference between the thermal expansion coefficient of the insulating substrate and the thermal expansion coefficient of the insulating film. Therefore, when the external lead terminals are attached to the lower surface of the insulating substrate in which the circuit wiring film and the insulating film are alternately laminated on the upper surface through the silver solder material (silver-copper alloy), the silver solder is used. When heat for heating and melting the material is applied to both the insulating film and the insulating substrate, the insulating film peels off from the insulating substrate, or the insulating film melts to change the characteristics, resulting in a multilayer structure. The defect that the function as a thin film wiring board is lost is induced.

【0008】[0008]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は絶縁膜の絶縁基板からの剥離や溶融によ
る特性変化を有効に防止しつつ絶縁基板に外部リード端
子を強固に取着し、回路配線膜に接続される各電子部品
を外部リード端子を介して他の外部電気回路基板に確
実、強固に電気的接続することができる多層薄膜配線基
板を提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to firmly prevent external lead terminals on an insulating substrate while effectively preventing characteristic changes due to peeling or melting of the insulating film from the insulating substrate. An object of the present invention is to provide a multilayer thin-film wiring board that can be securely attached to each external electronic circuit board that is attached and connected to a circuit wiring film to another external electric circuit board through external lead terminals.

【0009】[0009]

【課題を解決するための手段】本発明の多層薄膜配線基
板はメタライズ配線層を有する絶縁基板上に薄膜形成技
術より有機高分子材料から成る絶縁膜と金属材料から成
る回路配線膜とを交互に多層に積層してなり、前記メタ
ライズ配線層に前記回路配線膜を電気的に接続させると
ともに、外部リード端子を超音波接合により接合させた
ことを特徴とするものである。
A multilayer thin film wiring substrate of the present invention comprises an insulating substrate having a metallized wiring layer, and an insulating film made of an organic polymer material and a circuit wiring film made of a metal material are alternately formed on the insulating substrate by a thin film forming technique. It is laminated in multiple layers, and the circuit wiring film is electrically connected to the metallized wiring layer, and external lead terminals are bonded by ultrasonic bonding.

【0010】[0010]

【作用】本発明の多層薄膜配線基板によれば、回路配線
膜を薄膜形成技術より形成したことから回路配線膜の微
細化が可能で、回路配線膜の高密度化が達成できる。
According to the multilayer thin film wiring board of the present invention, since the circuit wiring film is formed by the thin film forming technique, the circuit wiring film can be miniaturized and the circuit wiring film can be made high in density.

【0011】また本発明の多層薄膜配線基板によれば、
絶縁基板に被着させたメタライズ配線層に外部リード端
子を超音波接合により接合させることから、外部リード
端子を取着する際に絶縁基板及び絶縁膜に不要な熱が印
加されることはなく、これによって絶縁膜は特性に変化
をきたすことなく絶縁基板に強固に被着し、回路配線膜
に接続される各電子部品を外部リード端子を介して他の
外部電気回路基板に確実、強固に電気的接続することが
できる。
According to the multilayer thin film wiring board of the present invention,
Since the external lead terminals are joined by ultrasonic bonding to the metallized wiring layer adhered to the insulating substrate, unnecessary heat is not applied to the insulating substrate and the insulating film when attaching the external lead terminals, As a result, the insulating film is firmly adhered to the insulating substrate without changing the characteristics, and each electronic component connected to the circuit wiring film is securely and firmly electrically connected to another external electric circuit board via the external lead terminals. Can be connected.

【0012】[0012]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1は本発明の多層薄膜配線基板の一実施例を示し
1は絶縁基板、2は回路配線膜、3は絶縁膜である。
The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a multilayer thin film wiring board according to the present invention, wherein 1 is an insulating substrate, 2 is a circuit wiring film, and 3 is an insulating film.

【0013】前記絶縁基板1は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスセラミックス焼結体等から成
り、絶縁基板1が例えば、酸化アルミニウム質焼結体か
らなる場合には、アルミナ、シリカ、マグネシア、カル
シア等の原料粉末に適当な有機溶剤、溶媒を添加混合し
て泥漿状となすとともにこれをドクターブレード法やカ
レンダーロール法等を採用することによってセラミック
グリーンシート(セラミック生シート)を形成し、しか
る後、前記セラミックグリーンシートに適当な打ち抜き
加工を施し、所定形状となすとともに高温(約1600
℃)で焼成することによって製作される。
The insulating substrate 1 is made of an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic sintered body, or the like. When it is composed of an aluminum oxide sintered body, alumina, silica, magnesia, calcia, etc. are mixed with a suitable organic solvent and a solvent to form a sludge and a doctor blade method or calender roll method is used. To form a ceramic green sheet (ceramic green sheet), and then subject the ceramic green sheet to an appropriate punching process to form a predetermined shape and a high temperature (about 1600).
It is manufactured by firing at (° C).

【0014】前記絶縁基板1の上面には回路配線膜2と
絶縁膜3とを交互に多層に配した多層配線部Aが被着さ
れており、該絶縁基板1は多層配線部Aを支持する支持
部材として作用する。
On the upper surface of the insulating substrate 1, a multi-layer wiring portion A in which circuit wiring films 2 and insulating films 3 are alternately arranged in multiple layers is adhered, and the insulating substrate 1 supports the multi-layer wiring portion A. Acts as a support member.

【0015】また前記絶縁基板1にはその上面から下面
にかけて導出するメタライズ配線層4が被着形成されて
おり、該メタライズ金属層4は絶縁基板1の上面に被着
される回路配線膜2を後述する絶縁基板1の下面に取着
される外部リード端子5に電気的に接続する作用を為
す。
A metallized wiring layer 4 extending from the upper surface to the lower surface of the insulating substrate 1 is adhered and formed, and the metallized metal layer 4 covers the circuit wiring film 2 adhered to the upper surface of the insulating substrate 1. It serves to electrically connect to external lead terminals 5 attached to the lower surface of the insulating substrate 1 described later.

【0016】前記メタライズ配線層4はタングステン、
モリブデン、マンガン等の金属材料から成り、該金属材
料に適当な有機溶剤、溶媒を添加混合して得た金属ペー
ストを絶縁基板1となるセラミックグリーンシートの上
下面及びセラミックグリーンシートに孔開け加工法を施
すことによって形成した貫通孔内に従来周知のスクリー
ン印刷法等により所定パターンに印刷充填しておくこと
によって絶縁基板1の上面から下面にかけて被着形成さ
れる。
The metallized wiring layer 4 is made of tungsten,
A method of forming a hole in the upper and lower surfaces of the ceramic green sheet and the ceramic green sheet which will be the insulating substrate 1 and is made of a metal material such as molybdenum or manganese, and a metal paste obtained by adding and mixing an appropriate organic solvent or solvent to the metal material. A predetermined pattern is printed and filled in the through hole formed by applying a known pattern by a screen printing method or the like, so that the insulating substrate 1 is adhered and formed from the upper surface to the lower surface.

【0017】前記メタライズ配線層4が被着された絶縁
基板1は更にその上面に回路配線膜2と絶縁膜3が交互
に多層に被着されており、該回路配線膜2と絶縁膜3と
で多層配線部Aが形成されている。
The insulating substrate 1 to which the metallized wiring layer 4 has been applied further has circuit wiring films 2 and insulating films 3 alternately and multilayerly deposited on the upper surface thereof. Thus, the multi-layer wiring part A is formed.

【0018】前記多層配線部Aの回路配線膜2は、例え
ばアルミニウム、銅、クロム、ニッケル等の金属材料か
ら成り、蒸着法やスパッタリング法等の薄膜形成技術及
びエッチング加工技術を採用することによって絶縁基板
1上で、間に絶縁膜3を挟んで多層に被着形成される。
この場合、回路配線膜2は薄膜形成技術により形成され
ることから回路配線膜2の微細化が可能となり回路配線
膜2を高密度に形成することができる。
The circuit wiring film 2 of the multi-layer wiring portion A is made of a metal material such as aluminum, copper, chromium, nickel or the like, and is insulated by employing a thin film forming technique such as a vapor deposition method or a sputtering method and an etching processing technique. A plurality of layers are formed on the substrate 1 with the insulating film 3 interposed therebetween.
In this case, since the circuit wiring film 2 is formed by the thin film forming technique, the circuit wiring film 2 can be miniaturized and the circuit wiring film 2 can be formed with high density.

【0019】前記回路配線膜2はその一部が絶縁基板1
に被着させたメタライズ配線層4に接触しており、回路
配線膜2に半導体素子6やコンデンサ7等の電子部品を
半田を介して接続すれば該半導体素子6やコンデンサ7
等の電子部品は回路配線膜2を介して各々が電気的に接
続されるとともに所定のメタライズ配線層4に電気的に
接続されることとなる。
A part of the circuit wiring film 2 is an insulating substrate 1.
If the electronic components such as the semiconductor element 6 and the capacitor 7 are connected to the circuit wiring film 2 through solder, the semiconductor element 6 and the capacitor 7 are in contact with the metallized wiring layer 4 attached to the semiconductor element 6 and the capacitor 7.
The electronic components such as the above are electrically connected to each other through the circuit wiring film 2 and also electrically connected to a predetermined metallized wiring layer 4.

【0020】尚、前記回路配線膜2はその厚みが0.0
5μm未満であると回路配線膜2の電気抵抗が大きなも
のになるとともに回路配線膜2にピンホールや断線が発
生し易いものとなる傾向にあり、また30μmを越える
と回路配線膜2を薄膜形成技術により形成する際の内部
応力によって回路配線膜2が絶縁膜3より剥離し易くな
るとともに該回路配線膜2の微細加工が困難となる傾向
にあることから0.05μm乃至20μmの範囲が良
く、好適には1μm乃至5μmの厚みに、最適には2μ
m乃至3μmの厚みにしておくことが良い。
The circuit wiring film 2 has a thickness of 0.0.
If it is less than 5 μm, the electric resistance of the circuit wiring film 2 tends to be large, and at the same time, pinholes and disconnections tend to occur in the circuit wiring film 2, and if it exceeds 30 μm, the circuit wiring film 2 is formed into a thin film. The range of 0.05 μm to 20 μm is preferable because the circuit wiring film 2 tends to peel off from the insulating film 3 due to internal stress when formed by the technique and the fine processing of the circuit wiring film 2 tends to be difficult. Suitably 1 μm to 5 μm thick, optimally 2 μm
It is preferable to set the thickness to m to 3 μm.

【0021】また前記回路配線膜2の間には絶縁膜3が
配されており、該絶縁膜3は上下に位置する各回路配線
膜2の電気的絶縁を維持する作用を為す。
An insulating film 3 is disposed between the circuit wiring films 2, and the insulating film 3 serves to maintain the electrical insulation of the circuit wiring films 2 located above and below.

【0022】前記絶縁膜3はポリイミド樹脂等の有機高
分子材料から成り、例えば4,4’ージアミノジフェニ
ルエーテル50モル%、ジアミノジフェニルスルホン5
0モル%、3,3’ービフェニルテトラカルボン酸二無
水物から成るポリマ溶液を絶縁基板1上にスピンコーテ
ィング法により塗布し、しかる後、これに約400℃の
熱を加えてポリマ溶液を熱架橋させることによって絶縁
基板1上で回路配線膜2の間に被着形成される。
The insulating film 3 is made of an organic polymer material such as polyimide resin. For example, 50 mol% of 4,4'-diaminodiphenyl ether and 5% of diaminodiphenyl sulfone.
A polymer solution consisting of 0 mol% of 3,3′-biphenyltetracarboxylic dianhydride was applied on the insulating substrate 1 by spin coating, and then heat of about 400 ° C. was applied to heat the polymer solution. By being cross-linked, it is deposited between the circuit wiring films 2 on the insulating substrate 1.

【0023】前記絶縁膜3はその厚みが1μm未満であ
ると絶縁膜3にピンホールが発生し易いものとなり、絶
縁膜3を挟んで上下に形成された回路配線膜2間の電気
的絶縁を図ることが困難となる傾向にあり、また50μ
mを越えると絶縁膜3を挟んで上下に形成された回路配
線膜2を互いに電気的に接続するための導電路となるビ
アホールを絶縁膜3に正確に形成することが困難となる
傾向にあることから1μm乃至50μmの範囲が良く、
好適には2μm乃至10μmの厚みに、最適には3μm
乃至5μmの厚みにしておくことが良い。
If the thickness of the insulating film 3 is less than 1 μm, pinholes are likely to be generated in the insulating film 3, and the electrical insulation between the circuit wiring films 2 formed above and below the insulating film 3 is facilitated. It tends to be difficult to achieve, and 50μ
If it exceeds m, it tends to be difficult to accurately form a via hole in the insulating film 3 that serves as a conductive path for electrically connecting the circuit wiring films 2 formed above and below with the insulating film 3 interposed therebetween. Therefore, the range of 1 μm to 50 μm is good,
Suitable thickness is 2 to 10 μm, optimally 3 μm
It is preferable to set the thickness to 5 μm.

【0024】更に前記上面に多層配線部Aが被着された
絶縁基板1はその下面に外部リード端子5が配されてお
り、該外部リード端子5は絶縁基板1の下面に導出され
たメタライズ配線層4に超音波接合により接合されてい
る。
Further, the insulating substrate 1 having the multi-layer wiring portion A adhered on the upper surface has external lead terminals 5 arranged on the lower surface thereof, and the external lead terminals 5 are metallized wirings led to the lower surface of the insulating substrate 1. It is bonded to the layer 4 by ultrasonic bonding.

【0025】前記外部リード端子5は多層配線部Aに接
続される半導体素子6やコンデンサ7等の電子部品を他
の外部電気回路基板に接続する作用を為し、鉄ーニッケ
ルーコバルト合金や鉄ーニッケル合金、銅等の金属材料
で形成されており、例えば、鉄ーニッケルーコバルト合
金等のインゴット(塊)を圧延加工法や打ち抜き加工法
等、従来周知の金属加工を施すことによって所定の形状
に形成される。
The external lead terminals 5 have a function of connecting electronic components such as the semiconductor element 6 and the capacitor 7 connected to the multilayer wiring portion A to another external electric circuit board, and are made of iron-nickel-cobalt alloy or iron. -Metal material such as nickel alloy or copper. For example, ingot (lump) of iron-nickel-cobalt alloy is subjected to well-known metal processing such as rolling method or punching method to obtain a predetermined shape. Is formed.

【0026】また前記外部リード端子5の絶縁基板1下
面に導出するメタライズ配線層4への接合は超音波接合
によって、具体的には絶縁基板1の下面に導出するメタ
ライズ配線層4に外部リード端子5を当接させるととも
に外部リード端子5の上面より超音波発振ホーンを1.
5乃至6.5Kgf/mm2 の圧力で押圧しながら振動
数30乃至50KHz、振幅10乃至30μmの超音波
振動を0.01乃至0.2秒間印加し、メタライズ配線
層4と外部リード端子5との間に相互拡散による固相接
合を起こさせることによって行われる。
The external lead terminals 5 are bonded to the metallized wiring layer 4 extending to the lower surface of the insulating substrate 1 by ultrasonic bonding. Specifically, the external lead terminals are connected to the metallized wiring layer 4 extending to the lower surface of the insulating substrate 1. 5 is brought into contact with the external lead terminal 5 and the ultrasonic oscillating horn 1.
While pressing with a pressure of 5 to 6.5 Kgf / mm 2 , ultrasonic vibration having a frequency of 30 to 50 KHz and an amplitude of 10 to 30 μm was applied for 0.01 to 0.2 seconds to connect the metallized wiring layer 4 and the external lead terminals 5 to each other. It is carried out by causing solid-phase bonding by mutual diffusion between the two.

【0027】前記外部リード端子5のメタライズ配線層
4への取着はメタライズ配線層4と外部リード端子5の
相互拡散による固相接合であり、外部リード端子5とメ
タライズ配線層4の接合界面は両者の一体化物となって
いるためその接合強度は極めて強く、外部リード端子5
に外力が印加されても該外力よって外部リード端子5が
メタライズ配線層4より容易に剥離することはない。
The attachment of the external lead terminal 5 to the metallized wiring layer 4 is solid phase bonding by mutual diffusion of the metallized wiring layer 4 and the external lead terminal 5, and the bonding interface between the external lead terminal 5 and the metallized wiring layer 4 is Since the two are integrated, the bonding strength is extremely strong.
Even if an external force is applied to the external lead terminals 5, the external lead terminals 5 are not easily separated from the metallized wiring layer 4 by the external force.

【0028】更に前記外部リード端子5はメタライズ配
線層4に超音波接合よって接合されているため絶縁基板
1及び多層配線部Aに不要な高温の熱が印加されること
はなく、その結果、絶縁膜3が絶縁基板1より剥離した
り、絶縁膜3が溶融して特性に変化をきたすことは一切
なく、絶縁膜3を特性に変化をきたすことなく絶縁基板
1に強固に被着させ、回路配線膜2に接続される各電子
部品を外部リード端子5を介して他の外部電気回路基板
に確実、強固に電気的接続することができる。
Further, since the external lead terminals 5 are bonded to the metallized wiring layer 4 by ultrasonic bonding, unnecessary high temperature heat is not applied to the insulating substrate 1 and the multilayer wiring portion A, and as a result, insulation is achieved. The film 3 is not peeled off from the insulating substrate 1 or the insulating film 3 is melted so that the characteristics are not changed, and the insulating film 3 is firmly adhered to the insulating substrate 1 without changing the characteristics. Each electronic component connected to the wiring film 2 can be securely and firmly electrically connected to another external electric circuit board via the external lead terminal 5.

【0029】かくして上述の多層薄膜配線基板によれ
ば、絶縁基板1の上面に被着させた多層配線部Aの回路
配線膜2に半導体素子6やコンデンサ7等の電子部品を
半田を介して接続すれば半導体素子6やコンデンサ7等
の電子部品はその各々が回路配線膜2を介して電気的に
接続され、外部リード端子5を他の外部電気回路基板に
接続すれば半導体素子6やコンデンサ7等の電子部品は
外部リード端子5を介して外部電気回路基板に電気的に
接続される。
Thus, according to the above-mentioned multilayer thin-film wiring board, electronic components such as the semiconductor element 6 and the capacitor 7 are connected to the circuit wiring film 2 of the multilayer wiring portion A adhered to the upper surface of the insulating substrate 1 via solder. Then, the electronic components such as the semiconductor element 6 and the capacitor 7 are electrically connected to each other through the circuit wiring film 2, and if the external lead terminal 5 is connected to another external electric circuit board, the semiconductor element 6 and the capacitor 7 are connected. The electronic components such as are electrically connected to the external electric circuit board through the external lead terminals 5.

【0030】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば上述の実施例においてメ
タライズ配線層4の露出表面にニッケル層を1μm乃至
10μmの厚みに被着させておくとメタライズ配線層4
の酸化腐食が有効に防止されるとともにメタライズ配線
層4と回路配線膜2との接続及びメタライズ配線層4と
外部リード端子5との接合がより強固となる。従って、
前記メタライズ配線層4はその露出表面にニッケル層を
1μm乃至10μmの厚みに被着させておくことが好ま
しい。
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-described embodiments, the metallized wiring layer 4 can be formed. If a nickel layer having a thickness of 1 μm to 10 μm is deposited on the exposed surface, the metallized wiring layer 4
The oxidative corrosion is effectively prevented, and the connection between the metallized wiring layer 4 and the circuit wiring film 2 and the connection between the metallized wiring layer 4 and the external lead terminal 5 are strengthened. Therefore,
It is preferable that a nickel layer is deposited on the exposed surface of the metallized wiring layer 4 to a thickness of 1 μm to 10 μm.

【0031】また外部リード端子5の表面にニッケル、
金等の耐蝕性に優れ、且つロウ材と濡れ性の良い金属を
メッキ法により0.1μm乃至20μmの厚みに被着さ
せておくと外部リード端子5の酸化腐食を有効に防止す
ることができるとともに外部リード端子5と外部電気回
路基板との接続を良好となすことができる。従って、前
記外部リード端子5はその表面にニッケル、金等を0.
1μm乃至20μmの厚みに層着させておくことが好ま
しい。
Further, nickel on the surface of the external lead terminal 5,
It is possible to effectively prevent oxidative corrosion of the external lead terminals 5 by depositing a metal having excellent corrosion resistance such as gold and having good wettability with the brazing material to a thickness of 0.1 to 20 μm by a plating method. In addition, the connection between the external lead terminal 5 and the external electric circuit board can be made good. Therefore, the external lead terminal 5 has nickel, gold, etc. on its surface.
It is preferable to deposit them in a thickness of 1 μm to 20 μm.

【0032】更に上述の実施例ではメタライズ配線層4
に外部リード端子5を直接、超音波接合により接合させ
たが、メタライズ配線層4と外部リード端子5との間に
銀ー銅合金を配し、該銀ー銅合金にメタライズ配線層4
及び外部リード端子5の各々を超音波接合により接合さ
せることによってメタライズ配線層4に外部リード端子
5を取着させてよい。
Further, in the above embodiment, the metallized wiring layer 4
The external lead terminal 5 was directly bonded to the external ultrasonic wave by ultrasonic bonding. A silver-copper alloy was placed between the metallized wiring layer 4 and the external lead terminal 5, and the metallized wiring layer 4 was formed on the silver-copper alloy.
Alternatively, the external lead terminals 5 may be attached to the metallized wiring layer 4 by bonding each of the external lead terminals 5 by ultrasonic bonding.

【0033】[0033]

【発明の効果】本発明の多層薄膜配線基板によれば、回
路配線膜を薄膜形成技術より形成したことから回路配線
膜の微細化が可能で、回路配線膜の高密度化が達成でき
る。
According to the multilayer thin film wiring board of the present invention, since the circuit wiring film is formed by the thin film forming technique, the circuit wiring film can be miniaturized and the circuit wiring film can be made high in density.

【0034】また本発明の多層薄膜配線基板によれば、
絶縁基板に被着させたメタライズ配線層に外部リード端
子を超音波接合により接合させることから、外部リード
端子を取着する際に絶縁基板及び絶縁膜に不要な熱が印
加されることはなく、これによって絶縁膜は特性に変化
をきたすことなく絶縁基板に強固に被着し、回路配線膜
に接続される各電子部品を外部リード端子を介して他の
外部電気回路基板に確実、強固に電気的接続することが
できる。
According to the multilayer thin film wiring board of the present invention,
Since the external lead terminals are joined by ultrasonic bonding to the metallized wiring layer adhered to the insulating substrate, unnecessary heat is not applied to the insulating substrate and the insulating film when attaching the external lead terminals, As a result, the insulating film is firmly adhered to the insulating substrate without changing the characteristics, and each electronic component connected to the circuit wiring film is securely and firmly electrically connected to another external electric circuit board via the external lead terminals. Can be connected.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の多層薄膜配線基板の一実施例を示す断
面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a multilayer thin film wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・・絶縁基板 2・・・・・・回路配線膜 3・・・・・・絶縁膜 4・・・・・・メタライズ配線層 5・・・・・・外部リード端子 A・・・・・・多層配線部 1 ... Insulating substrate 2 ... Circuit wiring film 3 ... Insulating film 4 ... Metallized wiring layer 5 ... External lead terminal A. ... Multi-layer wiring

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】メタライズ配線層を有する絶縁基板上に薄
膜形成技術より有機高分子材料から成る絶縁膜と金属材
料から成る回路配線膜とを交互に多層に積層してなり、
前記メタライズ配線層に前記回路配線膜を電気的に接続
させるとともに、外部リード端子を超音波接合により接
合させたことを特徴とする多層薄膜配線基板。
1. An insulating substrate having a metallized wiring layer, wherein an insulating film made of an organic polymer material and a circuit wiring film made of a metal material are alternately laminated in multiple layers by a thin film forming technique.
A multilayer thin-film wiring board, characterized in that the circuit wiring film is electrically connected to the metallized wiring layer and external lead terminals are bonded by ultrasonic bonding.
JP7140502A 1995-06-07 1995-06-07 Multilayer thin film wiring board Pending JPH08335777A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7140502A JPH08335777A (en) 1995-06-07 1995-06-07 Multilayer thin film wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7140502A JPH08335777A (en) 1995-06-07 1995-06-07 Multilayer thin film wiring board

Publications (1)

Publication Number Publication Date
JPH08335777A true JPH08335777A (en) 1996-12-17

Family

ID=15270138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7140502A Pending JPH08335777A (en) 1995-06-07 1995-06-07 Multilayer thin film wiring board

Country Status (1)

Country Link
JP (1) JPH08335777A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003871A (en) * 2008-06-20 2010-01-07 Kyocera Corp Wiring substrate, probe card, and electronic device
JP2011210828A (en) * 2010-03-29 2011-10-20 Tdk Corp Substrate for forming thin-film circuit, thin-film circuit component, and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003871A (en) * 2008-06-20 2010-01-07 Kyocera Corp Wiring substrate, probe card, and electronic device
JP2011210828A (en) * 2010-03-29 2011-10-20 Tdk Corp Substrate for forming thin-film circuit, thin-film circuit component, and method of manufacturing the same

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