JPH08331084A - Synchronization multiplexer - Google Patents

Abstract

PURPOSE: To provide the synchronization multiplexer in which data subject to time division multiplex are correctly outputted even when a deviation is caused in received data. CONSTITUTION: The multiplexer is provided with packet out of synchronism detection circuits 103a-103c detecting packet out of synchronism based on data, clock and packet head pulse received from input terminals 109, 111, 113 corresponding to channels A-C respectively. When packet out of synchronism is detected, a signal stopping read from an FIFO(fast in fast out) memory 105 and write to an FIFO memory is outputted to an FIFO write control block 101 and a read control block 107 of a corresponding channel. Simultaneously the corresponding FIFO memory 105 is reset, out of synchronism is cleared and when data sufficient to read the FIFO memory are written, the read is attained again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a synchronous multiplexer,
In particular, the present invention relates to a synchronous multiplexing device that performs time division multiplexing of data input from a plurality of channels.

[0002]

2. Description of the Related Art Continuous digital data divided into blocks of a fixed length (hereinafter referred to as "packets") are input from a plurality of channels, and the input packets of each channel are regularly time-division multiplexed. (TDM (Time D
ivision Multiplex) is also known in the past. The method of multiplexing performed in the synchronous multiplexer is the synchronous multiplexing (STM (Synchronous Transf
er Mode) also called) method.

In the synchronous multiplexer, the transfer rate of data input from each channel is the same in all channels, but the start position of the packet of data input from each channel is irregular for each channel. Therefore, inside the device, processing for aligning the heads of packets of data input from the respective channels is performed.
A FIFO (first-in, first-out) memory, which is a memory for temporarily storing data input to perform this process, is used.

FIG. 9 is a block diagram showing a concrete structure of a synchronous multiplexer for performing time division multiplexing of data input from channels A to C.

Referring to the figure, the synchronous multiplexing apparatus includes FIFO write control blocks 101a to 101c for controlling writing of data input from channels A to C into a FIFO memory, and A to C. FIFO memories 105a to 105c corresponding to the channels of
A read control block 107 for performing read control from the FIFO memories 105a to 105c.

The FIFO write control block 101a corresponding to the A channel has a data input terminal 109a for inputting the A channel data and a clock input terminal 11 for inputting a clock signal accompanying the data.
1a and a packet head pulse input terminal 113a for inputting a packet head pulse which is a pulse indicating the head position of the packet. Similarly, FIFO write control blocks 101b and 101 corresponding to the B and C channels, respectively.
Data input terminals 109b and 109c, clock input terminals 111b and 111c, and packet head pulse input terminals 113b and 113c for inputting the signals of the respective channels are also provided for each of c. The multiplexed data is output to the outside via a multiplexed data output terminal 115 provided in the read control block 107.

FIG. 10 shows the A to C channel FIFO of FIG.
FIG. 9 is a circuit diagram showing a mechanism for generating a read start pulse included in each of the write control blocks 101a to 101c.

Referring to the figure, each of the FIFO write control blocks 101a to 101c has FIFO write data counters 401a to 401c for counting the number of data written in the FIFO memories 105a to 105c of the corresponding channels, and an OR gate. 403a-40
3c and are included. One input terminal of the OR gate 403c included in the C channel FIFO write control block 101c is connected to the C channel FIFO write data counter 401c, and the other input terminal of the OR gate 403c is grounded. One input terminal of the OR gate 403b included in the B channel FIFO write control block 101b is connected to the B channel FIFO write data counter 401b, and the other input terminal is the output of the OR gate 403c included in the A channel FIFO write control block 101a. Connected to the terminal. One input terminal of the OR gate 403a included in the A channel FIFO write control block 101a is connected to the A channel FIFO write data counter 401a,
The other input terminal is connected to the output terminal of the OR gate 403b included in the B channel FIFO write control block 101b. Thereby, the OR gates 403a-40
3c are cascaded, A to C channel FIFO
When any of the write data counters 401a to 401c outputs a "High" level signal, a read start pulse which is a "High" level signal is output from the output terminal of the OR gate 403a.

FIG. 11 shows the read control block 10 of FIG.
7 is a block diagram showing a specific configuration of No. 7.

Referring to the figure, the read control block 107
Is an A to C channel read position pulse generator 201a to 201c for generating a pulse for reading the data of each channel of A to C stored in each of the FIFO memories 105a to 105c, and a read position pulse generator 201a to 201c. A switch 205 for selecting one of the FIFO memories 105a to 105c for reading in response to the pulse signal from 201c. The read start pulse input via the read start pulse input terminal 213 is input to the A to C channel read position pulse generators 201a to 201c. The read data from the A to C channel FIFO memories input through the read data input terminals 211a to 211c are input to the switch 205. Switch 20
The read data selected by 5 is output as multiplexed data via the multiplexed data output terminal 115. Also A
-C channel read position pulse generator 201a-2
01c are read clock output terminals 207a-2
A read clock, which is a clock for reading data from the FIFO memory, is output via 07c.

Next, the operation of time division multiplexing in the conventional synchronous multiplexer will be described with reference to FIGS. 9 to 11.

A data input terminal 1 is provided in each of the A to C channel FIFO write control blocks 101a to 101c.
09a to 109c, data of respective channels, clock input terminals 111a to 111c, clock signals of respective channels, and packet head pulse input terminals 113a to 113c. Here, as shown in FIG.
The data in each channel is data composed of continuous digital data having a header part and a data part. As shown in FIG. 14, the data has a header part of 5 bytes and a data part of 45 bytes, for a total of 50.
One byte is a set, and one set composed of 50 bytes of data is called a packet. The clock signal input from the clock input terminals 111a to 111c is a clock associated with the input data (a), as shown in FIG.
The cycle corresponds to the time when 1 byte of data is transmitted. Further, as shown in FIG. 12C, the packet head pulse is a pulse that is generated when the head 1-byte data of the header portion of the input data (a) is transmitted.

The FIFO write control blocks 101a to 101c of the respective channels perform write control of the input data to the FIFO memory based on the input data, clock and packet head pulse. FI
The FIFO write control blocks 101a to 101c of the respective channels are used to control writing to the FO memory.
Outputs a write clock for writing data, write data for writing, and a reset signal for resetting the FIFO memory to each of the corresponding FIFO memories 105a to 105c. Here, the write clock is a clock signal indicating the write timing to the FIFO memory, and is a clock corresponding to the clock input from the clock input terminal 111. The write data is digital data input through the data input terminal 109. What is a reset signal?
It is a signal for resetting the contents of the FO memory 105, and is a signal output when the device is started. FIFO
The data written in the memories 105a to 105c is FI.
The data is temporarily stored in the FO memory, read by the read control by the read control block 107, and the read data is output via the multiplex data output terminal 115.

The read control by the read control block 107 is performed according to the following procedure. When the device is activated, the reset signal causes the FIFO memory 105a.
Since the contents of each of to 105c are cleared, read control is not performed. The read control is started as follows. That is, as shown in FIG. 10, the FIFO write control block 101 of each channel is
The a to 101c count the number of data input via the data input terminals 109a to 109c by the FIFO write data counters 401a to 401c. The write data counter outputs a "High" level signal to the OR gates 403a to 403c when the written data becomes 100 bytes corresponding to the data of two packets. As a result, one of the FIFO memories 105a ...
When the data written in 105c becomes 2 packets, the read start pulse is read control block 1
It will be output to 07.

In the read control block 107, as shown in FIG. 11, a read start pulse input terminal 21
The read start pulse inputted through 3 is A to C.
Channel read position pulse generators 201a-201
input to each of c. At this time, as shown in the timing chart of FIG. 13, based on the read start pulse (a), the read position pulse generators 201a to 201c of the respective channels read the read position pulse (b) having a time difference with respect to each of them. ) To (d) are output. The pulse width of this read position pulse has a length for reading one packet of data, and corresponds to 50 clocks of the read clock. The switch 205 switches the channel from which data is read in response to the read position pulse of each channel, and the data read via the switch 205 is output as multiplexed data. The multiplexed data output as shown in FIG. 13E corresponds to the data of the channel in which the read position pulse is at the “High” level, and the read start pulse (a) is at the head, and A → B → C → A → B → C ...
... and A, B, and C channels are sequentially output. It should be noted that one segment of data shown in (e) has a length of one packet.

Further, referring to FIG. 15, the transfer rate of the data input from each of the channels A to C is α [bit / sec].
If so, the clock is controlled so that the transfer rate of the multiplexed data output from the multiplexer is 3 × α [bit / sec]. This prevents overflow of data stored in the FIFO memory and loss of data stored in the FIFO memory.

[0017]

However, the above-mentioned conventional synchronous multiplexing apparatus has a problem that correct time division multiplexing cannot be performed when a deviation occurs in input data. The reason for this is as follows. For example, with a conventional synchronous multiplexer,
It is assumed that video digital data in which video data from a plurality of channels are combined is multiplexed and transmitted on one transmission path. In the terminal on the receiving side, data of an arbitrary channel among the multiplexed data of a plurality of channels is separated and used as video data (such a system is called video on demand (VOD)). The video data multiplexed and transmitted from each of the channels in the video-on-demand system is requested by the user. Therefore, the video data service is provided according to the timing of the request made by the user. Therefore, when the service changes, the head position of the packet is displaced. At this time, the conventional synchronous multiplexer cannot cope with the shift of the packet start position, and only the channel in which the shift occurs causes the packet start position to be shifted and multiplexing is performed.

More specifically, as shown in FIG. 16, when the data of channels A to C are input to the synchronous multiplexer, the data of channel B is shifted, and the data of B-1 and B- Even if there is a gap between the two data, the synchronous multiplexer reads the FIFO memory based on the signal of the read position pulse generated based on the timing of the read start pulse as shown in FIG. In the output data 501, a shift occurs in the data portion of the B channel.
In this way, when the packets are multiplexed with the head of the packet shifted and the transmission is performed, even if the receiving terminal separates the channels and takes out the data, the data position in the packet shifts on the channel where the synchronization shift occurs, so the correct data Cannot play back.

The present invention has been made to solve the above problems, and provides a synchronous multiplexing apparatus capable of correctly outputting time-division-multiplexed data even if input data is deviated. The purpose is to do.

[0020]

A synchronous multiplexer according to claim 1 is a synchronous multiplexer for performing time division multiplexing of data input from two or more channels, and at least one of the two or more channels. A discriminating means for discriminating the deviation of the data inputted from one channel, and an output means for outputting after correcting the multiplexing timing of the data inputted from the channel in which the data discrepancy has occurred based on the discrimination output of the discriminating means. Be prepared.

A synchronous multiplexer according to a second aspect of the present invention is the synchronous multiplexer according to the first aspect, wherein the output means inputs from a channel in which a data shift has occurred based on the discrimination output of the discrimination means. A correction unit that corrects data and a storage unit that stores the corrected data are provided, and the stored data is output.

According to a third aspect of the present invention, there is provided the synchronous multiplex apparatus according to the second aspect, wherein the output means has a deviation of the data stored in the storage means based on the discrimination output of the discrimination means. The reading means for reading the data of the channel is further provided to output the read data.

The synchronous multiplexer according to claim 4 is the synchronous multiplexer according to claim 1, wherein the output means further comprises storage means for storing data input from each of the two or more channels. The read data is output by including read means for reading the data of the channel in which the deviation of the data stored in the storage means has occurred based on the judgment output of the judgment means.

[0024]

A synchronous multiplexer according to claim 1 discriminates a deviation of data input from at least one channel of two or more channels, and inputs from a channel in which a data deviation occurs based on the discrimination output. The data is output after correcting the timing of multiplexing the data.

According to a second aspect of the present invention, in addition to the function of the first aspect of the synchronous multiplexer, the data input from the channel in which the data shift occurs is corrected based on the discrimination output. The stored data is stored, and the stored data is output.

According to a third aspect of the present invention, in addition to the operation of the second aspect, the synchronous multiplexer reads out and reads out the data of the channel in which the deviation of the stored data occurs based on the discrimination output. The output data.

In addition to the function of the synchronous multiplexer described in claim 1, the synchronous multiplexer described in claim 4 stores data inputted from each of the channels, and stores the data based on a discriminated output of the data shift. The data of the channel in which the deviation of the read data has occurred is read, and the read data is output.

[0028]

An embodiment of the present invention will be described below with reference to the accompanying drawings. The synchronous multiplexer of the present invention is characterized in that a packet synchronization deviation detection circuit (discrimination circuit) for detecting a packet synchronization deviation (data deviation) is provided for each of the channels to which data is input. When it occurs, the data of the channel in which the synchronization shift has occurred is stored in and read from the FIFO memory based on the signal output from the packet synchronization shift detection circuit. More specifically, the packet synchronization deviation detection circuit resets the FIFO memory when the packet synchronization deviation is detected, and F
Writing to the IFO memory is stopped, and reading from the FIFO memory is stopped until two packets of data are written to the FIFO memory after the packet synchronization shift is resolved.

FIG. 1 is a block diagram showing a device configuration of a synchronous multiplexing device in one embodiment of the present invention which performs the above-mentioned operation.

Referring to the figure, the synchronous multiplexer inputs the data of each channel A to C, the clock and the packet head pulse, and shows the reset control signal for controlling the reset of the FIFO memory and the writeability to the FIFO memory. FIFO write enable signal, which is a signal, and F, which is a signal indicating readability from the FIFO memory
Packet synchronization deviation detection circuit 103 corresponding to each of the channels A to C outputting the IFO read enable signal
a to 103c. In addition, the FIFO memories 105a to 105c corresponding to the respective channels and the respective FIFOs
FIFO write control blocks 101a to 101c for controlling the O memories 105a to 105c, and a read control block 107 for controlling reading from the FIFO memory.
Is provided in the same manner as in the conventional synchronous multiplexing apparatus shown in FIG.

However, the read control block 107 includes the packet synchronization shift detection circuits 103a to 103a for the respective channels.
Since the read control from the FIFO memory is performed based on the FIFO read enable signal from 03c, the specific configuration thereof is different from the read control block in the conventional synchronous multiplexer.

FIG. 2 shows the read control block 107 of FIG.
It is a figure showing the concrete composition of. Referring to the figure, the read control block 107 includes A to C channel read pulse generators 203a to 203c for generating read pulses corresponding to respective channels. A to C channel read position pulse generator 201 for generating read position pulse corresponding to each channel
a-201c and a switch 205 for selecting the FIFO memory to be read are provided.
This is similar to the conventional read control block shown in FIG. Readout pulse generator 203 for each channel
a to 203c are read position pulses from the read position pulse generators 201a to 201c of respective channels and FIFO read enable signal input terminals 209a to 209a.
The read pulse is generated based on the FIFO read enable signal corresponding to each channel input via each of the channels 209c. The generated pulse is input to the switch 205.

FIG. 3 is a circuit diagram showing one specific configuration of the A to C channel read pulse generators 203a to 203c of FIG.

Referring to the drawing, the read pulse generator is a D flip-flop 301 forming a latch, AND gates 305a and 305b, an inverter 303, and a read position pulse input terminal 3 for inputting a read position pulse.
07 and FI that inputs the FIFO read enable signal
An FO read enable signal input terminal 309 and a read pulse output terminal 311 for generating a read pulse are provided. The read position pulse input terminal 307 is connected to the input terminal D of the D flip-flop 301 and one input terminal of the AND gate 305a. The FIFO read enable signal input terminal 309 is connected to the input terminal of the inverter 303 and one input terminal of the AND gate 305b.
The output terminal of the inverter 303 is the D flip-flop 30.
1 is connected to the input terminal ENA (clock input terminal). The output terminal Q of the D flip-flop 301 is connected to the other input terminal of the AND gate 305a. The output terminal of the AND gate 305a is connected to the other input terminal of the AND gate 305b. The output terminal of the AND gate 305b is connected to the read pulse output terminal 311.

The operation of the synchronous multiplexer in this embodiment shown in FIGS. 1 to 3 will be described below.

Packet synchronization deviation detection circuits 103a to 103c provided corresponding to the respective channels detect the packet synchronization deviations generated in the respective channels. The method of detecting packet synchronization deviation is as follows. That is, one packet of data (a) input with reference to FIG. 4 is composed of a header part and a data part, and its size is 50 bytes. The clock signal input as shown in (b) has a period corresponding to the time for which one byte of data is input. The packet head pulse (c) is a pulse output corresponding to the head of one packet (first data of the header part). Therefore, the packets of the input data are continuous when the packet synchronization is established, and the packet head pulse (c) is set to 1
The count number of clocks in the cycle is always 50 (time t1). However, when a gap (gap) occurs between the packets due to the data shift, the count value of the clock between the packet head pulse and the packet head pulse is 50 in the portion where the shift occurs.
Is different from (at time t2). In this way, when the clock count value between the packet head pulses becomes different from 50, the packet synchronization deviation detection circuit determines that there is a synchronization deviation. After it is determined that the synchronization is deviated, it is determined that the synchronization has been established when the clock count number between the packet head pulses becomes 50 again.

When it is determined that there is a synchronization deviation, the packet synchronization deviation detection circuit, as shown at time t4 in FIG. 6, outputs "Low" level as each signal of the inverted FIFO reset pulse, the FIFO write enable signal, and the FIFO read enable signal. The signal of is output. When a packet synchronization shift is detected by this operation, the contents of the FIFO memory of the channel are reset, and both reading and writing of the FIFO memory are prohibited. Further, the packet synchronization deviation detection circuit determines that the packet synchronization is established (t in FIG. 6).
5) Set each of the inverted FIFO reset pulse and the FIFO write enable signal to “High” level, and
Release the reset state and write-protected state of the IFO memory. At the time point (time t6) when two packets of data are input to the FIFO memory after the write-protection state of the FIFO memory is released, the packet synchronization deviation detection circuit sets the FIFO read enable signal to “High”.
The read control block 107 releases the read prohibition state of the FIFO memory of the channel. As a result, at time t6, reading of data from the sixth packet stored in the FIFO memory is restarted.

A specific example of the multiplexed data output from the read control block 107 will be described with reference to the timing chart shown in FIG. As shown in (d), the multiplexed data is basically output in the order of A → B → C → A → B → C .... By the way, the time (t1, t2, ..., T5) at which the A channel data is output in the multiplexed data is determined by the read position pulse (a) generated by the A channel read position pulse generator as in the prior art. . However, as shown in (b), for example, the FIFO in the read position pulse at times t2 and t3
If the read enable signal (b) is at "Low" level, the pulse (c) output from the A-channel read pulse generator will be output while the FIFO read enable signal (b) is at "Low" level. It is always at "Low" level. As a result, the read pulse is not generated at the times t2 and t3, so that the data of the A channel at the times t2 and t3 becomes blank reading (blank) data. Further, at time t4, the FIF
When the O read enable signal becomes "High" level, the reading from the A channel FIFO memory is restarted. In this way, the FIFO enable signal is "Low".
While the level is set, the reading of the data on the channel is stopped and blank data is output as multiplexed data, but the data on the channel output after synchronization is established eliminates the synchronization shift. As a result, the time-division multiplexed data can be correctly output.

Further, as shown in FIG. 8, at time t3, the read position pulse (a) of the A channel is "High".
When the read enable signal (b) becomes the "Low" level while it is at the "h" level, the A channel read pulse (c) output from the A channel read pulse generator is read even during the reading of the FIFO memory. As shown in (d), the blank data of the blank reading is output from the time t3 as shown in (d), while the high position of the read position pulse of the A channel is shown at time t5. When the A channel read enable signal becomes "High" level as shown in (b) while it is at "Level",
No read pulse is output as shown in (c),
At that time, no data is read from the FIFO memory.

As shown in FIG. 5, when the synchronization is established at the beginning of the first packet and the read enable signal becomes "High" level at time t2 when the data of two packets are read, the synchronization is lost thereafter. Each of the inverted FIFO reset pulse, the FIFO write enable signal, and the FIFO read enable signal keeps the “High” level until the packet synchronization shift detection circuit detects the multiplexed data input from the respective channels A to C. It will be output.

In the present embodiment, the packet synchronization deviation detection circuit detects the synchronization deviation by detecting the interval between the packet head pulses. However, for example, the header section included in the data is detected to detect the header section. The synchronization shift may be detected by detecting the distance from the header section.

Further, in the present embodiment, the writing control and the reading control to the FIFO memory are performed based on the packet synchronization deviation detected by the packet synchronization deviation detection circuit, but the writing is performed based on the packet synchronization deviation detection. Either control or read control may be performed. For example, when only read control is performed, data is always written in the FIFO memory regardless of whether or not a synchronization shift occurs.
When the synchronization shift occurs, the data is not read from the FIFO memory, and when the synchronization shift is resolved, the F
It is possible to read the data from the IFO memory in consideration of the synchronization deviation interval.

[0043]

According to the first aspect of the present invention, the synchronous multiplexer determines the deviation of the data input from at least one of the two or more channels, and based on the result of the judgment, the channel in which the data deviation occurs. Since the output is performed after correcting the multiplexing timing of the data input from, the time-division multiplexed data can be correctly output even if the input data is misaligned. Further, even if the packet synchronization is deviated in any channel, it does not affect other channels.

In addition to the effect of the synchronous multiplexer according to the first aspect, the synchronous multiplexer according to the second aspect stores the data after correcting the data input from the channel in which the data shift occurs based on the determination result. However, since the stored data is output, the data can be corrected more efficiently.

In addition to the effect of the synchronous multiplex device according to the second aspect, the synchronous multiplex device according to the third aspect reads out and outputs the data of the channel in which the deviation of the data stored based on the determination result occurs. Further, it is possible to more efficiently correct the data input from the channel in which the shift has occurred.

In addition to the effect of the synchronous multiplexer according to claim 1, the synchronous multiplexer according to claim 4 stores data inputted from each of two or more channels, and the data is stored based on the determination result. Since the data of the channel in which the data shift has occurred is read, the efficiency of data correction can be further improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a synchronous multiplexer according to an embodiment of the present invention.

2 is a block diagram showing a specific configuration of a read control block 107 in FIG.

FIG. 3 is a channel read pulse generator 203 of FIG.
It is a circuit diagram showing one concrete composition of a-203c.

4 is a diagram illustrating packet synchronization deviation detection circuits 103a to 103 of FIG.
FIG. 13 is a diagram for explaining a packet synchronization deviation determination process performed by one of the routers 03c.

5 is a diagram illustrating packet synchronization deviation detection circuits 103a to 103 of FIG.
It is a figure for demonstrating the signal which one of 03c outputs.

6 is a diagram showing packet synchronization deviation detection circuits 103a to 103 of FIG.
FIG. 3 is a diagram for explaining a signal output from one of the packet 03c, and is a diagram illustrating an output signal when a packet synchronization deviation occurs.

FIG. 7 is a first diagram for explaining a signal for reading A channel data and a multiplexed signal output by the signal.

FIG. 8 is a second diagram showing a signal for reading A channel data and a multiplexed signal output by the signal.

FIG. 9 is a block diagram showing a specific configuration of a conventional synchronous multiplexer.

FIG. 10 is a diagram for explaining a circuit for outputting a read start pulse.

11 is a block diagram showing a specific configuration of a read control block 107 in FIG.

FIG. 12 is a FIFO write control block 101 of FIG.
It is a figure which shows the specific example of the data input into one of a-101c, a clock, and a packet head pulse.

FIG. 13 is a diagram showing a read position pulse output based on a read start pulse and multiplexed data output based on the read position pulse.

FIG. 14 is a diagram for explaining one packet of input data.

FIG. 15 is a diagram for explaining data input to each of channels A to C and multiplexed data by the synchronous multiplexer.

FIG. 16 is a diagram showing a multiplexed signal when a shift occurs in input data, and is a diagram showing a problem of the conventional technique.

[Explanation of symbols]

 101 FIFO write control block 103 Packet synchronization deviation detection circuit (discrimination circuit) 105 FIFO memory (storage circuit) 107 Read control block 109 Data input terminal 111 Clock input terminal 113 Packet head pulse input terminal 115 Multiple data output terminal 201 Read position pulse generation Device 203 Read pulse generator 205 Switch 207 Read clock output terminal 209 FIFO read enable signal input terminal 211 Read data input terminal 213 Read start pulse input terminal 301 D flip-flop 303 Inverter 305 AND gate 307 Read position pulse input terminal 309 FIFO read enable Signal input terminal 311 Read pulse output terminal 401 FIFO write counter 403 O Gate

Claims (4)

[Claims] 1. A synchronous multiplexing device for performing time division multiplexing of data input from two or more channels, wherein a discriminating means for discriminating deviation of data input from at least one of the two or more channels. And a outputting unit for outputting after correcting the multiplexing timing of the data input from the channel in which the data shift has occurred, based on the discrimination output of the discriminating unit. 2. The output means corrects the data input from the channel in which the data shift occurs based on the determination output of the determination means, and the storage means stores the corrected data. The synchronous multiplexer according to claim 1, further comprising: outputting the stored data. 3. The read means further comprises a read means for reading the data of the channel in which the deviation of the data stored in the storage means has occurred, based on the determination output of the determination means, and the read data. The synchronous multiplexer according to claim 2, which outputs 4. The output means further comprises a storage means for storing data input from each of the two or more channels, and the data stored in the storage means based on a determination output of the determination means. 2. The synchronous multiplexing device according to claim 1, further comprising: a reading unit that reads out the data of the channel in which the shift has occurred, and outputs the read data.