JPH08330952A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE: To set an arbitrary damping factor without using of damping resistors. CONSTITUTION: This circuit consists or a variable oscillator 12, a phase comparator 16 which compares phases of the variable oscillation output of this oscillator 12 and a reference signal with each other, a charge pump circuit 18 which converts the phase comparison output into a corresponding control signal, a differentiator 40 which differentiates this control signal, and an adder 42 which adds the control signal to the differential signal, and the oscillation frequency of the variable oscillator 12 is controlled by the addition signal. The damping factor of a PLL system can be set by the gain of the differentiator 40 and the cut-off frequency. Thus, the dynamic range of the system is made narrow to not only reduce the power consumption but also make the circuit into an IC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit adapted to obtain an oscillating output phase-locked with an input signal, and more particularly to a differential signal added to a control signal corresponding to a phase comparison output. By using a thing as a control signal of a variable oscillator, it is possible to set an appropriate damping factor without using a damping resistor.

[0002]

2. Description of the Related Art Various electronic devices are required to internally generate a signal phase-locked with an input signal. For example, when a clock is extracted from transmission data, a phase locked loop circuit as a phase synchronization circuit, a so-called PLL circuit is used. This PLL circuit is often used when an internal reference signal whose phase and frequency are synchronized with an external reference signal is generated. There are various types of PLL circuits, such as digital type and analog type, and various types of phase comparator configuration methods are possible.
There is a circuit.

FIG. 11 shows a conventional example of a PLL circuit 10 adopting a digital system for a phase comparator used in such a circuit system.

In this example, the variable oscillator 12 is a voltage-controlled variable oscillator VCO (Voltage Controlled Oscillato).
r) is illustrated. A reference signal is supplied to the terminal 14.
The reference signal may be a periodic signal such as a clock or an aperiodic signal such as data.

The oscillation output (binarized clock) of the VCO 12 is supplied to the phase comparator 1 together with the reference signal (reference clock).
6 is input. The phase comparator 16 outputs a signal corresponding to the phase difference between the two input clock signals. In this example, as shown in FIGS. 12A and 12B, a pulse corresponding to the time difference of the rising edge of the reference signal with respect to the oscillation output is output as a down signal (FIG. 12C), and the pulse corresponding to the time difference of the rising edge of the oscillation output with respect to the reference signal is output. The pulse is output as an up signal (D in the same figure). The down signal lowers the oscillation frequency, and the up signal raises the oscillation frequency.
It is added to the control terminal of O12. If the positions of both edges to be compared are the same, both the up signal and the down signal are zero outputs and the VCO 12 continues to oscillate at a constant frequency.

Since both the up signal and the down signal are pulse signals as shown in FIG. 12, the VCO1 is left as it is.
2 cannot be directly added as a control signal. Normally, it is converted into voltage. The charge pump circuit 18 is used as a conversion circuit therefor.

FIG. 13 is a conceptual diagram of the charge pump circuit 18, which has a capacitor 22 for voltage integration. In the charge mode, the switch 2 is connected to the capacitor 22.
4 and the constant current source 26 are connected in series, and the constant current source 28 and the switch 30 are connected in series in the discharge mode. The switch 24 is closed by the up signal and the constant current I
The capacitor 22 is charged by p, the switch 30 is closed by the down signal, and it is decharged by the constant current In. As a result, when the up signal and the down signal are as shown in FIGS. 14B and C, the output voltage of the charge pump circuit 18 (the voltage across the capacitor 22) becomes the output voltage (frequency control voltage) as shown in FIG. 14A. 18a.

If the oscillation frequency change of the VCO 12 is sufficiently lower than the frequency of the reference signal, the transfer function of the oscillation output phase of the VCO 12 with respect to the phase of the reference signal can be obtained by performing appropriate approximation. The phase of the reference signal is expressed as θi (s) using the Laplace operator s, and the VCO oscillation output phase is expressed as θi (s) using the Laplace operator.
When expressed as o (s), the transfer function H (s) of the entire PLL circuit 10 is H (s) = θo (s) / θi (s) = ωn ² / (s ² + ωn ² ) (1 ) From the sensitivity Kv of the VCO 12, the charge pump current Ip, and the capacitance C of the integrating capacitor 22, the natural angular frequency ωn of the VCO 12 is expressed by the equation (2).

[0009]

[Equation 1]

When the step response is obtained from the transfer function H (s), it is found that the phase oscillates in a sine wave shape, and the control voltage applied to the VCO 12 changes in a sine wave shape at the angular frequency ωn (FIG. 15B). Therefore, the frequency of the VCO 12 also changes sinusoidally (FIG. 15C), and its value V (t) is as follows.

V (t) = A sin (ωn t + θ) (A and θ are arbitrary constants) (3) In this way, the voltage just integrated by the capacitor 22 is VC.
The PLL circuit 10 is used as the control voltage for O12.
Since the damping factor ζ of 0 is zero, the control voltage repeatedly oscillates as shown in FIG. 15, and the feedback system of the PLL circuit 10 becomes unstable. Incidentally, when the phase difference between the up and down signals shown in FIG. 15A is zero, the deviation of the oscillation frequency is maximum, and when the difference between the oscillation frequencies is zero, the phase difference of the up and down signals is maximum.

From the viewpoint of suppressing the oscillation of the control voltage to ensure the stability of the feedback system and removing the unnecessary high frequency component having a high frequency component contained in the feedback oscillation output, a loop as shown in FIG. The filter 32 is provided between the charge pump circuit 18 and the VCO 12.

In the configuration of FIG. 16, the transfer function H (s) becomes a system of the third order or higher, and it is difficult to set the constant of the PLL circuit 10. Therefore, normally, as shown in FIG. 17, a resistor 34 is inserted in series with the charge pump capacitor 22 to form a loop filter. This resistor 34 functions as a damping resistor. This transfer function is quadratic and is expressed by equation (4).

H (s) = (2ζ · ωn · s + ωn ² ) / (s ² + 2ζωn + ωn ² ) (4) Here, the sensitivity Kv of the VCO 12 and the charge pump current I
p, the capacitance C of the integrating capacitor 22, the damping resistance Rd
Then, ωn and ζ can be expressed as in equations (5) and (6).

[0015]

[Equation 2]

[0016]

(Equation 3)

The desired damping factor ζ can be easily obtained by selecting the damping resistance Rd after determining the angular frequency ωn. Usually set to 0.7.

[0018]

By the way, as shown in FIG. 17, the damping resistor 3 is connected in series with the integrating capacitor 22.
When 4 is connected, a pulse-like voltage drop (= IpRd, InRd) as shown in FIG. 18B is generated across the damping resistor 34 due to the currents Ip and In (= Icp) flowing when the capacitor C is charged and discharged. To do. As a result, a pulse voltage is superimposed on the control voltage (FIG. 18A) at the output terminal 18a of the capacitor 22 (FIG. 18C).

If this pulsed voltage is too large, the VCO
The value may be out of the oscillating frequency range of 12 and normal feedback may not be applied, or the VCO 12 may be damaged and destroyed depending on the type of the VCO 12.

Further, since this pulse-like voltage change is fast, it may not be possible to respond to this voltage change depending on the type of the VCO 12, and then normal feedback will not be applied.

Since the value of the voltage drop (Icp · Rd) is larger than the terminal voltage of the capacitor 22, the dynamic range of the PLL circuit 10 is set to the damping resistor 34 in order to process this pulsed voltage without distortion. It is required to be several times as large as that of the PLL circuit which does not use the capacitor 22 and has only the capacitor 22.

This pulse voltage may be attenuated by connecting a capacitor 36 in parallel with a series circuit of a capacitor 22 and a damping resistor 34 as shown in FIG. 19, but this time the PLL circuit 10 will be attenuated. Since it is a cubic transfer function, problems such as difficulty in constant design occur.

Therefore, the present invention solves such a conventional problem, and proposes a phase locked loop circuit capable of arbitrarily determining a damping factor without using a damping resistor.

[0024]

SUMMARY OF THE INVENTION In a phase locked loop circuit according to the present invention as set forth in claim 1, a variable oscillator, a phase comparator for performing a phase comparison between the variable oscillation output and a reference signal, and a phase A conversion circuit for converting the control signal according to the comparison output, a differentiator for differentiating the control signal, and a signal obtained by adding the control signal to the differential signal to control the oscillation frequency of the variable oscillator. Is characterized by.

[0025]

When the VCO is controlled by adding the differential output to the control signal, the damping effect can be provided without using the damping resistor, and the damping factor ζ at that time is the gain of the differentiator or the differential time constant. Since it is a function, the damping factor ζ can be determined by these values.

Since no damping resistor is used, the amount of pulsed voltage superimposed on the integrating capacitor is reduced, and the dynamic range of the entire circuit can be reduced accordingly. If the dynamic range can be narrowed, the power supply voltage of the PLL circuit can be lowered, and depending on the circuit configuration, it can be incorporated in the IC.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a case where an example of the phase locked loop circuit according to the present invention is applied to the above digital PLL circuit will be described in detail with reference to the drawings.

An example of the phase locked loop circuit (PLL circuit) according to the present invention is shown in FIG. Also in the present invention, basically the same circuit configuration as the conventional example is followed. Therefore, as shown in FIG.
12, a phase comparator 16 for phase comparison between a reference signal and an oscillation output, and a charge pump circuit 18 functioning as a conversion circuit for converting the phase comparison output into a control voltage are provided, and the output from the charge pump circuit 18 is provided. (Voltage across the capacitor) is used as a control voltage for the VCO 12. The reference signal supplied to the terminal 14 may be a periodic signal or data.

In contrast to such a configuration, the present invention further includes a differentiator 40 and an adder 42 at the subsequent stage of the charge pump circuit 18, and the added output of the differential output and the control voltage is supplied to the VCO 12 as a new control voltage. Added. Only the integrating capacitor 22 is connected to the charge pump circuit 18, and the conventional damping resistor 34 is not used.

In the circuit configuration described above, when the impedance of the integrating capacitor 22 provided in the charge pump circuit 18 is ZF (s) (s is the Laplace operator), a quantity similar to the charge pump output voltage is , Ip · ZF (s) (7a) when the charge pump current is Ip. The reason why this value is similar to the output voltage of the charge pump is that the charge pump current Ip is always the capacitor 2
This is because it does not flow to 2. When the impedance is only the capacitor 22, ZF (s) = 1 / sC (7b) ∴Ip · ZF (s) = Ip / sC (8) In series with the capacitor 22 When there is a damping resistor Rd, an amount similar to the charge pump output voltage is ZF (s) = Rd + 1 / sC (9) ∴Ip · ZF (s) = Ip (Rd + 1 / sC) = Ip · Rd + Ip / sC (10)

If an ideal differentiator is used as the differentiator 40 described above, then the capacitor 2
The impedance ZF (s) of 2 is only the capacitance C. Therefore, when a signal obtained by differentiating the charge pump output voltage is added to the charge pump output voltage, the added output V _s is V _s = charge pump output + differentiator output, where ks is the transfer function of the differentiator 40. (11) ∴V _s = Ip / sC + (ks · Ip) / sC = Ip (k / C) + Ip / sC (12)

When the equations (12) and (10) are compared, the damping resistance Rd is (k / C).
It turns out that Therefore, PL using the differentiator 40
The damping factor ζ of the L circuit 10 is given by Equation (6) as follows: ζ = ωn · k / 2 (13) The natural angular frequency ωn is the same as when the damping resistor Rd is used (see the equation (5)).

Assuming that an ideal differentiator is used as the differentiator 40 in this way, theoretically, the damping resistance R
shows the same response as the one with the addition of d, k
With the gain of 0, the value of the damping factor ζ can be set arbitrarily.

This will be described with reference to FIG. Figure 2
A differential output is obtained only when the output voltage of the capacitor 22 is changing like A and B, and this is added to the capacitor output voltage, so that the control voltage for the VCO 12 is as shown in FIG. 2C. The change in the output voltage of the capacitor 22 depends on the charge pump current Icp and the capacitor 2
Since the value is determined by the capacitance C of 2, the peak value of the differential output can be changed by the gain k of the differentiator 40. This corresponds to changing the damping resistance Rd.

Even if it is left as it is, it has the same merit as changing the damping resistance electronically.
The waveform of the control voltage applied to is the same as that when the damping resistor Rd is used. This is improved by the configuration shown in FIG.

The configuration of FIG. 3 follows the basic configuration of FIG. 1 as it is, and further, a low-pass filter 46 is connected between the charge pump circuit 18 and the adder 42 to such an extent that the phase delay is not affected. .

In this way, the rapid change in the capacitor output voltage output from the charge pump circuit 18 is filtered by the low-pass filter 46 (FIGS. 4A and 4B).
reference). Since the differential processing is performed on the filtered output voltage waveform, a rapid change in the differential output can be effectively suppressed by this (FIG. 4C). As a result, V
The peak value of the control voltage supplied to the CO 12 also becomes small (FIG. 4D), and the differential output value ΔP superimposed on the charge pump output voltage can be suppressed.

The smaller the peak value of ΔP, the more V
The variable oscillation range of the CO 12 can be narrowed and the dynamic range of the entire PLL circuit 10 can be designed small. When the dynamic range of the circuit becomes small, the value of the operating voltage supplied to this circuit can be lowered, and a low voltage power supply can be used. Along with this, it is possible to incorporate the PLL circuit 10 into the IC by devising the circuit configuration of the PLL circuit 10 such as the differentiator 40 having a differential amplifier configuration.

When the charge pump circuit 18 has a differential structure, high-frequency switching noise is generated, but the low-pass filter 46 described above also has a function of suppressing this high-frequency noise.

In each of the above-described embodiments, an ideal differentiator is used as the differentiator 40. In practice, a first-order incomplete differentiator composed of CR is used.
The circuit configuration when the first-order incomplete differentiator is used is the same as that in FIGS. 1 and 3, but is shown again in FIG. 5 as the first-order incomplete differentiator 50.

When the differentiator 50 is a first-order incomplete differentiator,
If the transfer function is kst / (1 + st) (14), the output voltage V _{s at} that time is

[0042]

[Equation 4]

The damping factor ζ is ζ = ωn · k · t / 2 (17) k is the gain of the differentiator 50, and t is the differential time constant.

The angular frequency ωn is the same as when the ideal differentiator 40 is used. By controlling the gain k or the differential time constant t from the equation (17), the same damping effect as when the damping resistor Rd is used can be obtained.

FIG. 6 shows an operation waveform diagram when the first-order incomplete differentiator 50 is used. As is apparent from the figure, a differential output with a suppressed peak value is obtained (B in the figure), and this is added to the charge pump output voltage in A in the figure, so that the peak value of the final control voltage is sufficiently increased. It can be suppressed (Fig. C).

If the low-pass filter 46 is connected to the first-order incomplete differentiator 50 as shown in FIG.
A waveform (B in the same figure) in which abrupt changes in the charge pump output voltage are suppressed as in B is input to the first-order incomplete differentiator 50, whereby the peak value of the control voltage can be further suppressed (C in the same figure, C). D).

FIG. 9 shows a specific example of the first-order incomplete differentiator 50, which is a pair of transistors Qa and Q forming a differential amplifier.
Variable constant current sources 56 and 58 are connected to the emitter side of b, respectively, and a differentiating capacitor 60 is connected between both emitters. Load resistors 62 and 64 in which the collector and base of the transistors are directly connected are connected to the collectors of the pair of transistors Qa and Qb.

A charge pump output voltage signal is differentially supplied to each base terminal 66 of the pair of transistors Qa and Qb, and a differential output is differentially obtained from a terminal 68 provided on the load resistors 62 and 64 side. To be Then, in this example, the current value i of the current source is controlled by the control signal supplied to the terminal 70.
Is controlled to control the differential time constant of the differentiator. The transfer function of this first-order incomplete differentiator is Vout / Vin = 2re / (2re + 1 / (sC)) = st / (1 + st) (18) t = 2re / where the emitter differential resistance of the transistor is re C ... Differential time constant re = 26 / i When the unit of i is [mA], re becomes [Ω].

Since the value of re can be adjusted by controlling the current i, it can be understood from the above equation that only the differential time constant can be controlled without changing the gain of the differentiator.

Therefore, the damping factor of the phase locked loop can be controlled by the current i.

Damping can be controlled even if the differential output is added to the adder through the amplifier having the amplification degree k in order to change k in the equation (17) while keeping the differential time constant of the first-order incomplete differentiator constant. Is. In the above first-order incomplete differentiator, k =
It is 1.

The present invention can also be applied to a PLL circuit that outputs a frequency N times the frequency of the reference signal as shown in FIG. In this case, the oscillation output from the VCO 12 is divided into 1 / N by the frequency dividing circuit 52 and supplied to the phase comparator 16. The other structure is the same, so its explanation is omitted.

[0053]

As described above, according to the present invention, a differentiator is used in place of the damping resistor and the phase locked
This is what constitutes a loop.

According to this, when the ideal differentiator is used, the damping factor ζ can be controlled by the conversion coefficient k, and when the first-order incomplete differentiator is used,
The damping factor ζ can be controlled by the differential time constant of the differentiator, that is, the cutoff frequency and the gain of the differentiator. Therefore, it has a feature that an appropriate damping factor ζ can be set without using a damping resistor.

Of course, the damping factor ζ can be changed by changing the value of the charge pump current or the sensitivity of the VCO.
Can be controlled. Further, since the peak value of the differential output can be effectively suppressed by providing the low-pass filter in the phase locked loop, it becomes possible to narrow the oscillation frequency range of the VCO. As a result, the dynamic range of the phase locked loop system can be narrowed and the operating voltage can be lowered. The response speed of the VCO may be slow.

In combination with this reduction in the power supply voltage, the damping factor ζ can be arbitrarily set by electronically controlling the cutoff frequency and gain of the differentiator, so that the phase locked loop system is built in the IC. It becomes possible to do it. Therefore, the present invention is extremely suitable for an electronic circuit system that outputs a clock that is phase- and frequency-synchronized with an input reference signal or outputs a clock that is phase-synchronized with input data.

[Brief description of drawings]

FIG. 1 is a system diagram showing a first embodiment of a phase locked loop circuit according to the present invention.

FIG. 2 is an explanatory diagram of the operation.

FIG. 3 is a system diagram showing a second embodiment of the phase locked loop circuit according to the present invention.

FIG. 4 is an explanatory diagram of the operation.

FIG. 5 is a system diagram showing a third embodiment of the phase locked loop circuit according to the present invention.

FIG. 6 is an explanatory diagram of the operation.

FIG. 7 is a system diagram showing a fourth embodiment of the phase locked loop circuit according to the present invention.

FIG. 8 is an explanatory diagram of the operation.

FIG. 9 is a connection diagram showing a specific example of a first-order incomplete differentiator.

FIG. 10 is a system diagram showing a fifth embodiment of the phase locked loop circuit according to the present invention.

FIG. 11 is a system diagram of a conventional phase locked loop circuit.

FIG. 12 is an explanatory diagram of the operation.

FIG. 13 is a system diagram showing an example of a charge pump circuit.

FIG. 14 is an explanatory diagram of the operation.

FIG. 15 is a diagram for explaining a conventional operation.

FIG. 16 is a system diagram showing another conventional example.

FIG. 17 is a system diagram showing still another conventional example.

FIG. 18 is an explanatory diagram of the operation.

FIG. 19 is a system diagram showing still another conventional example.

[Explanation of symbols]

 10 PLL circuit 12 VCO 16 Phase comparator 18 Charge pump circuit 22 Integrating capacitor 40 Differentiator 42 Adder 50 Primary incomplete differentiator 52 Dividing circuit

Claims (8)

[Claims] 1. A variable oscillator, a phase comparator for performing a phase comparison between the variable oscillation output and a reference signal, a conversion circuit for converting into a control signal according to the phase comparison output, and a differentiator for differentiating the control signal. And a signal obtained by adding the control signal to a differential signal to control the oscillation frequency of the variable oscillator. 2. The phase locked loop circuit according to claim 1, wherein a voltage controlled variable oscillator is used as the variable oscillator. 3. The phase locked loop circuit according to claim 1, wherein a charge pump circuit is used as the conversion circuit. 4. The phase locked loop circuit according to claim 1, wherein an ideal differentiator or a first-order incomplete differentiator is used as the differentiator. 5. The phase locked loop circuit according to claim 1, wherein a damping factor of the phase locked loop can be set by a gain of the differentiator. 6. The phase locked loop circuit according to claim 1, wherein a damping factor of the phase locked loop can be set by a differential time constant of the differentiator. 7. The phase difference is obtained by changing the ratio of addition of the differential output of the differentiator and the charge pump output.
2. The phase locked loop circuit according to claim 1, wherein a damping factor of the locked loop can be set. 8. The phase-locked loop circuit according to claim 1, further comprising a low-pass filter connected in a stage subsequent to the charge pump circuit used as the conversion circuit.