JPH08330934A - Semiconductor circuit - Google Patents

Abstract

PURPOSE: To adjust the signal timing by accelerating or decelerating the signal propagation or compensating the delay and advance of the signal propagation by making use of a crosstalk effect. CONSTITUTION: A signal line L32 connected to the output terminal of an inverter 32 is placed adjacent to a signal line L12. A signal S32 put on the line L23 has its phase adverse to a signal S12 put on the line L12 and also precedes the signal S12. Thus the propagation of the signal S12 is decelerated by a crosstalk effect. Then a signal line L10 connected to the output terminal of an inverter 10 is placed adjacent to a signal line L22. A signal S10 put on the line L10 has the same phase as a signal S22 put on the line L22 and also precedes the signal S22. Thus the propagation of the signal S22 is accelerated by the crosstalk effect. Furthermore, the delay and advance of signal propagation due to the crosstalk effect can be compensated by the adjacent placement between a signal line connected to an inverter and a signal line connected to no inverter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit which utilizes or cancels the crosstalk effect between adjacent signal wirings.

[0002]

2. Description of the Related Art With the high integration of semiconductor integrated circuits, on the one hand, the wiring interval is reduced and the wiring density is increased, and on the other hand, the multi-layer wiring technology is advanced and the inter-wiring capacitance is increased to increase the vertical or horizontal direction. Crosstalk between adjacent signal lines cannot be ignored. Crosstalk delays or speeds up signal propagation and causes a signal timing deviation, but it has become difficult to detect and correct all timing deviations due to the increased wiring density.

When the second signal line is adjacent to the first signal line, in order to prevent crosstalk from the second signal line to the first signal line, in the conventional semiconductor circuit, the first signal line and the first signal line are connected to each other. By arranging a new third signal line between the two signal lines and making the signal on the third signal line in phase with the signal on the first signal line, the first signal line and the third signal line are separated. The interconnection capacitance between them was substantially reduced (Japanese Patent Laid-Open No. 5-8264).
6). As a result, there is no need to detect and correct a timing shift due to crosstalk.

[0004]

However, it is necessary to dispose a new third signal line, and in order to prevent crosstalk from the third signal line to the second signal line,
Since it is necessary to dispose a new fourth signal line between the second signal line and the third signal line to make the signal on the fourth signal line in phase with the signal on the second signal line, the wiring density Substantially lower.

If there is a slight phase difference between the signal on the first signal line and the signal on the third signal line, crosstalk can be prevented by the mutual capacitance between the first signal line and the third signal line. In some cases, it becomes insufficient. Further, conventionally, there has been no one that positively utilizes the crosstalk effect.

Focusing on such a point, a first object of the present invention is to provide a semiconductor circuit capable of preventing crosstalk between adjacent signal lines without substantially reducing the wiring density. . A second object of the present invention is to provide a semiconductor circuit capable of substantially completely preventing the influence of crosstalk.

A third object of the present invention is to provide a semiconductor circuit which positively utilizes the crosstalk effect to adjust the signal timing by advancing or delaying signal propagation.

[0008]

According to the first aspect of the invention, the first gate, the first signal line connected to the output terminal of the first gate, and the signal in phase with the output of the first gate are provided. A second gate that outputs the signal before the output of the first gate;
A second signal line connected to the output of the second gate and disposed adjacent to the first signal line to speed up signal propagation on the first signal line.

According to the first aspect of the invention, the first of the second signal lines is provided.
By positively using the crosstalk effect on the signal line,
It is possible to accelerate the propagation of the signal on the first signal line and adjust the signal timing. In the second invention, the first gate,
A first signal line connected to the output terminal of the first gate; a second gate which outputs a signal in phase with the output of the first gate prior to the output of the first gate; and a second gate of the second gate It is connected to the output terminal and adjacent to the first signal line in order to cancel the delay of the signal propagation due to the wiring capacitance and the advance of the signal propagation on the first signal line due to the crosstalk effect on the first signal line. And a second signal line arranged.

According to the second aspect of the invention, the delay of signal propagation due to the wiring capacitance of the second signal line and the advance of signal propagation on the first signal line due to the crosstalk effect of the second signal line with respect to the first signal line cancel each other out. Therefore, it is possible to substantially completely prevent the influence of crosstalk. In a third invention, a first gate, a first signal line connected to an output terminal of the first gate, and a signal in phase with the output of the first gate are output later than the output of the first gate. It has two gates and a second signal line connected to the output terminal of the second gate and arranged adjacent to the first signal line for delaying signal propagation on the first signal line.

According to the third aspect of the invention, the first of the second signal lines is provided.
By positively using the crosstalk effect on the signal line,
It is possible to delay the propagation of the signal on the first signal line and adjust the timing of the signal. In the fourth invention, a first signal line and an inverter arranged adjacent to the first signal line,
A first signal line connected to the input terminal of the inverter;
A second signal line arranged adjacent to the first signal line and a third signal line connected to the output terminal of the inverter and arranged adjacent to the second part of the first signal line. The lagging / advancing effect of signal propagation of the two signal lines with respect to the first signal line is offset by the lagging / advancing effect of signal propagation of the third signal line with respect to the first signal line.

According to the fourth aspect of the invention, since a new signal wiring only for preventing crosstalk is not required, it is possible to prevent the wiring density from being substantially lowered, and the first signal line of the second signal line is prevented. The delay effect of signal propagation to the signal line is
Since the signal lines cancel each other out due to the delay and advance effect of signal propagation with respect to the first signal line, crosstalk between adjacent signal lines can be prevented.

In a first aspect of the fourth aspect of the present invention, the transistors have wiring regions arranged in a grid pattern, and the transistors are arranged in the first to third aspects.
The signal line is wired in the wiring region, and the inverter is composed of the transistor. According to this first aspect,
Since the transistors are arranged in a grid in the wiring area, the layout of wiring can be designed automatically or manually without consideration of crosstalk, and after this design, the inverter can be easily inserted at an appropriate position in the wiring. Can be dressed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a semiconductor circuit of the first embodiment which utilizes the crosstalk effect. The output end of the inverter 10 is connected to the clock signal input end of the logic circuit 14 via the inverters 11 to 13 on the one hand, and is connected to the clock signal input end of the logic circuit 24 via the inverters 21 to 23 on the other hand. . The drive capability of the clock signal CLK is amplified on the one hand by the inverters 10 to 13 and supplied to the logic circuit 14, and on the other hand, the inverters 10 and 21 to 21.
The driving capability is amplified by 23 and supplied to the logic circuit 24. Each of the logic circuits 14 and 24 has, for example, a D flip-flop, and the clock signal is supplied to its clock signal input terminal.

The inverter 22 and the inverter 23 are more than the signal line L12 between the inverter 12 and the inverter 13.
Since the signal line L22 between the logic circuit 14 and
The clock signal supplied to the logic circuit 24 is delayed more than the clock signal supplied to the logic circuit 24 and the timing of the synchronous operation is deviated. In the following, it is assumed that the clock signal supplied to the logic circuit 14 is too early and the clock signal supplied to the logic circuit 24 is too late.

The crosstalk effect will be described with reference to FIG. The output end of the inverter 1 and the input end of the inverter 2 are connected by a signal line L1, the output end of the inverter 3 and the input end of the inverter 4 are connected by a signal line L3, and the signal line L3 is a signal line. It is arranged adjacent to L1. In FIG. 3A, p of the inverter i (i = 1 to 4) is
The MIS transistor and the nMIS transistor are respectively represented by iP and iN, the input signal and the output signal of the inverter 1 are represented by signals S0 and S1, respectively, and the input signal and the output signal of the inverter 3 are represented by signals S2 and S3, respectively.
It is represented by. This MIS is a concept including MOS. The wiring capacitance of the signal line L1 is represented by C1, the wiring capacitance of the signal line L3 is represented by C3, and the signal line L1 and the signal line L3 are represented.
The mutual wiring capacitance between and is represented by C13.

FIG. 3B shows the waveforms of the signals S0 to S3 when the signal S0 and the signal S2 are in phase and the signal S2 falls before the signal S0. First, the signal S0
And S2 are high level, pMIS transistors 1P and 3
P is off, nMIS transistors 1N and 3N are on,
The signal lines L1 and L3 are at low level. From this state, when the signal S2 transitions to a low level, the nMIS transistor 3N turns off, the pMIS transistor 3P turns on, and the power supply line Vdd changes the pMIS transistor 3P.
On the one hand, the current flows to the wiring capacitance C3, and on the other hand, the current flows to the wiring capacitance C1 via the wiring capacitance C13. Therefore, the potential of the signal line L1 rises in conjunction with the signal line L3.

Next, when the signal S0 transits to the low level,
The nMIS transistor 1N is turned off, the pMIS transistor 1P is turned on, current flows from the power supply line Vdd through the pMIS transistor 1P to the wiring capacitance C1, and the signal line L1 becomes high level. When the wiring capacitance C13 is 0, the signal S1 changes like S10 shown by the alternate long and short dash line. However, because the wiring capacitance C13 is not 0 and the signal S2 precedes the signal S0 and changes in level in the same direction. The crosstalk effect that the propagation of the signal S1 on the signal line L1 is accelerated occurs.

Even when the signal S2 and the signal S0 are transited to the high level, similarly to the above, the wiring capacitance C13 is not 0 and the signal S2 precedes the signal S0 and changes its level in the same direction, whereby the signal line L1 is changed. A crosstalk effect occurs in that the propagation of the signal S1 above is accelerated. Figure 3 (C)
Indicates that the signal S0 and the signal S2 have opposite phases and the signal S2 is the signal S0.
Signals S0 to S3 when rising earlier
Shows the waveform of.

First, the signal S0 is at a high level, the signal S2 is at a low level, the pMIS transistor 1P and the nMIS transistor 3N are off, and the nMIS transistors 1N and pM.
The IS transistor 3P is turned on, the signal line L1 is at a low level,
The signal line L3 is at high level. From this state, when the signal S2 transitions to a high level, the nMIS transistor 3N turns on and the pMIS transistor 3P turns off,
On the one hand, a current flows from the wiring capacitance C3 through the nMIS transistor 3N to the ground line, and on the other hand, a current flows from the wiring capacitance C1 through the wiring capacitance C13 and the nMIS transistor 3N to the ground line. Therefore, the potential of the signal line L1 drops in conjunction with the signal line L3.

Next, when the signal S0 transits to the low level,
The nMIS transistor 1N is turned off, the pMIS transistor 1P is turned on, current flows from the power supply line Vdd through the pMIS transistor 1P to the wiring capacitance C1, and the signal line L1 becomes high level. When the wiring capacitance C13 is 0, the signal S1 changes like S10 shown by the alternate long and short dash line. However, because the wiring capacitance C13 is not 0 and the signal S2 precedes the signal S0 and changes in level in the opposite direction. The crosstalk effect that the propagation of the signal S1 on the signal line L1 is delayed occurs.

Even when the signal S2 changes to the low level and the signal S0 changes to the high level, the wiring capacitance C13 is the same as above.
Is not 0 and the level of the signal S2 changes in the opposite direction prior to the signal S0, which causes a crosstalk effect that the propagation of the signal S1 on the signal line L1 is delayed. In FIG. 1, the output end of the inverter 10 is connected to the input end of the inverter 33 via the inverter 32 in order to reduce the above-mentioned timing deviation.
Signal line L3 between the output end of the inverter and the input end of the inverter 33
2 is arranged adjacent to the signal line L12. The signal S32 on the signal line L32 is the signal S12 on the signal line L12.
The signal S12 and the signal S12 precede the signal S12 by the signal propagation delay time of the inverter 11. Therefore, due to the crosstalk effect of the signal line L32 with respect to the signal line L12, the propagation of the signal S12 is delayed, and the above timing shift is reduced.

The signal line L is connected to the output terminal of the inverter 10.
10 are connected, and the signal line L10 is arranged adjacent to the signal line L22. The signal S10 on the signal line L10 is in phase with the signal S22 on the signal line L22, and precedes the signal S22 by the signal propagation delay time of the inverters 21 and 22. Therefore, the signal S22 is generated by the crosstalk effect of the signal line L10 with respect to the signal line L22.
Is accelerated and the above timing deviation is reduced.

In FIG. 1, both advance and delay of signal propagation due to the crosstalk effect are used, but a configuration in which only one is used may be used. Further, in the above-described conventional technique for preventing crosstalk, if there is a slight phase shift between signals on adjacent signal lines, crosstalk may not be sufficiently prevented due to mutual capacitance between adjacent signal lines. However, for example, in FIG. 1, by making the signal advance of the signal line L10 with respect to the signal line L22 due to the crosstalk effect and the signal delay of the signal S22 due to the capacitance of the signal line L10 substantially equal, the signal propagation as a whole is improved. The advance / delay can be made smaller, and the first embodiment can be applied to such an application.

[Second Embodiment] FIG. 2 shows a semiconductor circuit of the second embodiment which utilizes the crosstalk effect. In this circuit, the signal line L11 is connected to the output terminal of the inverter 11 without using the inverters 32 and 33 of FIG.
11 is arranged adjacent to the signal line L12. Further, the input end of the inverter 30 is connected to the input end of the inverter 10, the MIS capacitor C0 is connected to the output end of the inverter 30 via the signal line L30, and the signal line L30 is arranged adjacent to the signal line L22. ing.

The signal S11 on the signal line L11 is the signal line L
12 has a phase opposite to that of the signal S12 on the inverter 12 and the inverter 1
Since the signal propagation delay time of 2 precedes the signal S12, the crosstalk effect of the signal line L11 with respect to the signal line L12 delays the propagation of the signal S12 and reduces the timing shift. Further, because of the capacitance of the signal line L11, the signal propagation from the inverter 11 to the inverter 12 is delayed as compared with the case of FIG. 1, so that the delay effect of the signal S12 is larger than that of FIG.

The signal S30 on the signal line L30 is
22 has the same phase as the signal S22 on the inverter 22 and the inverter 2
1 and 22 signal propagation delay time and MIS capacitor C0
Signal S22 by the difference from the propagation delay time of signal S30
Since it precedes, the signal line L to the signal line L22
The crosstalk effect of 30 speeds up the propagation of the signal S22 and reduces the timing shift. Further, in FIG. 1, the signal propagation from the inverter 10 to the inverter 21 is delayed by the capacitance of the signal line L10.
In this case, since the inverter 30 is used, this delay is prevented, and the signal S22 is propagated earlier than in the case of FIG.

The MIS capacitor C0 is connected to the signal S2.
This is for adjusting the time difference between the signal No. 2 and the signal S30 to be shorter. [Third Embodiment] FIG. 4 shows a semiconductor circuit of the third embodiment in which the crosstalk effect is canceled. This circuit is one block on the semiconductor chip 40, and FIG. 4 shows its schematic configuration.

In FIG. 4, 41 to 58 are logic circuits, which are L
41, L43 to L45, L470 to L473, L49,
L500 to L502, L52, L53, L56 and L5
Reference numeral 7 is a signal wiring between the logic circuits. Reference numeral 60 denotes a wiring region for canceling out the crosstalk effect between the wirings, and the CMIS transistors 61 are arranged in a lattice pattern in the wiring region 60. One CMIS transistor 61 is one
It is composed of a pair of nMIS transistor and pMIS transistor. Inverters 471-473, 501 and 502
Are each composed of one CMIS transistor 61. The high-density parallel long wiring is wired in the wiring region 60.

The signal line L43 connected between the output end of the logic circuit 43 and the input end of the logic circuit 44, the signal line L44 connected to the input end of the logic circuit 45, and the logic circuit 49.
The signal line L49 connected to the output end of the wiring is wired along the longitudinal direction of the wiring region 60, and no inverter is interposed in these wirings. It is twice the interval.

Between the signal line L44 and the signal line L43,
Signal lines L470 to L473 connecting the output end of the logic circuit 47 and the input end of the logic circuit 48 are arranged, and the inverters 471 to 473 are connected between these signal lines. Further, between the signal line L43 and the signal line L49, signal lines L500 to L502 that connect the output end of the logic circuit 50 and the input end of the logic circuit 51 are arranged, and the inverter 501 is provided between these signal lines. And 502 are connected.

Signals on signal line L501 and signal line L502
Since the phases of the above signals are opposite to each other, the signal line L4
The signal propagation delay advance effect (crosstalk effect) of the signal line L501 for the signal line No. 3 is the signal line L5 for the signal line L43.
The signal has a relationship opposite to the signal propagation delay / advance effect of 02, and both effects cancel each other out. Similarly, the signal propagation delay advance effect of the signal line L43 with respect to the signal line L501 and the signal line L502.
And the signal propagation delay advance effect of the signal line L43 with respect to each other cancel each other out. Such a crosstalk canceling effect is exerted between the signal lines L501 and L502 and the signal line L49, between the signal line L44 and the signal lines L470 to L473, and between the signal lines L470 to L473 and the signal line L43. Also occurs.

Due to the crosstalk canceling effect, wiring can be performed without considering the delay or advance of signal propagation due to the crosstalk effect. Therefore, for a semiconductor integrated circuit having a high degree of integration, a complicated and enormous work of detecting and correcting a timing shift due to crosstalk becomes unnecessary. Further, since the crosstalk canceling effect is obtained without wiring extra signal lines, it is possible to prevent the wiring density from being substantially reduced.

Further, since the CMIS transistors 61 are arranged in the wiring region 60 in a grid pattern, the wiring is laid out automatically or manually without considering crosstalk.
After this layout, the inverter may be provided at the appropriate position in the wiring as described above, which facilitates the wiring layout design. Since this inverter can be used as a buffer circuit for amplifying the driving capability, the buffer inverter at the output stage of the logic circuits 47 and 50 can be omitted by that much, and the signal due to the extra use of the inverter can thus be omitted. Propagation delay can be reduced. Further, this delay time can be easily predicted at the design stage, unlike the crosstalk effect between the wirings, so that the timing deviation can be corrected at the design stage.

The signal lines L41 and L54 have a relatively long wiring length, but since the density of long wiring is low, the influence of crosstalk is small and it is not necessary to pass them through the wiring region 60. Signal line L
Since 52, L53, L56 and L57 have a relatively short wiring length, it is not necessary to pass them through the wiring region 60. In addition, the present invention includes various modifications. For example, the first
The third to third embodiments are not limited to the adjacent wirings in the same wiring layer,
It is also applicable to adjacent wiring between different wiring layers. Further, the present invention can be applied to various semiconductor integrated circuits, as is clear from its configuration and operational effects.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor circuit utilizing a crosstalk effect according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a semiconductor circuit using a crosstalk effect according to a second embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of using the crosstalk effect.

FIG. 4 is a diagram showing a semiconductor circuit according to a third embodiment of the present invention, in which a crosstalk effect is canceled.

[Explanation of symbols]

1-4, 10-13, 21-23, 30-33, 471
˜473, 501, 502 Inverter 14, 24, 41-58 Logic circuit 40 Semiconductor chip 60 Wiring area 61 CMIS transistor C1, C3, C13 Wiring capacity C0 MIS capacitor

Claims (5)

[Claims] 1. A first gate, a first signal line connected to an output terminal of the first gate, and a signal in phase with the output of the first gate prior to the output of the first gate. A second signal line, and a second signal line connected to an output terminal of the second gate and arranged adjacent to the first signal line for speeding up signal propagation on the first signal line. Semiconductor circuit. 2. A first gate, a first signal line connected to an output terminal of the first gate, and a signal in phase with the output of the first gate prior to the output of the first gate. The second gate is connected to the output terminal of the second gate, and is for canceling the delay of signal propagation due to the wiring capacitance and the advance of signal propagation on the first signal line due to the crosstalk effect on the first signal line. And a second signal line arranged adjacent to the first signal line. 3. A first gate, a first signal line connected to an output terminal of the first gate, and a signal which is in phase with the output of the first gate and is delayed from the output of the first gate. Two gates and a second signal line connected to the output terminal of the second gate and arranged adjacent to the first signal line for delaying signal propagation on the first signal line. Semiconductor circuit. 4. A first signal line, an inverter arranged adjacent to the first signal line, a first signal line connected to an input terminal of the inverter,
A second signal line disposed adjacent to the first section and a second signal line of the first signal line connected to the output terminal of the inverter.
A third signal line disposed adjacent to the section, and a delay advance effect of signal propagation of the second signal line with respect to the first signal line, a signal of the third signal line with respect to the first signal line. A semiconductor circuit characterized by being offset by the effect of delay and advance of propagation. 5. The transistor has a wiring region arranged in a grid, the first to third signal lines are wired in the wiring region, and the inverter is composed of the transistor. The semiconductor circuit according to claim 4.