JPH08330354A - Semiconductor device - Google Patents

Abstract

PURPOSE: To suppress the noise on a power source line generated when parasitic capacitance is charged and discharged by a method wherein the impedance of the part which is cut when the device is actually used, is increased between an LSI pad and a test pad in a TAB when a functional test is performed. CONSTITUTION: In a semiconductor device having a plurality of TAB leads 3 which are connected to a testing pad 2 from an LSI pad 1 when a functional test is conducted, the resistance value of the part of the TAB leads 3 which is cut when it is actually used is made higher than the resistance value of the remaining part. To be more precise, the width of a part of the TAB leads 3 of an output terminal is made narrower in the amount of (x) than the conventional width. As a result, the peak value of the transient current when an output signal is inverted becomes small, the noise of the power source line of the semiconductor integrated circuit to be measured becomes small, and the erroneous operation when a functional test is conducted can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a TAB lead.

[0002]

2. Description of the Related Art In recent years, as downsizing of semiconductor devices progresses, TAB leads are often used for the purpose of improving packaging density.

FIG. 3 shows an example of a conventional semiconductor device using a TAB lead. FIG. 3 (A) shows the state during a functional test, and FIG. 3 (B) shows the state during actual use. ing. In the semiconductor device shown in FIG. 3, the LSI pad was connected to the test pad by a TAB lead having a relatively small impedance and the same impedance on all pins.

When performing a functional test of a semiconductor device, a semiconductor integrated circuit measuring instrument inputs and outputs an electric signal through a TAB lead and a test pad.

A semiconductor device which has passed the functional test in the TAB form is cut from the carrier tape, lead-shaped, and connected to a desired package. At that time, the TAB lead is cut uniformly, but impedance is not taken into consideration.

[0006]

As described above,
When performing a functional test of a conventional semiconductor device, in a semiconductor integrated circuit measurement system, if an LSI pad to a semiconductor integrated circuit measuring device are included, an excessive parasitic capacitance may be added as compared with the actual use state of the semiconductor integrated circuit. Many. As a result, there is a drawback that noise is generated in the power supply line due to charging and discharging of the parasitic capacitance during measurement of the semiconductor integrated circuit, and the noise causes the semiconductor integrated circuit to malfunction.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
It is characterized in that the impedance of a portion between the LSI pad and the test pad in at least one TAB at the time of the function test, which is cut during the actual use, is increased.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and FIG.
Shows the state at the time of the functional test, and FIG. 1 (B) shows the state at the time of the actual use. In FIG. 1, a part of the TAB lead of the output terminal is narrower than the conventional width by x. At this time, when the thickness of the TAB lead is D, the conventional width is W, and the resistivity of the material of the lead is ρ, the impedance Z of the lead length L is Z = ρ · L /
(D · W) was Z = ρ · L / {D · (W-
x)}. The parasitic capacitance of the measurement system during the functional test is C
Let p be the output impedance of the measured terminal and Re be
The charging / discharging time constant T of the parasitic capacitance Cp is the conventional T = Cp · {R
From e + ρ · L / (D · W)}, T = Cp · [Re + ρ ·
L / {D · (W−x)}]. As a result, the peak value of the transient current when the output signal is inverted is reduced, the noise on the power supply line of the semiconductor integrated circuit under test is reduced, and malfunction during the functional test can be prevented.

In this embodiment, the TAB leads whose width is reduced are a part of the TAB leads related to the functional test, but all the TAB leads may be reduced in width to have the same shape.

FIG. 2 shows another embodiment of the present invention. FIG. 2 (A) shows the state at the time of the functional test.
(B) shows the state at the time of actual use. In this way, by increasing the length of the TAB lead of the signal terminal from y to L, the impedance of the lead portion becomes R = ρ · L /
(D · W) can be increased to R = ρ · (L + y) / (D · W), and the charging / discharging time constant T of the parasitic capacitance Cp is T = Cp ·
From {Re + ρ · L / (D · W)}, T = Cp · {Re +
ρ · (L + y) / (D · W)}. As a result, the same effect as that of the first embodiment can be obtained.

The method described above is a method of increasing the impedance of the lead portion by changing the shape of the TAB lead of the output terminal. In addition to this, the impedance can be changed by changing the resistivity ρ, that is, by changing the material. Even if it is increased, the same effect can be obtained. Specifically, instead of the narrow width portion in the first embodiment, the material having a high resistivity in that portion may be used.

[0012]

As described above, according to the present invention, by increasing the impedance of the TAB lead between the LSI pad and the test pad in the semiconductor device, the measurement system parasitic capacitance can be satisfied during the functional test of the semiconductor integrated circuit. It has the effect of preventing malfunction due to discharge, and when the parasitic capacitance during actual use becomes small, the TAB lead can be partially cut to reduce the impedance.

[Brief description of drawings]

FIG. 1 shows the shape of a TAB according to an embodiment of the present invention.

FIG. 2 is a TAB shape according to another embodiment of the present invention.

FIG. 3 shows the shape of a conventional TAB.

[Explanation of symbols]

 1 LSI pad 2 Test pad 3 TAB lead 4 LSI D TAB thickness L TAB lead length W TAB lead width ρ TAB lead material resistivity x TAB lead width difference y y TAB lead length Difference from conventional

Claims (3)

[Claims] 1. In a semiconductor device having a plurality of TAB leads connected from an LSI pad to a test pad during a functional test, a portion of at least one of the TAB leads that is cut during actual use is a portion that remains during actual use. A semiconductor device characterized by being made higher than a resistance value. 2. The semiconductor device according to claim 1, wherein a portion of the TAB lead having a high resistance value is narrower than a portion of another TAB lead. 3. The semiconductor device according to claim 1, wherein the TAB lead having a high resistance value is longer than other TAB leads.