JP2680132B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2680132B2 JP2680132B2 JP1172162A JP17216289A JP2680132B2 JP 2680132 B2 JP2680132 B2 JP 2680132B2 JP 1172162 A JP1172162 A JP 1172162A JP 17216289 A JP17216289 A JP 17216289A JP 2680132 B2 JP2680132 B2 JP 2680132B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode pad
- chip
- test
- pad
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
【発明の詳細な説明】 ［概要］ 半導体装置に係り、特に高速動作を行なう半導体装置
に関し、 ICチップのプロービング試験を行なうことができると
共に、電極パッドの寄生容量を低減させて高速化を実現
することができる半導体装置を提供することを目的と
し、 探針プローブを当てるための第１の電極パッドと、前
記第１の電極パッドよりもパッドサイズの小さい高速信
号用の第２の電極パッドと、前記第１の電極パッドと前
記第２の電極パッドを接続する抵抗層と、前記第２の電
極パッドに接続される高速信号用回路とを有するように
構成する。The present invention relates to a semiconductor device, and more particularly to a semiconductor device that operates at high speed, and can perform a probing test of an IC chip and reduce parasitic capacitance of an electrode pad to achieve high speed. A first electrode pad for applying a probe probe, and a second electrode pad for a high-speed signal having a smaller pad size than the first electrode pad, for the purpose of providing a semiconductor device capable of The resistance layer connecting the first electrode pad and the second electrode pad, and the high-speed signal circuit connected to the second electrode pad are configured.
［産業上の利用分野］ 本発明は半導体装置に係り、特に高速動作を行なう半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device that operates at high speed.
［従来の技術］ 近年、IC（半導体集積回路）は高速化の一途を辿って
いる。これに伴って、ICチップ上の電極パッドは、交流
特性を劣化させる一因となる寄生容量を低減するため、
パッドサイズを縮小することが強く要求されている。[Prior Art] In recent years, ICs (semiconductor integrated circuits) have been increasing in speed. Along with this, the electrode pads on the IC chip reduce the parasitic capacitance that causes deterioration of AC characteristics.
There is a strong demand to reduce the pad size.
しかし、従来の半導体装置において、パッケージのイ
ンナーリードと接続されるICチップ上の電極パッドのカ
バーサイズは、100μｍ□程度である。これは、ウェー
ハ状態におけるICチップの電気的試験いわゆるプロービ
ング試験が、電極パッドに試験用の針すなわち探針プロ
ーブを当てて行なわれるためである。However, in the conventional semiconductor device, the cover size of the electrode pad on the IC chip connected to the inner lead of the package is about 100 μm □ . This is because an electrical test of an IC chip in a wafer state, that is, a probing test is performed by applying a test needle, that is, a probe probe to the electrode pad.
従って、ICの高速化に伴って電極パッドの縮小化が要
求されても、プロービング試験において電極パッドに探
針プローブを精度よく当てるのに必要とされるパッドサ
イズ以下に縮小することは困難であった。Therefore, even if the reduction in the size of the electrode pad is required as the speed of the IC increases, it is difficult to reduce the size to a size equal to or smaller than the pad size required for accurately applying the probe to the electrode pad in the probing test. It was
［発明が解決しようとする課題］ このように、上記従来の半導体装置においては、ウェ
ーハ状態におけるICチップのプロービング試験を行なう
のに100μｍ□程度のパッドサイズの電極パッドが必要
とされるため、電極パッドの寄生容量を低減させてICの
高速化を図ることは困難であった。[Problems to be Solved by the Invention] As described above, in the conventional semiconductor device described above, an electrode pad having a pad size of about 100 μm □ is required to perform a probing test of an IC chip in a wafer state. It was difficult to reduce the parasitic capacitance of the pad and increase the speed of the IC.
そこで本発明は、ICチップのプロービング試験を行な
うことができると共に、電極パッドの寄生容量を低減さ
せて高速化を実現することができる半導体装置を提供す
ることを目的とする。Therefore, an object of the present invention is to provide a semiconductor device capable of performing a probing test of an IC chip and reducing the parasitic capacitance of an electrode pad to realize high speed operation.
［課題を解決するための手段］ 第１図は、本発明の原理説明図である。[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention.
半導体チップ２のチップ端４近傍に、探針プローブを
当てるに十分な大きさのパッドサイズを有する第１の電
極パッド６が配置されている。この第１の電極パッド６
は、抵抗層Ｒを介して、第１の電極パッド６よりもパッ
ドサイズの小さい高速信号用の第２の電極パッド８に接
続されている。A first electrode pad 6 having a pad size large enough to hit a probe probe is arranged near the chip end 4 of the semiconductor chip 2. This first electrode pad 6
Is connected to the second electrode pad 8 for high-speed signals, which has a smaller pad size than the first electrode pad 6, via the resistance layer R.
そしてこの第２の電極パッド８は、半導体チップ２上
に形成された高速信号用回路のトランジスタＴと接続さ
れている。The second electrode pad 8 is connected to the transistor T of the high-speed signal circuit formed on the semiconductor chip 2.
［作用］ すなわち本発明は、パッドサイズが小さくて寄生容量
の小さい第２の電極パッド８を信号経路とすることによ
り、高速信号動作を行なうことができる。このとき、パ
ッドサイズの大きい従って寄生容量の大きい第１の電極
パッド６との間に介在する抵抗層Ｒを高抵抗とすれば、
この第１の電極パッド６の寄生容量が高速信号経路の交
流特性に影響を及ぼすことはない。[Operation] That is, according to the present invention, high-speed signal operation can be performed by using the second electrode pad 8 having a small pad size and a small parasitic capacitance as a signal path. At this time, if the resistance layer R interposed between the first electrode pad 6 having a large pad size and therefore a large parasitic capacitance has a high resistance,
The parasitic capacitance of the first electrode pad 6 does not affect the AC characteristics of the high speed signal path.
また、パッドサイズの大きい第１の電極パッド６には
探針プローブを容易に当てることができ、ウェーハ状態
における半導体チップ２のプロービング試験を安定的に
行なうことができる。このとき、プロービング試験には
低周波又は直流の試験用信号が用いられるため、抵抗層
Ｒが高抵抗であり、その高抵抗の抵抗層Ｒを介してトラ
ンジスタＴに試験用信号を入力しても、半導体チップ２
の機能試験に支障が生じることはない。Further, the probe probe can be easily applied to the first electrode pad 6 having a large pad size, and the probing test of the semiconductor chip 2 in a wafer state can be stably performed. At this time, since a low-frequency or direct-current test signal is used in the probing test, the resistance layer R has a high resistance, and even if a test signal is input to the transistor T via the high-resistance resistance layer R. , Semiconductor chip 2
There is no problem in the functional test of.
［実施例］ 以下、本発明を図示する実施例に基づいて具体的に説
明する。[Examples] Hereinafter, the present invention will be specifically described based on the illustrated examples.
第２図（ａ）は、本発明の第１の実施例による半導体
装置を示す平面図である。FIG. 2A is a plan view showing a semiconductor device according to the first embodiment of the present invention.
ICチップ12のチップ端14近傍に、カバーサイズ100μ
ｍ□程度の試験用の電極パッド16及び低速信号用の電極
パッド18と、カバーサイズ25μｍ□程度の高速信号用の
電極パッド20とがそれぞれ配置されている。そして試験
用の電極パッド16と高速信号用の電極パッド20とは、例
えば30kΩ以上の高抵抗値の抵抗層R1を介して接続され
ている。なお、この抵抗層R1は、例えば不純物拡散によ
って形成してもよいし、またポリシリコン層等を用いて
形成してもよい。Cover size 100μ near the chip edge 14 of the IC chip 12.
An electrode pad 16 for test and an electrode pad 18 for low speed signal of about m square, and an electrode pad 20 for high speed signal of about 25 μm square in cover size are arranged. The test electrode pad 16 and the high-speed signal electrode pad 20 are connected to each other through the resistance layer R1 having a high resistance value of, for example, 30 kΩ or more. The resistance layer R1 may be formed by, for example, impurity diffusion, or may be formed using a polysilicon layer or the like.
また、低速信号用の電極パッド18及び高速信号用の電
極パッド20は、ICチップ12上に形成されたトランジスタ
T1,T2にそれぞれ接続されている。Further, the electrode pads 18 for low speed signals and the electrode pads 20 for high speed signals are transistors formed on the IC chip 12.
They are connected to T1 and T2 respectively.
次いで、第２図（ａ）に示されるように配置され接続
された電極パッド16,18,20を有するIC回路の一例とし
て、ECL（Emitter Coupled Logic）回路を第２図（ｂ）
に示す。Next, an ECL (Emitter Coupled Logic) circuit is shown in FIG. 2 (b) as an example of an IC circuit having electrode pads 16, 18, 20 arranged and connected as shown in FIG. 2 (a).
Shown in
トランジスタT1,T2のコレクタC1,C2は、それぞれ抵抗
Rc1,Rc2を介して、接地されたコレクタ電源VCCに接続さ
れている。またエミッタE1,E2は、定電流源22を介し
て、一般に−5V程度の負の電圧を有する電源VEEに接続
されている。そしてトランジスタT1のベースB1は、基準
電圧VBBが印加される入力端子、即ち低速信号用の電極
パッド18に接続され、またトランジスタT2のベースB2
は、入力電圧VINが印加される入力端子、即ち高速信号
用の電極パッド20に接続されている。The collectors C1 and C2 of the transistors T1 and T2 are resistors
It is connected to the grounded collector power supply V CC via Rc1 and Rc2. Further, the emitters E1 and E2 are connected via a constant current source 22 to a power supply V EE having a negative voltage of about −5V in general. The base B1 of the transistor T1 is connected to the input terminal to which the reference voltage V BB is applied, that is, the electrode pad 18 for the low speed signal, and the base B2 of the transistor T2.
Is connected to an input terminal to which an input voltage V IN is applied, that is, an electrode pad 20 for high speed signals.
そしてさらに、負荷の駆動能力を向上させるために、
エミッタホロワ回路が付加されている。And further, to improve the drive capacity of the load,
An emitter follower circuit is added.
すなわち、トランジスタT1,T2のコレクタ電位が、そ
れぞれトランジスタT3,T4のベースに接続されている。
また、トランジスタT3,T4のコレクタはそれぞれ接地さ
れた電源VCCに接続され、またエミッタは、それぞれ定
電流源24,26を介して、負の電圧を有する電源VEEに接続
されている。そしてトランジスタT3,T4のエミッタ電位
が、それぞれ出力VOUT1,VOUT２に接続されている。That is, the collector potentials of the transistors T1 and T2 are connected to the bases of the transistors T3 and T4, respectively.
The collectors of the transistors T3 and T4 are connected to the grounded power source V CC , and the emitters are connected to the negative power source V EE via the constant current sources 24 and 26, respectively. The emitter potentials of the transistors T3 and T4 are connected to the outputs V OUT 1 and V OUT 2, respectively.
次いで、第２図に示された半導体装置のプロービング
試験について述べる。Next, a probing test of the semiconductor device shown in FIG. 2 will be described.
半導体装置のプロービング試験は、ウェーハ状態にお
いて、ICチップ12上の試験用の電極パッド16及び低速信
号用の電極パッド18に探針プローブを当てて行なう。こ
のとき、電極パッド16,18のチップサイズは100μｍ□程
度であるため、30μｍφ程度の太さの探針プローブであ
っても十分に精度よく当てることができる。The probing test of the semiconductor device is performed by applying a probe probe to the test electrode pad 16 and the low speed signal electrode pad 18 on the IC chip 12 in a wafer state. At this time, since the chip size of the electrode pads 16 and 18 is about 100 μm □ , even a probe probe having a thickness of about 30 μmφ can be applied with sufficient accuracy.
また、試験用信号は探針プローブを通って電極パッド
16に入力され、30kΩ以上の高抵抗値の抵抗層R1を経由
してトランジスタT2に伝搬されるが、このときの試験用
信号には低周波信号又は直流信号が用いられるため、IC
チップ12の論理チェック等の機能試験には何等の支障も
生じない。In addition, the test signal passes through the probe and the electrode pad.
It is input to 16 and is propagated to the transistor T2 through the resistance layer R1 having a high resistance value of 30 kΩ or more, but the low-frequency signal or DC signal is used for the test signal at this time, so the IC
No problem occurs in the functional test such as the logic check of the chip 12.
次いで、組立後の半導体装置の動作について、第３図
を用いて述べる。Next, the operation of the semiconductor device after assembly will be described with reference to FIG.
第２図（ａ）に示されたICチップ12がパッケージ30上
に搭載されている。そしてICチップ12のチップ端14近傍
の低速信号用の電極パッド18が、パッケージ30に配置さ
れ基準電圧VBBが印加されるインナーリード32とボンデ
ィングワイヤ33によって接続されている。同様にして、
高速信号用の電極パッド20が、パッケージ30に配置され
入力電圧VINが印加されるインナーリード34とボンディ
ングワイヤ35によって接続されている。The IC chip 12 shown in FIG. 2A is mounted on the package 30. Then, the low-speed signal electrode pad 18 near the chip end 14 of the IC chip 12 is connected by the bonding wire 33 to the inner lead 32 arranged in the package 30 and to which the reference voltage V BB is applied. Similarly,
The electrode pad 20 for high speed signal is connected to the inner lead 34, which is arranged in the package 30 and to which the input voltage V IN is applied, by the bonding wire 35.
このとき、高速信号用の電極パッド20のチップサイズ
は25μｍ□程度であって、探針プローブを当てるには小
さいが、ワイヤボンディングの可能な大きさである。な
お、試験用の電極パッド16は、オープンになっている。At this time, the chip size of the electrode pad 20 for high-speed signals is about 25 μm □ , which is small for hitting the probe, but large enough for wire bonding. The test electrode pad 16 is open.
このような半導体装置は、入力信号VINの信号経路と
なる高速信号用の電極パッド20のパッドサイズが25μｍ
□程度と従来の1/4程度に縮小され、従って寄生容量が
小さくなているために、高速信号動作を行なうことがで
きる。このとき、パッドサイズが100μｍ□程度と大き
く寄生容量の大きい試験用の電極パッド16と高速信号用
の電極パッド20との間には、30kΩ以上の高抵抗値を有
する抵抗層R1が介在しているために、この試験用の電極
パッド16の寄生容量が高速信号経路の交流特性に影響を
及ぼすことはない。In such a semiconductor device, the pad size of the electrode pad 20 for the high speed signal, which is the signal path of the input signal V IN , is 25 μm.
Since it is reduced to about □ and about 1/4 of that of the conventional one, and the parasitic capacitance is reduced, high-speed signal operation can be performed. At this time, a resistance layer R1 having a high resistance value of 30 kΩ or more is interposed between the test electrode pad 16 having a large pad size of about 100 μm □ and a large parasitic capacitance and the electrode pad 20 for high speed signal. Therefore, the parasitic capacitance of the test electrode pad 16 does not affect the AC characteristics of the high-speed signal path.
このように第１の実施例によれば、一方において、パ
ッドサイズの大きい試験用の電極パッド16を用いること
により、ウェーハ状態におけるICチップ12のプロービン
グ試験を安定的に行なうことができる。また他方におい
て、パッドサイズの小さい、従って寄生容量の小さい高
速信号用の電極パッド20を信号経路とすることにより、
高速信号動作を行なうことができる。As described above, according to the first embodiment, on the other hand, by using the test electrode pad 16 having a large pad size, the probing test of the IC chip 12 in the wafer state can be stably performed. On the other hand, by using the electrode pad 20 for high-speed signals having a small pad size and thus a small parasitic capacitance as a signal path,
High-speed signal operation can be performed.
次に、第４図に用いて、本発明の第２の実施例による
半導体装置を説明する。Next, a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG.
第４図（ａ）において、第２図（ａ）に示されたICチ
ップ12がパッケージ30上に搭載されている。そしてICチ
ップ12のチップ端14近傍の低速信号用の電極パッド18及
び高速信号用の電極パッド20が、それぞれパッケージ30
に配置され、入力電圧VINが印加されるインナーリード3
2及び基準電圧VBBが印加されるインナーリード34とボン
ディングワイヤ35によって接続されている。さらに試験
用の電極パッド16が、パッケージ30に配置され、最も低
い（most negative）電源VEEが印加されるインナーリー
ド36とボンディングワイヤ37によって接続されている。In FIG. 4A, the IC chip 12 shown in FIG. 2A is mounted on the package 30. The low-speed signal electrode pad 18 and the high-speed signal electrode pad 20 near the chip end 14 of the IC chip 12 are respectively package 30
The inner lead 3 which is placed at the input voltage V IN
2 and the inner lead 34 to which the reference voltage VBB is applied, and the bonding wire 35. Further, a test electrode pad 16 is disposed on the package 30 and is connected to the inner lead 36 to which the most negative power source V EE is applied by the bonding wire 37.
この第４図（ａ）に示される半導体装置の回路の一例
を第４図（ｂ）に示す。An example of the circuit of the semiconductor device shown in FIG. 4 (a) is shown in FIG. 4 (b).
この回路は、第２図（ｂ）に示されたECL回路におい
て、入力電圧VINが印加される入力端子即ち高速信号用
の電極パッド20が、抵抗R1を介して、電源VEEに接続さ
れているものである。In this circuit, in the ECL circuit shown in FIG. 2 (b), the input terminal to which the input voltage V IN is applied, that is, the electrode pad 20 for high-speed signal is connected to the power source V EE via the resistor R1. It is what
次いで、動作を述べると、試験用の電極パッド16と高
速信号用の電極パッド20とを接続している30kΩ以上の
高抵抗値を有する抵抗層R1は電源VEEに接続されること
により、高速信号用の電極パッド20に入力される入力信
号VINの雑音防止用のプル・ダウン（pull−down）抵抗
として働く。Then, to describe the operation, the resistance layer R1 having a high resistance value of 30 kΩ or more, which connects the test electrode pad 16 and the high-speed signal electrode pad 20, is connected to the power supply V EE , thereby increasing the speed. It functions as a pull-down resistor for noise prevention of the input signal V IN input to the signal electrode pad 20.
このように第２の実施例によれば、一方においてウェ
ーハ状態におけるICチップ12のプロービング試験を安定
的に行なうことができるようにし、また他方において高
速信号動作を行なうことができるようにするために設け
た抵抗層R1を、入力雑音防止用のプル・ダウン（pull−
down）抵抗として用いることができる。As described above, according to the second embodiment, on the one hand, the probing test of the IC chip 12 in the wafer state can be stably performed, and on the other hand, the high speed signal operation can be performed. The resistive layer R1 provided is pulled down (pull-
down) Can be used as a resistor.
また、試験用の電極パッド16が最も低いエミッタ電源
VEEに接続されるため、試験用の電極パッド16の寄生容
量が高速信号経路の交流特性に及ぼす影響は完全に遮断
される。Also, the electrode pad 16 for testing is the lowest emitter power supply.
Since it is connected to V EE , the influence of the parasitic capacitance of the test electrode pad 16 on the AC characteristics of the high-speed signal path is completely cut off.
次に、第５図に用いて、本発明の第３の実施例による
半導体装置を説明する。Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.
第５図（ａ）に示されるICチップ42は、第２図（ａ）
に示されたICチップ12において試験用の電極パッド16と
高速信号用の電極パッド20とを接続している30kΩ以上
の高抵抗値の抵抗層R1の代わりに、抵抗値50Ω程度の抵
抗層R2が設けられている。The IC chip 42 shown in FIG. 5 (a) is shown in FIG. 2 (a).
In the IC chip 12 shown in Fig. 2, instead of the resistance layer R1 having a high resistance value of 30 kΩ or more, which connects the test electrode pad 16 and the electrode pad 20 for high-speed signal, the resistance layer R2 having a resistance value of about 50 Ω is used. Is provided.
そしてこのICチップ42がパッケージ30上に搭載されて
いる。また、ICチップ42のチップ端44近傍の低速信号用
の電極パッド18は、基準電圧VBBが印加されるインナー
リード32に接続されている。同様にして、高速信号用の
電極パッド20は、パッケージ30に配置されているインナ
ーリード34を介して、入力電圧VINが印加される伝送路Z
0に接続されている。The IC chip 42 is mounted on the package 30. The electrode pad 18 for low speed signals near the chip end 44 of the IC chip 42 is connected to the inner lead 32 to which the reference voltage V BB is applied. Similarly, the high-speed signal electrode pad 20 is connected to the transmission line Z to which the input voltage V IN is applied via the inner lead 34 arranged in the package 30.
Connected to 0 .
さらに試験用の電極パッド16は、一般に−2V程度の終
端電圧VTが印加されるインナーリード36に接続されてい
る。Further, the test electrode pad 16 is generally connected to the inner lead 36 to which a terminal voltage V T of about −2V is applied.
この第５図（ａ）に示される半導体装置の回路の一例
を第５図（ｂ）に示す。An example of the circuit of the semiconductor device shown in FIG. 5 (a) is shown in FIG. 5 (b).
この回路は、第２図（ｂ）に示されたECL回路におい
て、入力電圧VINが印加される入力端子即ち高速信号用
の電極パッド20が、抵抗R2を介して、終端電圧VTに接続
されているものである。In this circuit, in the ECL circuit shown in FIG. 2B, the input terminal to which the input voltage V IN is applied, that is, the electrode pad 20 for high-speed signal is connected to the terminal voltage V T via the resistor R2. It has been done.
次いで、動作を述べると、試験用の電極パッド16と高
速信号用の電極パッド20とを接続している抵抗値50Ω程
度の抵抗層R2は、終端電圧VTに接続されることにより、
高速信号用の電極パッド20に入力される入力信号VINの
終端抵抗として働く。Next, to describe the operation, the resistance layer R2 having a resistance value of about 50Ω connecting the electrode pad 16 for testing and the electrode pad 20 for high-speed signals is connected to the termination voltage V T ,
It works as a terminating resistor for the input signal V IN input to the electrode pad 20 for high speed signals.
このように第３の実施例によれば、一方においてウェ
ーハ状態におけるICチップ12のプロービング試験を安定
的に行なうことができるようにし、また他方において高
速信号動作を行なうことができるようにするために設け
た抵抗層R2を、ICチップ内部終端抵抗として用いること
ができる。このようなICチップ内部終端抵抗は、インピ
ーダンスのマッチングによって高周波動作に極めて有効
である。従って、半導体装置の高性能化を図ることがで
きる。As described above, according to the third embodiment, the probing test of the IC chip 12 in the wafer state can be stably performed on the one hand, and the high speed signal operation can be performed on the other hand. The provided resistance layer R2 can be used as an IC chip internal terminating resistor. Such an IC chip internal terminating resistor is extremely effective for high frequency operation due to impedance matching. Therefore, the performance of the semiconductor device can be improved.
なお、第３の実施例においては抵抗層R2が50Ω程度で
あるため、試験用の電極パッド16をオープンにしておく
と試験用の電極パッド16の寄生容量が高速信号経路の交
流特性の劣化を招くおそれがあるが、実際の使用におい
ては試験用の電極パッド16が終端電圧VTに接続されるた
め、このおそれは解消される。Since the resistance layer R2 is about 50Ω in the third embodiment, if the test electrode pad 16 is left open, the parasitic capacitance of the test electrode pad 16 causes deterioration of the AC characteristics of the high-speed signal path. However, in actual use, the test electrode pad 16 is connected to the termination voltage V T , so this fear is eliminated.
［発明の効果］ 以上のように本発明によれば、探針プローブを当てる
に十分な大きさのパッドサイズを有する第１の電極パッ
ドと第１の電極パッドよりもパッドサイズの小さい高速
信号用の第２の電極パッドとを抵抗層を介して設けるこ
とにより、第１の電極パッドを用いてプロービング試験
を行なうことができると共に、パッドサイズが小さく寄
生容量の小さい第２の電極パッドを信号経路として高速
信号動作を実現することができる。EFFECTS OF THE INVENTION As described above, according to the present invention, a first electrode pad having a pad size large enough to hit a probe probe and a high-speed signal having a smaller pad size than the first electrode pad By providing the second electrode pad with the second electrode pad via a resistance layer, a probing test can be performed using the first electrode pad, and the second electrode pad having a small pad size and a small parasitic capacitance can be connected to the signal path. As a result, high-speed signal operation can be realized.
第１図は本発明の原理説明図、 第２図及び第３図は本発明の第１の実施例による半導体
装置を示す図、 第４図は本発明の第２の実施例による半導体装置を示す
図、 第５図は本発明の第３の実施例による半導体装置を示す
図である。 図において、 ２…半導体チップ ４、14、44…チップ端 ６、８、16、18、20…電極パッド 12、42…ICチップ 22、24、26…定電流源 30…パッケージ 32、34、36…インナーリード 33、35、37…ボンディングワイヤ Ｒ、R1、R2、Rc1、Rc2…抵抗 Ｔ、T1、T2、T3、T4…トランジスタ C1、C2…コレクタ E1、E2…エミッタ B1、B2…ベース VCC…電源（MOST POSITIVE） VEE…電源（MOST NEGATIVE） VBB…基準電圧 VIN…入力電圧 VOUT１、VOUT２…出力 Z0…伝送路 VT…終端電圧FIG. 1 is a diagram for explaining the principle of the present invention, FIGS. 2 and 3 are diagrams showing a semiconductor device according to a first embodiment of the present invention, and FIG. 4 is a semiconductor device according to a second embodiment of the present invention. FIG. 5 is a diagram showing a semiconductor device according to a third embodiment of the present invention. In the figure, 2 ... Semiconductor chips 4, 14, 44 ... Chip ends 6, 8, 16, 18, 20 ... Electrode pads 12, 42 ... IC chips 22, 24, 26 ... Constant current source 30 ... Packages 32, 34, 36 … Inner leads 33, 35, 37… Bonding wires R, R1, R2, Rc1, Rc2… Resistors T, T1, T2, T3, T4… Transistors C1, C2… Collectors E1, E2… Emitters B1, B2… Base V CC … Power supply (MOST POSITIVE) V EE … Power supply (MOST NEGATIVE) V BB … Reference voltage V IN … Input voltage V OUT 1, V OUT 2… Output Z 0 … Transmission line V T … Termination voltage
フロントページの続き (56)参考文献 特開 昭49−41077（ＪＰ，Ａ) 特開 昭58−161336（ＪＰ，Ａ) 特開 昭59−52860（ＪＰ，Ａ) 特開 平２−241046（ＪＰ，Ａ) 実開 昭57−132452（ＪＰ，Ｕ)Continuation of the front page (56) References JP-A-49-41077 (JP, A) JP-A-58-161336 (JP, A) JP-A-59-52860 (JP, A) JP-A-2-241046 (JP , A) Actual development Sho 57-132452 (JP, U)
Claims (1)
ッドと、 前記第１の電極パッドよりもパッドサイズの小さい高速
信号用の第２の電極パッドと、 前記第１の電極パッドと前記第２の電極パッドを接続す
る抵抗層と、 前記第２の電極パッドに接続される高速信号用回路と を有することを特徴とする半導体装置。1. A first electrode pad for applying a probe, a second electrode pad for a high speed signal having a smaller pad size than the first electrode pad, the first electrode pad and the A semiconductor device, comprising: a resistance layer connecting the second electrode pad; and a high-speed signal circuit connected to the second electrode pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1172162A JP2680132B2 (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1172162A JP2680132B2 (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0336745A JPH0336745A (en) | 1991-02-18 |
| JP2680132B2 true JP2680132B2 (en) | 1997-11-19 |
Family
ID=15936726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1172162A Expired - Lifetime JP2680132B2 (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2680132B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3318928B2 (en) | 1999-04-12 | 2002-08-26 | 日本電気株式会社 | Semiconductor device |
| DE102007029657B4 (en) * | 2007-06-27 | 2017-10-19 | Fuji Electric Co., Ltd. | Inverter module for power converters |
| JP4711442B2 (en) * | 2007-08-23 | 2011-06-29 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
-
1989
- 1989-07-03 JP JP1172162A patent/JP2680132B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0336745A (en) | 1991-02-18 |
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