JPH0336745A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0336745A JPH0336745A JP1172162A JP17216289A JPH0336745A JP H0336745 A JPH0336745 A JP H0336745A JP 1172162 A JP1172162 A JP 1172162A JP 17216289 A JP17216289 A JP 17216289A JP H0336745 A JPH0336745 A JP H0336745A
- Authority
- JP
- Japan
- Prior art keywords
- electrode pad
- chip
- size
- pad
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000523 sample Substances 0.000 claims abstract description 13
- 230000003071 parasitic effect Effects 0.000 abstract description 16
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 238000007664 blowing Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000011990 functional testing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］
半導体装置に係り、特に高速動作を行なう半導体装置に
関し、
ＩＣチップのブロービング試験を行なうことができると
共に、電極パッドの寄生容量を低減させて高速化を実現
することができる半導体装置を提供することを目的とし
、
探針プローブを当てるための第１の電極パッドと、前記
第１の電極パッドよりもパッドサイズの小さい高速信号
用の第２の電極パッドと、前記第１の電極パッドと前記
第２の電極パッドを接続する抵抗層と、前記第２の電極
パッドに接続される高速信号用回路とを有するように構
成する。[Detailed Description of the Invention] [Summary] Regarding semiconductor devices, especially semiconductor devices that operate at high speed, it is possible to perform a blobbing test on an IC chip, and also achieve high speed by reducing the parasitic capacitance of electrode pads. The purpose of the present invention is to provide a semiconductor device that can be used for high-speed signals, and has a first electrode pad for applying a probe, and a second electrode pad for high-speed signals that is smaller in pad size than the first electrode pad. , a resistance layer connecting the first electrode pad and the second electrode pad, and a high-speed signal circuit connected to the second electrode pad.
［産業上の利用分野］
本発明は半導体装置に係り、特に高速動作を行なう半導
体装置に関する。[Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device that operates at high speed.
［従来の技術］
近年、ＩＣ（半導体集積回路）は高速化の一途を辿って
いる。これに伴って、ＩＣチップ上の電極パッドは、交
流特性を劣化させる一因となる寄生写量を低減するため
、パッドサイズを縮小することが強く要求されている。[Background Art] In recent years, ICs (semiconductor integrated circuits) are becoming faster and faster. Along with this, there is a strong demand for electrode pads on IC chips to be reduced in pad size in order to reduce the amount of parasitic radiation that causes deterioration of AC characteristics.
しかし、従来の半導体装置において、パラゲージのイン
ナーリードと接続されるＩＣチップ上の４Ｓ極パツドの
カバーサイズは、１００μｍ０程度である。これは、ウ
ェーハ状態におけるＩＣチップの電気的試験いわゆるブ
ロービング試験が、電極パッドに試験用の針すなわち探
針プローブを当てて行なわれるためである。However, in conventional semiconductor devices, the cover size of the 4S pole pad on the IC chip connected to the inner lead of the paragauge is about 100 μm. This is because an electrical test of an IC chip in a wafer state, a so-called blobbing test, is performed by applying a test needle, ie, a probe, to an electrode pad.
従って、ＩＣの高速化に伴って電極パッドの縮小化が要
求されても、ブロービング試験において電極パッドに探
針プローブを精度よく当てるのに必要とされる゛バッド
サイズ以下に縮小することは困難であった。Therefore, even if electrode pads are required to be made smaller as IC speeds increase, it is difficult to reduce the pad size to less than the size required to accurately apply a tip probe to an electrode pad in a blowing test. Met.
［発明が解決しようとする課題］
このように、上記従来の半導体装置においては、ウェー
ハ状態におけるＩＣチップの１０−ビング試験を行なう
のに１００μｍ口程度のパブドサイズの電極パッドが必
要とされるため、電極パッドの寄生容量を低減させてＩ
Ｃの高速化を図ることは困難であった。[Problems to be Solved by the Invention] As described above, in the above-mentioned conventional semiconductor device, electrode pads with a pad size of about 100 μm are required to perform a 10-bing test on an IC chip in a wafer state. By reducing the parasitic capacitance of the electrode pad,
It has been difficult to increase the speed of C.
そこで本発明は、ＩＣチップのブロービング試験を行な
うことができると共に、電極パッドの寄生容量を低減さ
せて高速化を実現することができる半導体装置を提供す
ることを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that can perform a broaching test on an IC chip, and can also reduce the parasitic capacitance of an electrode pad and realize high speed operation.
［課題を解決するための手段］ 第１図は、本発明の原理説明図である。[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.
半導体チップ２のチップ端４近傍に、探針プローブを当
てるに十分な大きさのパッドサイズを有する第１の電極
パッド６が配置されている。この第１の電極バッド６は
、抵抗層Ｒを介して、第１の電極パッド６よりもパッド
サイズの小さい高速信号用の第２の電極パッド８に接続
されている。A first electrode pad 6 is arranged near the chip end 4 of the semiconductor chip 2 and has a pad size large enough to be touched by a probe. The first electrode pad 6 is connected via the resistance layer R to a second electrode pad 8 for high-speed signals, which is smaller in pad size than the first electrode pad 6.
そしてこの第２の電極パッド８は、半導体チップ２上に
形成された高速信号用回路のトランジスタＴと接続され
ている。This second electrode pad 8 is connected to a transistor T of a high-speed signal circuit formed on the semiconductor chip 2.
［作 用］
すなわち本発明は、パッドサイズが小さくて寄生容量の
小さい第２の電極パッド８を信号経路とすることにより
、高速信号動作を行なうことができる。このとき、パッ
ドサイズの大きい従って寄生容量の大きい第１の電極バ
ッド６との間に介在する抵抗層Ｒを高抵抗とすれば、こ
の第１の電極バッド６の寄生容量が高速信号経路の交流
特性に影響を及ぼすことはない。[Function] That is, in the present invention, high-speed signal operation can be performed by using the second electrode pad 8, which has a small pad size and a small parasitic capacitance, as a signal path. At this time, if the resistance layer R interposed between the first electrode pad 6, which has a large pad size and therefore has a large parasitic capacitance, has a high resistance, the parasitic capacitance of the first electrode pad 6 is It does not affect the characteristics.
また、パッドサイズの大きい第１の電極バッド６には探
針プローブを容易に当てることができ、ウェーハ状態に
おける半導体チップ２のブロービング試験を安定的に行
なうことができる。このとき、ブロービング試験には低
周波又は直流の試験用信号が用いられるため、抵抗層Ｒ
が高抵抗であり、その高抵抗の抵抗層Ｒを介してトラン
ジスタＴに試験用信号を入力しても、半導体チップ２の
機能試験に支障が生じることはない。Furthermore, the probe can be easily applied to the first electrode pad 6 having a large pad size, and a broaching test of the semiconductor chip 2 in a wafer state can be stably performed. At this time, since a low frequency or DC test signal is used in the broaching test, the resistance layer R
has a high resistance, and even if a test signal is input to the transistor T through the high resistance resistance layer R, there will be no problem in the functional test of the semiconductor chip 2.
［実施例コ
以下、本発明を図示する実施例に基づいて具体的に説明
する。[Example] Hereinafter, the present invention will be specifically explained based on an illustrative example.
第２図（ａ）は、本発明の第１の実施例による半導体装
置を示す平面図である。FIG. 2(a) is a plan view showing a semiconductor device according to a first embodiment of the present invention.
ＩＣチップ上２のチップ端１４近傍に、カバーサイズ１
００μｍ口程度の試験用の電極パッド１６及び低速信号
用の電極パッド１８と、カバ−サイズ２５μｍ０程度の
高速信号用の電極パッド２０とがそれぞれ配置されてい
る。そして試験用の電極パッド１６と高速信号用の電極
パッド２０とは、例えば３０にΩ以上の高抵抗値の抵抗
層Ｒ１を介して接続されている。なお、この抵抗層Ｒ１
は、例えば不純物拡散によって形成してもよいし、また
ポリシリコン層等を用いて形成してもよい。Cover size 1 is placed near the chip end 14 on IC chip 2.
An electrode pad 16 for testing and an electrode pad 18 for low-speed signals with a cover size of about 25 μm and an electrode pad 20 for high-speed signals with a cover size of about 25 μm are respectively arranged. The test electrode pad 16 and the high-speed signal electrode pad 20 are connected to, for example, 30 via a resistance layer R1 having a high resistance value of Ω or more. Note that this resistance layer R1
may be formed, for example, by impurity diffusion, or may be formed using a polysilicon layer or the like.
また、低速信号用の電極バッド１８及び高速信号用のｔ
ｉパッド２０は、ＩＣチップ１２上に形成されたトラン
ジスタＴＩ、Ｔ２にそれぞれ接続されている。In addition, electrode pad 18 for low-speed signals and t for high-speed signals are also provided.
The i-pad 20 is connected to transistors TI and T2 formed on the IC chip 12, respectively.
次いで、第２図（ａ）に示されるように配置され接続さ
れた電極バッド１６．１８．２０を有するＩＣ回路の一
例として、Ｅ ＣＬ （Ｅｌ′１ｉｔｔｅｒ Ｃｏｕｐ
ｌｅｄ Ｌｏｇｉｃ ）回路を第２図（ｂ）ニ示ス。Next, as an example of an IC circuit having electrode pads 16, 18, and 20 arranged and connected as shown in FIG.
The LED Logic circuit is shown in Figure 2(b).
トランジスタＴＩ、Ｔ２のコレクタＣ１，Ｃ２は、それ
ぞれ抵抗Ｒｃｌ、Ｒｃ２を介して、接地されたコレクタ
電源ＶＣＣに接続されている。またエミッタＥｌ、Ｅ２
は、定電流源２２を介して、一般に一５Ｖ程度の負の電
圧を有する電源Ｖａｔに接続されている。そしてトラン
ジスタＴ１のベースＢ１は、基準電圧Ｖｌｌｌｌが印加
される入力端子、即ち低速信号用の電極パッド１８に接
続され、またトランジスタＴ２のベースＢ２は、入力電
圧ＶＩＮが印加される入力端子、即ち高速信号用の電極
パッド２０に接続されている。Collectors C1 and C2 of transistors TI and T2 are connected to a grounded collector power supply VCC via resistors Rcl and Rc2, respectively. Also emitters El, E2
is connected via a constant current source 22 to a power supply Vat, which generally has a negative voltage of about -5V. The base B1 of the transistor T1 is connected to the input terminal to which the reference voltage Vllll is applied, that is, the electrode pad 18 for low-speed signals, and the base B2 of the transistor T2 is connected to the input terminal to which the input voltage VIN is applied, that is, the electrode pad 18 for low-speed signals. It is connected to a signal electrode pad 20.
そしてさらに、負荷の駆動能力を向上させるために、エ
ミッタホロワ回路が付加されている。Furthermore, an emitter follower circuit is added to improve the load driving ability.
すなわち、トランジスタＴＩ、Ｔ２のコレクタ電位が、
それぞれトランジスタＴ３．Ｔ４のベースに接続されて
いる。また、トランジスタＴ３゜Ｔ４のコレクタはそれ
ぞれ接地された電源Ｖｃｃに接続され、またエミッタは
、それぞれ定電流源２４．２６を介して、負の電圧を有
する電源ＶＩＫに接続されている。そしてトランジスタ
Ｔ３．Ｔ４のエミッタ電位が、それぞれ出力ＶＯＬＩ丁
１ 、 ＶｏｕＴ２に接続されている。That is, the collector potential of transistors TI and T2 is
Transistor T3. Connected to the base of T4. Further, the collectors of the transistors T3 and T4 are each connected to a grounded power supply Vcc, and the emitters are respectively connected to a power supply VIK having a negative voltage via constant current sources 24 and 26. and transistor T3. The emitter potential of T4 is connected to the outputs VOLI-1 and VouT2, respectively.
次いで、第２図に示された半導体装置のプロービング試
験について述べる。Next, a probing test of the semiconductor device shown in FIG. 2 will be described.
半導体装置のブロービング試験は、ウェーハ状態におい
て、ＩＣチップ１２上の試験用の電極バッド１６及び低
速信号用の電極バッド１８に探針プローブを当てて行な
う、このとき、電極パッド１６．１８のチップサイズは
１００μｍＯ程度であるため、３０μｍφ程度の太さの
探針１０−プであっても十分に精度よく当てることがで
きる。A blowing test of a semiconductor device is performed in a wafer state by applying a probe to the test electrode pad 16 and low-speed signal electrode pad 18 on the IC chip 12. At this time, the tip of the electrode pad 16. Since the size is about 100 .mu.mO, even a probe 10 having a thickness of about 30 .mu.m.phi. can be applied with sufficient precision.
また、試験用信号は探針プローブを通って電極パッド１
６に入力され、３０にΩ以上の高抵抗値の抵抗層Ｒ１を
経由してトランジスタＴ２に伝搬されるが、このときの
試験用信号には低周波信号又は直流信号が用いられるた
め、ＩＣチップ１２の論理チエツク等の機能試験には何
等の支障ら生じない。In addition, the test signal passes through the probe to the electrode pad 1.
6 and is propagated to the transistor T2 via the resistance layer R1 with a high resistance value of 30Ω or more, but since the test signal at this time is a low frequency signal or a DC signal, the IC chip There is no problem with functional tests such as 12 logic checks.
次いで、組立後の半導体装置の動作について、第３図を
用いて述べる。Next, the operation of the semiconductor device after assembly will be described using FIG.
第２図（ａ）に示されたＩＣチップ１２がパッケージ３
０上に搭載されている。そしてＩＣチップ１２のチップ
端１４近傍の低速信号用の電極バッド１８が、パッケー
ジ３０に配置され基準電圧ＶＢｌｌが印加されるインナ
ーリード３２とボンディングワイヤ３３によって接続さ
れている。同様にして、高速信号用の電極バッド２０が
、パッケージ３０に配置され入力電圧ＶＩＮが印加され
るインナーリード３４とボンディングワイヤ３５によっ
て接続されている。The IC chip 12 shown in FIG. 2(a) is packaged in a package 3.
It is installed on 0. An electrode pad 18 for low-speed signals near the chip end 14 of the IC chip 12 is connected by a bonding wire 33 to an inner lead 32 arranged in the package 30 and to which a reference voltage VBll is applied. Similarly, the electrode pad 20 for high-speed signals is connected by a bonding wire 35 to an inner lead 34 arranged in the package 30 and to which the input voltage VIN is applied.
このとき、高速信号用の電極パッド２０のチップサイズ
は２５μｍ口程度太めって、探針プローブを当てるには
小さいが、ワイヤボンディングの可能な大きさである。At this time, the chip size of the electrode pad 20 for high-speed signals is about 25 μm thick, which is too small to be touched by a tip probe, but large enough to allow wire bonding.
なお、試験用の電極バ・ｙド１６は、オープンになって
いる。Note that the electrode bar 16 for testing is open.
このような半導体装置は、入力信号ＶＩＮの信号経路と
なる高速信号用の電極パッド２０のパッドサイズが２５
μｍ口程度太め来の１／４程度に縮小され、従って寄生
容量が小さくなでいるために、高速信号動作を行なうこ
とができる。このとき、パッドサイズが１００μｍ口程
度と太さく寄生容量の大きい試験用の電極パッド１６と
高速信号用の電極パッド２０との間には、３０にΩ以上
の高抵抗値を有する抵抗層Ｒ１が介在しているために、
この試験用の電極パッド１６の寄生容量が高速信号経路
の交流特性に影響を及ぼすことはない。In such a semiconductor device, the pad size of the electrode pad 20 for high-speed signals serving as the signal path of the input signal VIN is 25.
Since it is reduced to about 1/4 of the diameter of the thicker one, about .mu.m, and the parasitic capacitance is kept small, high-speed signal operation can be performed. At this time, a resistance layer R1 having a high resistance value of 30Ω or more is placed between the test electrode pad 16, which has a thick pad size of about 100 μm and a large parasitic capacitance, and the high-speed signal electrode pad 20. Because of the intervention,
This parasitic capacitance of the test electrode pad 16 does not affect the AC characteristics of the high-speed signal path.
このように第１の実施例によれば、一方において、パッ
ドサイズの大きい試験用の電極パッド１６を用いること
により、ウェーハ状態におけるＩＣチップ１２の１０−
ビング試験を安定的に行なうことができる。また他方に
おいて、パッドサイズの小さい、従って寄生容量の小さ
い高速信号用の電極パッド２０を信号経路とすることに
より、高速信号動作を行なうことができる。As described above, according to the first embodiment, on the one hand, by using the test electrode pad 16 having a large pad size, it is possible to
Bing tests can be performed stably. On the other hand, high-speed signal operation can be performed by using the electrode pad 20 for high-speed signals, which is small in pad size and therefore has small parasitic capacitance, as a signal path.
次に、第４図を用いて、本発明の第２の実施例による半
導体装置を説明する。Next, a semiconductor device according to a second embodiment of the present invention will be explained using FIG.
第４図（ａ）において、第２図（ａ）に示されたＩＣチ
ップ１２がパッケージ３０上に搭載されている。そして
ＩＣチップ１２のチップ端１４近傍の低速信号用の電極
パッド１８及び高速信号用の電極パッド２０が、それぞ
れパッケージ３０に配置され、入力電圧ＶＩＮが印加さ
れるインナーリード３２及び基準電圧ＶＢＢが印加され
るインナーリード３４とボンディングワイヤ３５によっ
て接続されている。さらに試験用の電極バッド１６が、
パッケージ３０に配置され、最も低い（ｌｏｓｔ ｎｅ
ｇａｔｉｖｅ ）電源ＶｇＩ＋が印加されるインナーリ
ード３６とボンディングワイヤ３７によって接続されて
いる。In FIG. 4(a), the IC chip 12 shown in FIG. 2(a) is mounted on a package 30. In FIG. Electrode pads 18 for low-speed signals and electrode pads 20 for high-speed signals near the chip end 14 of the IC chip 12 are arranged in a package 30, respectively, and inner leads 32 to which input voltage VIN is applied and reference voltage VBB are applied. The inner leads 34 and the bonding wires 35 are connected to each other. Furthermore, the electrode pad 16 for testing is
placed in the package 30 and the lowest (lost ne
Gative) It is connected by a bonding wire 37 to an inner lead 36 to which a power supply VgI+ is applied.
この第４図（ａ）に示される半導体装置の回路の一例を
第４図（ｂ）に示す。An example of the circuit of the semiconductor device shown in FIG. 4(a) is shown in FIG. 4(b).
この回路は、第２図（ｂ）に示されたＥＣＬ回路におい
て、入力電圧ＶＩＮが印加される入力端子即ち高速信号
用の′ｒ４極パッド２０が、抵抗Ｒ１を介して、電源Ｖ
、に接続されているものである。This circuit is similar to the ECL circuit shown in FIG.
, which is connected to.
次いで、動作を述べると、試験用の電極バッド１６と高
速信号用の電極パッド２０とを接続している３０にΩ以
上の高抵抗値を有する抵抗層Ｒ１は電源Ｖ、に接続され
ることにより、高速信号用の電極パッド２０に入力され
る入力信号■、の雑音防止用のプル・ダウン（ｐｕｌｌ
−ｄｏｗｎ ）抵抗として働く。Next, to describe the operation, the resistance layer R1 having a high resistance value of Ω or more is connected to the power supply V at 30 which connects the test electrode pad 16 and the high-speed signal electrode pad 20. , a pull-down (pull-down) for noise prevention of the input signal inputted to the electrode pad 20 for high-speed signals.
-down) acts as a resistance.
このように第２の実施例によれば、一方においてウェー
ハ状態におけるＩＣチップ１２のブロービング試験を安
定的に行なうことができるようにし、また他方において
高速信号動作を行なうことができるようにするために設
けた抵抗層Ｒ１を、入力雑音防止用のプル・ダウン（ｐ
ｕｌｌ−ｄｏｗｎ ）抵抗として用いることができる。As described above, according to the second embodiment, on the one hand, it is possible to stably perform a blobbing test on the IC chip 12 in the wafer state, and on the other hand, it is possible to perform high-speed signal operation. The resistance layer R1 provided in the
(Ull-down) can be used as a resistor.
また、試験用の電極バッド１６が最も低いエミッタ電源
Ｖ□に接続されるため、試験用の電極バッド１６の寄生
容量が高速信号経路の交流特性に及ぼす影響は完全に遮
断される。Furthermore, since the test electrode pad 16 is connected to the lowest emitter power supply V□, the influence of the parasitic capacitance of the test electrode pad 16 on the AC characteristics of the high-speed signal path is completely blocked.
次に、第５図を用いて、本発明の第３の実施例による半
導体装置を説明する。Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.
第５図（ａ）に示されるＩＣチップ４２は、第２図（ａ
）に示されたＩＣチップ１２において試験用のｘｉバッ
ド１６と高速信号用の電極パッド２０とを接続している
３０にΩ以上の高抵抗値の抵抗層Ｒ１の代わりに、抵抗
値５０Ω程度の抵抗層Ｒ２が設けられている。The IC chip 42 shown in FIG. 5(a) is similar to the IC chip 42 shown in FIG.
) In the IC chip 12 shown in ), instead of the resistance layer R1 having a high resistance value of Ω or more, a resistor layer R1 having a resistance value of about 50Ω is connected to the 30 connecting the xi pad 16 for testing and the electrode pad 20 for high-speed signals. A resistive layer R2 is provided.
そしてこのＩＣチップ４２がパッケージ３０上に搭載さ
れている。また、ＩＣチップ４２のチップ端４４近傍の
低速信号用の電極パッド１８は、基準電圧Ｖ。が印加さ
れるインナーリード３２に接続されている。同様にして
、高速信号用の電極バッド２°Ｏは、パッケージ３０に
配置されているインナーリード３４を介して、入力電圧
ＶＩＮが印加される伝送路Ｚｏに接続されている。This IC chip 42 is mounted on the package 30. Further, the electrode pad 18 for low-speed signals near the chip end 44 of the IC chip 42 has a reference voltage V. is connected to the inner lead 32 to which is applied. Similarly, the high-speed signal electrode pad 2°O is connected via an inner lead 34 arranged in the package 30 to the transmission line Zo to which the input voltage VIN is applied.
さらに試験用の電極バッド１６は、一般に一２Ｖ程度の
終端電圧ＶＴが印加されるインナーリード３６に接続さ
れている。Further, the test electrode pad 16 is connected to an inner lead 36 to which a termination voltage VT of about -2V is generally applied.
この第５図（ａ）に示される半導体装置の回路の一例を
第５図（ｂ）に示す。An example of the circuit of the semiconductor device shown in FIG. 5(a) is shown in FIG. 5(b).
この回路は、第２図（ｂ）に示されたＥＣＬ回路におい
て、入力電圧ＶＩＮが印加される入力端子即ち高速信号
用の電極パッド２０が、抵抗Ｒ２を介して、終端電圧Ｖ
Ｔに接続されているものである。In this circuit, in the ECL circuit shown in FIG. 2(b), the input terminal to which the input voltage VIN is applied, that is, the electrode pad 20 for high-speed signals, is connected to the terminal voltage VIN via the resistor R2.
It is connected to T.
次いで、動作を述べると、試験用の電極バッド１６と高
速信号用の電極パッド２０とを接続している抵抗値５０
Ω程度の抵抗層Ｒ２は、終端電圧■７に接続されること
により、高速信号用の電極パッド２０に入力される入力
信号■、の終端抵抗として働く。Next, to describe the operation, the resistance value 50 connecting the test electrode pad 16 and the high-speed signal electrode pad 20 is
The resistance layer R2 of approximately Ω is connected to the termination voltage (7), and thereby functions as a termination resistance for the input signal (2) inputted to the electrode pad 20 for high-speed signals.
このように第３の実施例によれば、一方においてウェー
ハ状態におけるＩＣチップ１２のブロービング試験を安
定的に行なうことができるようにし、また他方において
高速信号経路を行なうことができるようにするために設
けた抵抗７１Ｒ２を、ＩＣチップ内部終端抵抗として用
いることができる。このようなＩＣチップ内部終端抵抗
は、インピーダンスのマツチングによって高周波動作に
極めて有効である。従って、半導体装置の高性能化を図
ることができる。As described above, according to the third embodiment, on the one hand, it is possible to stably perform a blobbing test on the IC chip 12 in the wafer state, and on the other hand, it is possible to perform a high-speed signal path. The resistor 71R2 provided in the IC chip can be used as an internal termination resistor of the IC chip. Such an IC chip internal termination resistor is extremely effective for high frequency operation due to impedance matching. Therefore, it is possible to improve the performance of the semiconductor device.
なお、第３の実施例においては抵抗層Ｒ２が５０Ω程度
であるため、試験用の電極バッド１６をオープンにして
おくと試験用の電極バッド１６の寄生容量が高速信号経
路の交流特性の劣化を招くおそれがあるが、実際の使用
においては試験用の電極パッド１６が終端電圧■７に接
続されるため、このおそれは解消される。In the third embodiment, the resistance layer R2 is approximately 50Ω, so if the test electrode pad 16 is left open, the parasitic capacitance of the test electrode pad 16 will cause deterioration of the AC characteristics of the high-speed signal path. However, in actual use, since the test electrode pad 16 is connected to the termination voltage (7), this fear is eliminated.
［発明の効果］
以上のように本発明によれば、探針プローブを当てるに
十分な大きさのパッドサイズを有する第１の電極パッド
と第１の電極パッドよりもパッドサイズの小さい高速信
号用の第２の電極パッドとを抵抗層を介して設けること
により、第１の電極パッドを用いてブロービング試験を
行なうことができると共に、パッドサイズが小さく寄生
容量の小さい第２の電極パッドを信号経路として高速信
号動作を実現することができる。[Effects of the Invention] As described above, according to the present invention, the first electrode pad has a pad size large enough to be hit by a probe, and the high-speed signal pad has a pad size smaller than the first electrode pad. By providing a second electrode pad with a resistance layer in between, it is possible to perform a blobbing test using the first electrode pad, and the second electrode pad, which is small in size and has low parasitic capacitance, can be used as a signal. As a route, high-speed signal operation can be realized.
第１図は本発明の原理説明図、
第２図及び第３図は本発明の第１の実８１例による半導
体装置を示す図、
第４図は本発明の第２の実施例による半導体装置を示す
図、
第５図は本発明の第３の実施例による半導体装置を示す
図である。
図において、
２・・・半導体チップ
４．１４．４４・・・チップ端
６．８．１６．１８．２０・・・電極パッド１２．４２
・・・ＩＣチップ
２２．２４．２６・・・定電流源
３０・・・バヅゲージ
３２．３４．３６・・・インナーリード３３．３５．３
７・・・ボンディングワイヤＲ，Ｒ１、Ｒ２、Ｒｃｌ、
Ｒｃ２・・・抵抗Ｔ、ＴＩ、Ｔ２、Ｔ３、Ｔ４・・・ト
ランジスタＣ１、Ｃ２・・・コレクタ
Ｅｌ、Ｂ２・・・エミッタ
Ｂ１、Ｂ２・・・ベース
Ｖ ｃｃ・＝ を源（ＨＯ３Ｔ ＰＯ８ＩＴＩＶＥ）■
□・・・電源（ＨＯ３Ｔ ＮＥＧＡＴＩＶＥ）Ｖｌｌｌ
・・基準電圧
ＶＩＮ・・・入力電圧
Ｖ ＯＬ＋Ｔ １ 、Ｖ ０ＩＪＴ
Ｚｏ・・・伝送路
ＶＴ・・・終端電圧
２・・・出力
＼、−一FIG. 1 is a diagram illustrating the principle of the present invention. FIGS. 2 and 3 are diagrams showing a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a semiconductor device according to a second embodiment of the present invention. FIG. 5 is a diagram showing a semiconductor device according to a third embodiment of the present invention. In the figure, 2...Semiconductor chip 4.14.44...Chip end 6.8.16.18.20...Electrode pad 12.42
...IC chip 22.24.26...constant current source 30...bud gauge 32.34.36...inner lead 33.35.3
7... Bonding wires R, R1, R2, Rcl,
Rc2...Resistor T, TI, T2, T3, T4...Transistor C1, C2...Collector El, B2...Emitter B1, B2...Base V cc・= Source (HO3T PO8ITIVE)■
□・・・Power supply (HO3T NEGATIVE) Vllll
...Reference voltage VIN...Input voltage VOL+T1, V0IJT Zo...Transmission line VT...Terminal voltage 2...Output\, -1
Claims (1)
信号用の第２の電極パッドと、 前記第１の電極パッドと前記第２の電極パッドを接続す
る抵抗層と、 前記第２の電極パッドに接続される高速信号用回路と を有することを特徴とする半導体装置。[Claims] A first electrode pad to which a probe is applied; a second electrode pad for high-speed signals that is smaller in pad size than the first electrode pad; and the first electrode pad. A semiconductor device comprising: a resistance layer connecting the second electrode pad; and a high-speed signal circuit connected to the second electrode pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1172162A JP2680132B2 (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1172162A JP2680132B2 (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0336745A true JPH0336745A (en) | 1991-02-18 |
| JP2680132B2 JP2680132B2 (en) | 1997-11-19 |
Family
ID=15936726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1172162A Expired - Lifetime JP2680132B2 (en) | 1989-07-03 | 1989-07-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2680132B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465850B1 (en) | 1999-04-12 | 2002-10-15 | Nec Corporation | Semiconductor device |
| JP2008011561A (en) * | 2007-08-23 | 2008-01-17 | Renesas Technology Corp | Semiconductor integrated circuit device |
| DE102007029657B4 (en) * | 2007-06-27 | 2017-10-19 | Fuji Electric Co., Ltd. | Inverter module for power converters |
-
1989
- 1989-07-03 JP JP1172162A patent/JP2680132B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465850B1 (en) | 1999-04-12 | 2002-10-15 | Nec Corporation | Semiconductor device |
| DE102007029657B4 (en) * | 2007-06-27 | 2017-10-19 | Fuji Electric Co., Ltd. | Inverter module for power converters |
| JP2008011561A (en) * | 2007-08-23 | 2008-01-17 | Renesas Technology Corp | Semiconductor integrated circuit device |
| JP4711442B2 (en) * | 2007-08-23 | 2011-06-29 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2680132B2 (en) | 1997-11-19 |
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