JPH08328857A - Microprocessor - Google Patents

Abstract

PURPOSE: To provide a microprocessor which can prevent reduction of the program execution speed that is caused by an instruction look-ahead operation when a branch instruction exists at a page boundary and also the branching destination is included in a pulse. CONSTITUTION: A microprocessor 1 consists of an instruction prereading device 2, an instruction decoder 3, an instruction execution unit 4 and a memory management unit 5. The device 2 has a function to decide whether a branch instruction exists at a page boundary and a function to stop the instruction look-ahead operation. If the branch instruction exists at the page boundary, the instruction look-ahead operation of the device 2 is discontinued until the branching destination of the branch instruction is decided. When the branching destination is decided, the look-ahead operation is started again through the branching destination address. Thus it is possible to prevent reduction of the program execution speed that is caused by a page fault.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor having a virtual memory function.

[0002]

2. Description of the Related Art A conventional instruction prefetching method or instruction prefetching method used in a microprocessor having such a virtual memory function or a microprocessor having no virtual memory function is disclosed in, for example, JP-A-63-
No. 254532, "Address conversion method of central processing unit", JP-A-60-51947, "Instruction prefetching method in virtual memory computer", and JP-A-64-5943.
It is disclosed in Japanese Laid-Open Patent Publication No. 2 “Instruction Preemption Method”. In the following, the main points of these conventional examples will be described.

FIG. 9 is a block diagram showing the configuration of an example of a conventional microprocessor. In FIG. 9, the microprocessor 21 includes an instruction prefetching device 22, an instruction decoder 3, an instruction execution unit 4, and a memory management unit 23, and a branch address output from the instruction execution unit 4. The signal 101 and the branch destination address confirmation signal 102 are connected to the instruction prefetching device 22, and the instruction prefetching device 22 is connected to the instruction decoder 3 via the instruction queue data bus 103 and the instruction output from the instruction decoder 3. The decode signal 104 is connected to the instruction execution unit 4. Further, the command prefetch address signal 108 output from the command prefetch device 22.
Are connected to an internal address bus 110, and are connected to an internal data bus 109 via a command prefetch data bus 106. Further, the instruction execution unit 4 is connected to the internal data bus 109 via the operand data bus 113 and is connected to the internal address bus 110 via the operand address bus 114. The memory management unit 23 is connected to the internal data bus 109 via the data bus 111 and also connected to the internal address bus 110 via the virtual address bus 112, and is output from the memory management unit 23. The page fall signal 105 is sent to the instruction execution unit 4, and the real address signal 116 that is also output is output to the outside of the microprocessor 21.

The internal configuration of the instruction prefetching device 22 in this conventional example is as shown in FIG. 10, in which a program counter 6, a kun counter 8 and an address adder 9 are provided.
And an instruction queue buffer 10. Branch address signal 1 from the program counter 6
Upon receiving the input 01, the execution address signal 118 is output and input to the address adder 9. Queue counter 8
The queue count signal 119 output from the instruction queue buffer 10 is input to the address adder 9 and
Is input to The address adder 9 receives the execution address signal 118 and the queue count signal 119, and outputs the addition output of these two signals as the instruction prefetch address signal 108. The instruction queue buffer 10 is connected to the instruction queue data bus 103 and the instruction prefetch data bus 106, and receives a branch destination address confirmation signal 102 from the outside and the queue count signal 1 described above.
19 has been entered.

The internal structure of the memory management unit 23 is shown in FIG. In FIG. 11, the memory management unit 23 includes an address conversion buffer 14 and an address comparator 15, and the address conversion buffer 14 is connected to a data bus 111 and a virtual address bus 112. , Address conversion data signal 121 and real address signal 116 are output. Further, the address comparator 15 has a virtual address bus 1
12 is connected and the address conversion data signal 1
21 is input and the page fault signal 105 is output.

FIG. 12 is a diagram showing a virtual memory system using a hard disk corresponding to the microprocessor 21 capable of virtual storage. The real address signal 116 output from the microprocessor 21 is input to the real memory 24, the real memory 24 and the microprocessor 21 are connected via the data bus 115, and the bird disk 25 is also connected to the data bus 115. It is connected.

Next, the operation of executing a program using the instruction prefetching device 22 in the conventional example will be described. When starting the execution of the microprocessor 21 from a certain address, the execution start address is set in the program counter 6 of the instruction prefetching device 26, and the address value is output as the execution address signal 118 and the address adder is added. 9 is input. The queue counter 8 is incremented every bus cycle, and the queue count signal 119 is output and input to the address adder 9. In the address adder 9, the execution address signal 118 and the queue count signal 119 are added, and the instruction prefetch address signal 10 is added.
8 is generated and output, and is input to the memory management unit 23 as a virtual address via the internal address bus 110 and the virtual address bus 112.

In the memory management unit 23, it is checked whether the given virtual address is loaded inside the real memory 24 (see FIG. 12).
The address translation buffer 14 contains address information of the memory loaded in the real memory 24 at the present time.
As shown in FIG. 11, it is composed of a pair of entries of part (a) and part (b). In one entry, the value of the virtual address is recorded in the portion (a), and where in the real memory 24 the area corresponding to the portion (a) is recorded in the portion (b). There is. This means that "the virtual address is the address translation buffer 14
Registered in. Virtual address bus 1
Reference numeral 12 is connected to the portion (a) of the address conversion buffer 14 and the address comparator 15, and the address comparator 1
In 5, the virtual address input via the virtual address bus 112 and the address translation data signal 121 of all the entries of the address translation buffer 14 are compared and collated. If the given virtual memory is registered in the real memory 24, it means that the required memory is loaded on the real memory, and the memory of the virtual address is stored. The stored data is output as the real address signal 116 and input to the real memory 24. If the required virtual memory is not registered in the real memory 24, the page fault signal 105 is output from the address comparator 15 and input to the instruction execution unit 4 in the microprocessor 21. To be done.

In the instruction execution unit 4, when the page fault signal 105 is generated and input, the real memory of the required area is loaded from the hard disk 25 (see FIG. 12) into the main memory, and the operand data bus is loaded. An operation for updating the content of the entry of the address translation buffer 14 is executed via 113, internal data bus 109 and data bus 111, and operand address bus 114, internal address bus 110 and virtual address bus 112. The operation of exchanging the virtual address given to the memory management unit 23 between the real memory 24 and the hard disk 25 because the virtual address is not registered in the address translation buffer 14 is called "page swap". Then, at the time of prefetching the instruction, the instruction prefetching device 2
When the virtual address given to the memory management unit 23 from 2 exists in the real memory 24, the data of the address is stored in the data bus 115 and the internal data bus 10.
9 and the instruction prefetch data bus 106 to be input and held in the instruction queue buffer 10.

Instructions to be read every bus cycle are sequentially input to and held in the instruction queue buffer 10, and the instruction queue data bus 10 is sequentially loaded in the order in which they are held.
3 to the instruction decoder 3. In the instruction decoder 3, the type of the instruction is classified, the instruction decode signal 104 is output, and the instruction execution method is instructed to the instruction execution unit 4 through the instruction decode signal 104. In the instruction execution unit 4, the instruction is executed according to the decoding result of the instruction decoder 3. When the instruction to be executed is a branch instruction, the branch destination address is sent to the instruction prefetching device 22 by the branch destination address signal 101. As a result, the value of the program counter 6 in the instruction prefetching device 22 is changed, and the program branches. When a program branch occurs due to this branch instruction, it becomes necessary to reject the instruction inside the instruction queue buffer 10 that holds the instruction that has been prefetched by the instruction prefetching device 22 until then, and the instruction execution unit 4 branches from the instruction execution unit 4. The destination address confirmation signal 102 is output and input to the instruction prefetching device 22. In the instruction read-ahead device 22, the branch destination address determination signal 102 is input to the instruction queue buffer 10, and the instruction queue buffer 10 is cleared thereby.

The memory management unit 23 manages the real memory 24 in banks called "pages" in units of several kbytes, and the page swap operation only occurs in units of pages. The execution address of the program is indicated by the program counter 6, and its value is the same as the instruction prefetch address output at the time of prefetching the instruction or a value + α delayed by the number of stages of the instruction queue buffer 10. .

On the other hand, FIG. 13 shows an example of the structure of an instruction prefetching device in the case of a microcomputer (not shown) for branch prediction. 13, the instruction prefetching device 26 includes a program counter 6, a queue counter 8, an address adder 9, and an instruction queue buffer 1.
0, a branch history buffer 27, a comparator 28, and address switches 29 and 30.
Compared with the conventional example in which the branch instruction does not occur, there is a difference in that a branch history buffer 27, a comparator 28, and address switches 29 and 30 are newly added.
In the case of the instruction prefetching device 26, the operations of the program counter 6, the queue counter 8 and the address adder 9 are the same as the instruction prefetching device 2 shown in FIG.
The same as in the case of 2, but in the case of this microcomputer, the instruction prefetch address output from the address adder 9 every time the data of the read instruction is output to the instruction prefetch data bus 106. The signal is input to the branch address location portion of the branch history buffer 27, the branch instruction code input via the instruction prefetch data bus 106 is input to the branch instruction code portion of the branch history buffer 27, and the branch destination address signal 101
Is input to the branch destination address part of the branch history buffer 27. Whether or not the instruction data input via the instruction prefetch data bus 106 is the previously executed branch instruction is determined by the data output from the branch address location section and the branch instruction code section of the branch history buffer 27. When the instruction data is compared and collated in the comparator 28 and the instruction data is a previously executed branch instruction,
The coincidence signal 125 is output from the comparator 28 and input to the address switch 30. In the address switch 30, in response to the input of the coincidence signal 125, the branch destination address signal 124 output from the branch destination address portion of the branch history buffer 27 is output as the branch destination address signal 126 and transferred to the address switch 29. To be done. The address switch 29 receives the branch destination address signal 126 and performs a switching operation to switch the instruction prefetch address signal 108 to the branch destination address signal 126. As a result, in this conventional example, when the branch destination address of the branch instruction is deviated, the instruction prefetch buffer is cleared and the function of fetching the instruction again from the deviated address is also required.

[0013]

In the above-mentioned instruction prefetching method in the microprocessor, when the microprocessor executes the instruction, several instructions ahead of the instruction currently being executed are always prefetched, and the branch instruction. Exists within a page boundary and the branch destination of the branch instruction is within the current page, the branch destination is unknown when the instruction is prefetched. The address instruction, that is, the instruction to cross the page is also unconditionally read. When such page crossing occurs and the address is not registered in the address translation buffer, a page fault occurs in the memory management unit, and a data transfer cycle between the real memory and the hard disk occurs. It will be activated. Generally, since the page fault cycle takes a long time, the branch destination of the branch instruction is determined during this page fault cycle, and the instruction prefetch means tries to read the instruction at the branch destination address. However, since the memory management unit is in the page fault operation state, it is impossible to prefetch the branch destination address. If the branch destination is an address outside the page,
This page fault cycle is necessary, but if the branch destination is an address stored in the address translation buffer, this page fault cycle is a wasteful cycle. As an example, in the case of an average hard disk, 1
Although it takes about 0 milliseconds, the time taken for the prefetched branch instruction to be decoded and the branch destination address to be determined is 1 microsecond or less. That is, in the instruction prefetching method in the conventional microprocessor, the branch instruction exists at the page boundary, and if the branch destination of the branch instruction exists in the current page, the execution speed of the program decreases. There is.

Further, after the branch destination address of the branch instruction is determined, the instruction prefetch means is in a state of reading the instruction, but the instruction execution unit and the memory management unit concentrate on the page swap operation. Since the instruction prefetching means is in a state in which it is in a state in which it is forced to wait until this operation is completed. This is a problem in the conventional instruction prefetching method. On the other hand, in the case of a microcomputer adopting the branch prediction method, it is possible to predict where to branch the branch instruction at the time of prefetching the branch instruction, and there is a branch instruction at the page boundary. If the branch destination exists in the page, the probability of unnecessary page fault cycles is low, but a branch history buffer for branch prediction and an enormous circuit for controlling the branch history buffer are required. However, there are drawbacks such as an increase in cost due to an increase in chip area and a decrease in reliability due to a complicated circuit.

An object of the present invention is that when a branch instruction exists within a page boundary and the branch destination is within a page, there is no need for an enormous circuit configuration and there is no need for an instruction prefetch operation. Another object of the present invention is to provide a microprocessor equipped with an instruction pre-reading means capable of preventing the program execution speed from being lowered due to various page fault cycles.

[0016]

The microprocessor of the first invention includes at least instruction prefetch means, an instruction decoder, an instruction execution unit and a memory management unit,
In the microprocessor having a virtual memory management mechanism, the instruction prefetch means receives a branch destination address signal output from the instruction execution unit and outputs an instruction execution address signal corresponding to the branch destination address signal. Corresponding to the presence of a branch instruction on a predetermined instruction prefetch data bus by receiving a counter, a branch destination address determination signal output from the instruction execution unit, and a page boundary signal output from the memory management unit A branch instruction discriminator that outputs a predetermined level instruction prefetch stop signal and an operation function that outputs a predetermined queue count signal that is incremented for each bus cycle. A queue counter whose operation functions are controlled, and the instruction execution address signal and And the queue count signal are input and added, and an operation function of outputting an instruction prefetch address signal corresponding to the instruction prefetch operation to the memory management unit is provided, and the operation is performed by the instruction prefetch stop signal of the predetermined level. Address adders whose functions are controlled, and branch instructions on the instruction prefetch data bus are sequentially held in correspondence with the input states of the branch destination address confirmation signal and the queue count signal, and the branch instructions are successively output by the instruction. An instruction queue buffer for outputting to a decoder is provided at least, and the memory management unit inputs a data signal input via a predetermined data bus and a virtual address signal input via a predetermined virtual address bus. Then, the real address signal is output corresponding to the previous data signal, and the virtual address is output. Address conversion buffer that outputs an address conversion data signal corresponding to a signal, a data signal input via the data bus and the address conversion data signal are input, and both signals are compared and collated to An address comparator that outputs a page fault signal as a comparison result and sends it to the instruction execution unit, and an actual address signal output from the address translation buffer are input, and the page boundary signal is generated and output. It is characterized by comprising at least a page boundary discriminator.

The microprocessor of the second invention includes at least an instruction pre-reading means, an instruction decoder, an instruction execution unit and a memory management unit, and in the microprocessor having a virtual memory management mechanism, the instruction pre-reading means has the instructions. A program counter that receives an input of a branch destination address signal output from the execution unit and outputs an instruction execution address signal corresponding to the branch destination address signal, and a predetermined queue count signal that is incremented every bus cycle A queue counter, an address adder that inputs and adds the instruction execution address signal and the queue count signal, and outputs an instruction prefetch address signal corresponding to an instruction prefetch operation to the memory management unit; Address confirmation signal and In accordance with the input state of the queue count signal, it is configured to include at least an instruction queue buffer that sequentially holds branch instructions on the instruction prefetch data bus and sequentially outputs the branch instruction signals to the instruction decoder, The memory management unit inputs and holds a data signal input via a predetermined data bus and a virtual address signal input via a predetermined virtual address bus, and the real address signal corresponding to the previous data signal. And an address conversion buffer for outputting an address conversion data signal corresponding to the virtual address signal, a data signal input via the data bus and the address conversion data signal, and both signals And an address comparator which outputs a page fault signal as the comparison result, and the address. A page boundary discriminator that inputs a real address signal output from the conversion buffer to generate and output a predetermined page boundary signal, a predetermined prefetch command signal, and the page boundary signal are input, and the prefetch command signal is input. In the case of a branch instruction, a branch instruction discriminator that outputs a predetermined read-ahead stop signal, the page fault signal and the read-ahead stop signal are input, and a branch read-ahead address confirmation signal output from the instruction execution unit is generated. And a page fault gate for outputting the output.

[0018]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In FIG. 1, the microprocessor 1 includes an instruction prefetching device 2, an instruction decoder 3, an instruction execution unit 4, and a memory management unit 5, and a branch address output from the instruction execution unit 4. Signal 101 and branch destination address confirmation signal 1
02 is connected to the instruction prefetching device 2. The instruction prefetching device 2 is connected to the instruction decoder 3 via the instruction queue data bus 103, and the instruction decode signal 104 output from the instruction decoder 3 is connected to the instruction execution unit 4. Further, the instruction prefetch address signal 108 output from the instruction prefetch device 2 is the internal address bus 11
The instruction prefetching device 2 is connected to the internal data bus 109 via the instruction prefetch data bus 106.
It is connected to the. Further, the instruction execution unit 4 uses the internal data bus 109 via the operand data bus 113.
And the operand address bus 114
Is connected to the internal address bus 110 via. Further, the memory management unit 5 is connected to the internal data bus 109 via the data bus 111 and to the internal address bus 110 via the virtual address bus 112, and is output from the memory management unit 5. The page fault signal 105 is sent to the instruction execution unit 4, the page boundary signal 107 that is also output is input to the instruction prefetch unit 2, and the real address signal 116 is also input.
Is output to the outside of the microprocessor 1.

The internal structure of the instruction prefetching device 2 in this embodiment is shown in FIG.
The branch instruction discriminator 7, the queue counter 8, the address adder 9, and the instruction queue buffer 10 are provided. As is clear from a comparison with the instruction prefetching device 22 in the conventional microprocessor shown in FIG. 10, the instruction prefetching device 2 in this embodiment additionally includes a branch instruction discriminator 7. The branch instruction discriminator 7 is connected to the instruction prefetch data bus 106 connected to the internal data bus 109, and the branch destination address determination signal 102 output from the instruction execution unit 4 and the page output from the memory management unit 5 are output. The boundary signal 107 is input, and the instruction prefetch stop signal 117 output from the branch instruction discriminator 7 is sent to the queue counter 8. FIG. 3 is a block diagram showing an internal configuration of the branch instruction discriminator 7, which includes a decoder 11 connected to the instruction prefetch data bus 106 and the decoder 11 concerned.
AND the page boundary signal 107, a logical product circuit 12 for outputting a logical product, a logical product output of the logical product circuit 12, an input of the branch destination address determination signal 102 and the clock signal 102, and an instruction prefetch stop signal 117. And a flip-flop 13 that outputs

FIG. 4 is a block diagram showing the internal structure of the memory management unit 5 included in this embodiment shown in FIG. 1. The address conversion buffer 14 and the address comparator 15 are shown in FIG.
And a page boundary discriminator 16 newly added. The data bus 111 and the virtual address bus 112 are connected to the address translation buffer 14, and the address translation data signal 121 and the real address are provided. The signal 116 is output. Also, the address comparator 15
Is connected to the virtual address bus 112, the address conversion data signal 121 is input, and the page fault signal 105 is output. The page boundary discriminator 16 receives the real address signal 116 and outputs the page boundary signal 107. As shown in FIG. 5, the page boundary discriminator 16 is composed of a decoder 17, and receives the input of the real address signal 116,
The page boundary signal 107 is output.

Next, in this embodiment, the operation when the program is executed using the instruction prefetching device 2 will be described. When starting the execution of the microprocessor 1 from a certain address, the execution start address is set in the program counter 6 of the instruction prefetching device 2 and the address value is output as the execution address signal 118 to be added to the address adder. 9 is input. On the other hand, in the page boundary discriminator 16 of the memory management unit 5, the lower address value of the real address signal 116 is the page boundary (4
If it is kB / page, it is determined whether or not FFFh is the boundary), and if it is determined to be the page boundary, the page boundary signal 107 is output at the active level and the instruction prefetch device 2 branches. It is sent to the instruction discriminator 7. Now, assume that the branch instruction is the instruction prefetch data bus 106.
It is assumed that the branch instruction is when the upper 4 bits of "1011" are "1011". In this case, when a branch instruction is present on the instruction prefetch data bus 106 and the upper 4 bits “1011” of the instruction prefetch data bus 106 are decoded by the decoder 11 in the branch instruction discriminator 7 of FIG. The decoded output is output at the active level and input to the AND circuit 12. This AND circuit 12
As another input, a page boundary signal 107 output from the memory management unit 5 is also input to
When these two signals are both at active level,
An AND level circuit 12 outputs an active level signal, and the JK flip-flop 13 receives the active level signal and is set.

The page boundary signal 107 is a signal output from the page boundary discriminator 16 of the memory management unit 5. In FIG. 5, the real address signal 116 input from the address conversion buffer 14 is input to the decoder 17. Then, it is checked whether or not the value of the lower address of the real address signal 116 is “FFFh”,
When the value of the lower address is “FFFh”, the page boundary signal 107 is output from the page boundary discriminator 16 at the active level. In addition to the output of the AND circuit 12, the JK flip-flop 13 is also supplied with the clock signal 120 and the branch destination address confirmation signal 102 sent from the instruction execution unit 4, and is connected to the branch instruction discriminator 7. The branch instruction determiner 7 receives the branch instruction of the instruction prefetch data bus 106, the page boundary signal 107 output from the memory management unit 5, and the branch prefetch address determination signal 102 output from the instruction execution unit 4. Is the corresponding instruction preemption stop signal 117
Is output and sent to the queue counter 8. Figure 6
(A), (b), (c) and (d) are timing charts of operation signals in the branch instruction discriminator 7. Figure 6
In, the prefetched instruction is input to the decoder 11 of the branch instruction discriminator 7 via the instruction prefetch data bus 106, it is determined whether the instruction is a branch instruction, and it is determined that the instruction is a branch instruction. When the branch destination address determination signal 102 is input at the inactive level and the page boundary signal 107 is input at the active level (see FIG. 6B), the instruction prefetch is performed. The stop signal 117 is output at the active level (see FIG. 6D). Further, when it is determined that the instruction is a branch instruction and the branch destination address determination signal 102 becomes active (see FIG. 6C), the instruction prefetch stop signal 117 becomes inactive level (FIG. 6D). Reference).

Therefore, in the course of executing the program, the branch instruction at the page boundary is read by the instruction prefetching device 2 and input to the branch instruction discriminator 7 via the instruction prefetch data bus 106, and at the same time, Since the page boundary signal 107 output from the memory management unit 5 becomes active level, the instruction prefetch stop signal 117 output from the branch instruction discriminator 7 in the instruction prefetch device 2 is output at active level. Instruction prefetch stop signal 11
7 is input to the queue counter 8 and the address adder 9. However, when the instruction prefetch stop signal 117 is at the active level, both the queue counter 8 and the address adder 9 are in the operation stop state. This stops the instruction prefetch operation function. During the stop of the instruction prefetch operation, the instruction execution unit 4 determines the branch destination of the branch instruction that caused the instruction prefetch stop,
Branch destination address confirmation signal 102 from instruction execution unit 4
Is output and input to the branch instruction discriminator 7. At the same time, the branch destination address signal 101 is input to the program counter 6. In the branch destination instruction discriminator 7, the branch destination address decision signal 102 is input, the instruction prefetch stop signal 117 shifts to the inactive level, and in response to this, the queue counter 8 and the address adder 9 are both normal. The operation is restored, and the instruction prefetch operation from the branch destination address is restarted.

Next, a second embodiment of the present invention will be described. FIG. 7 is a block diagram showing the configuration of the second embodiment of the present invention. In FIG. 2, the microprocessor 1
The instruction look-ahead device 22 includes an instruction decoder 3, an instruction decoder 3, an instruction execution unit 4, and a memory management unit 19.
Has the same configuration as the conventional instruction prefetching device 22 shown in FIG. Branch address signal 101 and branch destination address confirmation signal 102 output from the instruction execution unit 4
Are connected to the instruction prefetching device 22. The instruction prefetching device 2 is connected to the instruction decoder 3 via the instruction queue data bus 103, and the instruction decode signal 104 output from the instruction decoder 3 is connected to the instruction execution unit 4. Further, the instruction prefetch address signal 108 output from the instruction prefetch device 2 is the internal address bus 110.
The instruction prefetch device 22 is connected to the internal data bus 109 via the instruction prefetch data bus 106.
It is also connected to the memory management unit 19. Further, the instruction execution unit 4 uses the operand data bus 11
3 to an internal data bus 109, and an operand address bus 114 to an internal address bus 110.
And the output branch destination address determination signal 102 is directly connected to the memory management unit 19. In addition, the memory management unit 19 uses the data bus 1
The page fault signal 105 output from the memory management unit 5 to the instruction execution unit 4 is connected to the internal data bus 109 via 11 and the internal address bus 110 via the virtual address bus 112. The real address signal 116 that is sent out and output in the same manner is output to the outside of the microprocessor 1.

In this embodiment, the memory management unit shown in FIG. 8 includes a branch instruction discriminator 7 and an address translation buffer 1.
4, an address comparator 15, and a page boundary discriminator 16
And a page fault gate 20. As apparent from comparison with the conventional example, the branch instruction discriminator 7, the address comparator 15, and the page boundary discriminator 16 are provided.
Is newly added. In FIG. 8, the real address signal 116 output from the address translation buffer 14 is input to the page boundary discriminator 16, and the page boundary signal 107 output from the page boundary discriminator 16 is input to the branch instruction discriminator 7. To be done. An instruction prefetch data bus 106 is connected to the branch instruction discriminator 7, and an instruction prefetch stop signal 123 output from the branch instruction discriminator 7 and an output from the address comparator 20 are output to the page fault gate 20. The mismatch signal 122 and the branch destination address confirmation signal 102 are input. A page fault signal 105 is output from the page fault gate 20 and sent to the instruction execution unit 4.

When prefetching an instruction at a page boundary, the page boundary discriminator 16 outputs a page boundary signal 10.
7 is output, and at the same time, the read instruction is input to the branch instruction discriminator 7 from the instruction prefetch data bus 106 via the data bus 115. In the branch instruction discriminator 7, when the page boundary signal 107 is active and the instruction on the instruction prefetch data bus 106 is a branch instruction, the instruction prefetch stop signal 117 transitions to active. When the instruction prefetch stop signal 117 becomes active, the page fault gate 20 is closed and the page fault signal 105 is always inactive. In this state, the next instruction read-ahead cycle occurs, but since the instruction read-ahead cycle immediately before the instruction read-ahead cycle was on a page boundary, the virtual address was not registered in the address translation buffer 14. In this case, in the conventional example, a page fault occurs due to a mismatch in the comparison and comparison results in the address comparator 15. However, in the present embodiment, the page fault gate 20 is closed, so the page fault is generated. Does not occur. After that, when the branch instruction at the page boundary is executed by the instruction execution unit 54 to determine the branch destination address, a new branch destination address is input from the virtual address bus 112, and
By the branch destination address confirmation signal 102, the page fault gate 20 is opened, and the page fault can be generated. When the branch destination address of the branch instruction is not registered in the address translation buffer 14, a page fault occurs due to a mismatch in the address comparator 15. Further, when the branch destination address of the branch instruction is registered in the address translation buffer 14, the instruction prefetch from the branch destination address is performed.

That is, in this embodiment, even if a branch instruction exists at a page boundary and the branch destination is outside the current page, the branch destination is registered in the address translation buffer 14. Page page
By utilizing the fact that no default occurs, the operation frequency at which the instruction prefetching operation is stopped is reduced as compared with the case of the first embodiment, and therefore the execution speed of the program can be improved. .

The operation related to the instruction prefetching device 22 is the same as in the case of the above-mentioned conventional example, and its explanation is omitted.

[0030]

As described above, according to the present invention, a branch instruction exists on a page boundary by providing a branch instruction discrimination function, an instruction prefetch stop function, and a branch destination address decision discrimination function in the instruction prefetch device. However, even when the branch destination of the branch instruction is within the page, the deterioration of the program execution due to unnecessary page faults is prevented,
There is an effect that the program execution speed can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing one embodiment of an instruction prefetching device in the first embodiment.

FIG. 3 is a block diagram showing an embodiment of a branch instruction discriminator in the instruction prefetching device.

FIG. 4 is one of the memory management units in the first embodiment.
It is a block diagram which shows an Example.

FIG. 5 is a block diagram showing a page boundary discriminator in the memory management unit.

FIG. 6 is an operation timing chart of instruction prefetch stop signal output.

FIG. 7 is a block diagram showing a second embodiment of the present invention.

FIG. 8 is one of the memory management units in the second embodiment.
It is a block diagram which shows an Example.

FIG. 9 is a block diagram showing a conventional example.

FIG. 10 is a block diagram showing an instruction prefetching device in a conventional example.

FIG. 11 is a block diagram showing a memory management unit in a conventional example.

FIG. 12 is a diagram showing a system configuration using a virtual memory.

FIG. 13 is a diagram showing an instruction prefetching device when performing branch prediction.

[Explanation of symbols]

 1, 18, 21 Microprocessor 2, 22, 26 Instruction prefetching device 3 Instruction decoder 4 Instruction execution unit 5, 19, 23 Memory management unit 6 Program counter 7 Branch instruction discriminator 8 Queue counter 9 Address adder 10 Instruction queue buffer 11 , 17 decoder 12 AND circuit 13 flip-flop 14 address conversion buffer 15 address comparator 16 page boundary discriminator 20 page fault gate 24 real memory 25 hard disk 27 branch history buffer 28 comparator 29, 30 address switch 101 branch address signal 102 branch Destination address confirmation signal 103 Instruction queue data bus 104 Instruction decode signal 105 Page fault signal 106 Instruction prefetch data bus 107 Page boundary signal 108, 127 instruction Prefetch address signal 109 Internal data bus 110 Internal address bus 111, 115 Data bus 112 Virtual address bus 113 Operand data bus 114 Operand address bus 116 Real address signal 117 Instruction prefetch stop signal 118 Execution address signal 119 Queue count signal 120 Internal clock signal 121 Address conversion data signal 122 Mismatch signal 123 Prefetch stop signal 124, 126 Branch destination address signal 125 Match signal

Claims (2)

[Claims] 1. A microprocessor having at least an instruction prefetch means, an instruction decoder, an instruction execution unit and a memory management unit, and having a virtual memory management mechanism, wherein the instruction prefetch means outputs a branch destination address from the instruction execution unit. A program counter that receives a signal input and outputs an instruction execution address signal corresponding to the branch destination address signal, a branch destination address confirmation signal output from the instruction execution unit, and a page output from the memory management unit A branch instruction discriminator which receives an input of a boundary signal and outputs an instruction prefetch stop signal of a predetermined level in response to the presence of a branch instruction on a predetermined instruction prefetch data bus, and a predetermined increment by every bus cycle Has the operation function of outputting the cue count signal of A queue counter whose operation function is controlled by a constant level instruction prefetch stop signal, and the instruction execution address signal and the queue count signal are input and added to correspond to the instruction prefetch operation for the memory management unit. Address adder having an operation function of outputting an instruction prefetch address signal, the operation function of which is controlled by the instruction prefetch stop signal of the predetermined level, and an input state of the branch destination address confirmation signal and the queue count signal And an instruction queue buffer that sequentially holds branch instructions on the instruction prefetch data bus and sequentially outputs the branch instructions to the instruction decoder, wherein the memory management unit has a predetermined data bus. Data signal input via the bus and input via a predetermined virtual address bus An address conversion buffer that inputs and holds a virtual address signal, outputs a real address signal corresponding to the data signal, and outputs an address conversion data signal corresponding to the virtual address signal, and the data bus An address to be input to the instruction execution unit by inputting a data signal input via the address conversion data signal, comparing and collating these two signals, and outputting a page fault signal as the comparison result. A microprocessor comprising at least a comparator, and a page boundary discriminator which inputs the real address signal output from the address conversion buffer and generates and outputs the page boundary signal. . 2. A microprocessor having at least a command prefetching unit, a command decoder, a command execution unit and a memory management unit and having a virtual memory management mechanism, wherein the command prefetching unit outputs a branch destination address output from the command execution unit. A program counter that receives an input of a signal and outputs an instruction execution address signal corresponding to the branch destination address signal, a queue counter that outputs a predetermined queue count signal that is incremented for each bus cycle, and the instruction execution address signal And an address adder that inputs and adds the queue count signal and outputs an instruction prefetch address signal corresponding to the instruction prefetch operation to the memory management unit; and a branch destination address confirmation signal and the queue count signal. For input state And an instruction queue buffer for sequentially holding branch instructions on the instruction prefetch data bus and sequentially outputting the branch instruction signals to the instruction decoder. The data signal input via the bus and the virtual address signal input via a predetermined virtual address bus are input and held, and the real address signal is output in response to the previous data signal, and the virtual address signal is output. An address conversion buffer that outputs an address conversion data signal corresponding to the above, and a data signal input via the data bus and the address conversion data signal are input, and both signals are compared and collated, and the comparison is performed. As a result, an address comparator which outputs a page fault signal, and an actual address output from the address conversion buffer. Enter the-less signals, enter the page boundary discriminator generating and outputting a predetermined page boundary signal, the page boundary signal with a predetermined prefetch instruction signal,
A branch instruction discriminator that outputs a predetermined pre-read stop signal when the pre-read instruction signal is a branch instruction, and a branch pre-read that is output from the instruction execution unit by inputting the page fault signal and the pre-read stop signal A page fault gate that generates and outputs an address confirmation signal, and a microprocessor.