JPH0831954A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent leak current between first and second element formation regions and to stabilize electrical characteristics by setting the n-type first semiconductor region and n-type second semiconductor region to the same potential. CONSTITUTION:A semiconductor layer 5 is laminated on the main surface of a support substrate 3 via an insulator 4. First and second element formation regions 6A and 6B of the semiconductor layer 5 are mutually separated by a separation groove 11 reaching the insulator 4 from the main surface of the semiconductor layer 5. N-type first semiconductor region 7A and n-type second semiconductor region 7B are formed between n-type well region 8 of the first element formation region 6A of the semiconductor layer 5 and the insulator and between p-type well region 9 of the second element formation region 6B of the semiconductor layer 5 and the insulator 4, respectively. Especially, the n-type first semiconductor region 7A and the n-type second & semiconductor region 7B are set to the same potential, thus preventing leak current between the first element formation region 6A and the second element formation region 6B even if a small defect occurs at the separation groove 11 and the insulator 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor layer having a first element formation region and a second element formation region which are laminated on the main surface of an insulator. The present invention relates to a technique effectively applied to a semiconductor integrated circuit device which is separated from each other by a separation groove reaching a surface of the insulator.

[0002]

2. Description of the Related Art The SRAM (Static
RandomAccessMemory) is insulated on the main surface of the support substrate
A so-called SOI (layer of semiconductor layers stacked with a body interposed)Silicon
OnInsulator) structure semiconductor substrate
It In the memory cell array forming region of the semiconductor substrate,
A number of memory cells are arranged in a matrix.

[0003] The memory cell includes a flip-flop circuit and two transfer MOSFET (M etal O xide S emic
consisting of onductor F ield E ffect T ransistor) .
The flip-flop circuit is configured as an information storage unit,
Two drive MOSFETs and two load MOSFETs
Composed of T. The two load MOSFETs are of p-channel conductivity type, and the two transfer MOSFETs and the two driving MOSFETs are of n-channel conductivity type.

Each of the two load MOSFETs is mounted in a P-MOS formation region (first element formation region) of the semiconductor layer, and has two transfer MOSFETs and two drive MOs.
Each of the SFETs has an N-MOS formation region (second
It is mounted in the device formation area).

The P-MOS formation region and the N-MOS formation region are insulated and isolated from each other by an isolation groove which reaches the insulator in the depth direction from the main surface of the element isolation region of the semiconductor layer. An insulator made of, for example, a silicon oxide film is embedded in the isolation trench.

An n-type well region used as a channel forming region of the load MOSFET is formed on the main surface of the P-MOS forming region of the semiconductor layer. Further, a buried n-type semiconductor region having a higher impurity concentration than that of the n-type well region is formed between the insulator and the n-type well region in the P-MOS formation region of the semiconductor layer. .

On the main surface of the N-MOS formation region of the semiconductor layer, p-type well regions used as channel formation regions for the transfer MOSFET and the drive MOSFET are formed. In addition, p in the N-MOS formation region of the semiconductor layer
A buried n-type semiconductor region is formed between the type well region and the insulator. The buried n-type semiconductor region is formed in the same manufacturing process as the buried n-type semiconductor region used for supplying the well potential.

The SRAM having the above structure is formed of an insulator and a separation groove formed between the supporting substrate and the semiconductor layer, and has a P shape.
Since the -MOS formation region and the N-MOS formation region can be completely separated from each other, latch-up resistance, operating speed, integration density, radiation resistance, etc. can be improved.

[0009]

In the SRAM (semiconductor integrated circuit device), the P-MOS formation region and the N-M are formed.
The isolation groove for insulating isolation from the OS formation area (between the element formation areas) tends to become finer with higher integration, and micro defects are likely to occur in the isolation groove and the insulator embedded in the isolation groove. . Therefore, a leak current is generated between the P-MOS formation region and the N-MOS formation region, and the load MOSF is formed.
Since the electrical characteristics of each of the ET, the driving MOSFET, and the transfer MOSFET become unstable, there is a problem that the electrical reliability of the SRAM decreases.

An object of the present invention is to provide a technique capable of improving the electrical reliability of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

The first element formation region and the second element formation region of the semiconductor layer laminated on the main surface of the insulator are separated from each other by a separation groove reaching the insulator from the main surface of the semiconductor layer, N used as the channel formation region of the p-channel MISFET on the main surface of the first element formation region of the semiconductor layer
A p-type well region used as a channel formation region of an n-channel MISFET is formed on the main surface of the second well formation region of the semiconductor layer, and n of the first formation region of the semiconductor layer is formed. An n-type first semiconductor region is provided between the type well region and the insulator, and an n-type second semiconductor region is provided between the p-type well region and the insulator in the second element forming region of the semiconductor layer.
In the semiconductor integrated circuit device in which each of the semiconductor regions is formed, the n-type first semiconductor region and the n-type second semiconductor region are set to the same potential.

[0014]

According to the above-mentioned means, even if a minute defect occurs in the isolation trench or the insulator embedded in the isolation trench, the n-type first semiconductor region and the n-type second semiconductor region are the same. Since the potential is set, the leak current between the first element formation region and the second element formation region can be prevented. As a result, p-channel MISFET, n-channel MISFE
Since the electrical properties of each T can be stabilized, the electrical reliability of the semiconductor integrated circuit device can be improved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with an embodiment in which the present invention is applied to an SRAM.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 (plan view of a main portion) shows a schematic structure of an SRAM which is Embodiment 1 of the present invention.

As shown in FIG. 1, the SRAM has a plurality of memory cells 2 arranged in a memory cell array forming region of a semiconductor chip 1. The plurality of memory cells 2 are regularly arranged in a matrix in the respective extending directions of the word lines and the data lines.

As shown in FIG. 2 (equivalent circuit diagram), the memory cell 2 has a first data line DL1 and a second data line DL2.
Are arranged at the intersections with the respective word lines WL. The memory cell 2, the flip-flop circuit composed of two inverter circuits and two transfer MISFET (M etal In
sulator S emiconductor F ield E ffect T ransistor)
It is composed of Qt1 and Qt2.

Each of the transfer MISFETs Qt1 and Qt2 has one semiconductor region connected to each of a pair of input / output terminals of the flip-flop circuit. MISFET for transfer
The other semiconductor region of Qt1 is connected to the first data line DL1 and its gate electrode is connected to the word line WL. The other semiconductor region of the transfer MISFET Qt2 is connected to the second data line DL2, and its gate electrode is the word line WL.
Connected to. The transfer MISFETs Qt1 and Qt2
Of n channel conductivity type.

The flip-flop circuit includes two driving MISFETs Qd1 and Qd2 and two load MISFETs.
It is composed of FETs Qp1 and Qp2. MISF for drive
Each of ETQd1 and ETQd2 is of n-channel conductivity type. Each of the load MISFETs Qp1 and Qp2 is of p-channel conductivity type. That is, the SRA of this embodiment
Memory cell 2 of M is complete CMIS (C omplementary M e
It consists of tal Insulator S emiconductor) structure.

The driving MISFET Qd1 and the load M
Each of the ISFETs Qp1 connects their drain regions to each other and their gate electrodes to each other. Similarly, drive MISFETQd2, load MISFETQ
Each of p2 connects the drain regions to each other and the gate electrodes to each other. MISFET for drive
The drain regions (storage nodes) of the Qd1 and the load MISFET Qp1 are connected to one semiconductor region of the transfer MISFET Qt1 and the driving MISFET Q is formed.
d2, connected to the respective gate electrodes of the load MISFET Qp2. Drive MISFET Qd2, load MIS
Each drain region (storage node) of the FET Qp2 is connected to one semiconductor region of the transfer MISFET Qt2, and also has a driving MISFET Qd1 and a load MISF.
It is connected to each gate electrode of ETQp1.

The source region of each of the driving MISFETs Qd1 and Qd2 is, for example, a power supply potential VEM (for example, −
It is fixed at 2.5 [V]). In addition, the load MIS
The source regions of the FETs Qp1 and Qp2 are fixed to the reference potential VCC (for example, 0 [V]), for example.

The memory cell 2 is, as shown in FIG.
In the memory cell array forming region of the semiconductor chip 1, the P-MI whose periphery is defined by the field insulating film 10.
MISFE for load is formed in the S formation region (first element formation region) 6A.
Each of TQp1 and Qp2 is mounted on the field insulating film 1
The driving MISFETs Qd1 and Qd2 and the transfer MISFETs Qt1 and Qt2 are mounted in the N-MIS formation region (second element formation region) 6B whose periphery is defined by 0. The P-MIS formation region 6A and the N-MIS formation region 6B are insulated and isolated from each other by the isolation trench 11. The isolation trench 11 extends along, for example, the extending direction of the word line WL, and the P-MIS formation regions 6A and NM of each memory cell 2 are formed.
The IS formation region 6B is separated.

As shown in FIG. 3 (a sectional view taken along the line AA of FIG. 1), the semiconductor chip 1 has a semiconductor layer 5 on the main surface of the support substrate 3 with an insulator 4 interposed therebetween. Is formed by stacking SOI structures. The support substrate 3 is formed of, for example, a single crystal silicon substrate, and the insulator 4 is formed of, for example, a silicon oxide film. Although not limited to this embodiment, the semiconductor layer 5 has a two-layer structure in which the epitaxial layer 5B is laminated on the main surface of the single crystal silicon substrate 5A.

P-MIS formation region 6A of the semiconductor layer 5
An n-type well region 8 is formed on the main surface of. Also, P-
In the MIS formation region 6A, the bottom surface of the n-type well region 8 is in contact with the space between the n-type well region 8 and the insulator 4.
The n + type semiconductor region 7A is formed. Each of the n-type well region 8 and the n + -type semiconductor region 7A extends along the extending direction of the word line WL.

N-MIS formation region 6B of the semiconductor layer 5
A p-type well region 9 is formed on the main surface of. Also, N-
In the MIS formation region 6B, between the p-type well region 9 and the insulator 4 is in contact with the bottom surface of the p-type well region 9.
The n + type semiconductor region 7B is formed. Each of p type well region 9 and n + type semiconductor region 7B extends along the extending direction of word line WL.

Each of the n + type semiconductor region 7A and the n + type semiconductor region 7B has the same manufacturing process as the buried type semiconductor region which is the collector region of the bipolar transistor mounted in the peripheral circuit forming region of the semiconductor chip 1. At the same time or separately.

A load M is formed on the main surface of the n-type well region 8.
ISFET Qp1 is configured. MISFE for this load
The TQp1 is composed of an n-type well region (channel forming region) 8, a gate insulating film 13, a gate electrode 14, and a pair of p + -type semiconductor regions 16 which are a source region and a drain region. Although not shown, a load MISFET Qp2 is formed on the main surface of the n-type well region 8.

A driving M is formed on the main surface of the p-type well region 9.
ISFET Qd1 is configured. This drive MISFE
The TQd1 is composed of a p-type well region (channel forming region) 9, a gate insulating film 13, a gate electrode 14, and a pair of n + type semiconductor regions 15 which are a source region and a drain region. Although not shown, the main surface of the p-type well region 9 includes a driving MISFET Qd1 and a transfer MISFET.
Each of Qt1 and Qt2 is configured.

In the semiconductor layer 5, each of the P-MOS formation region 6A and the N-MOS formation region 6B is a separation groove 11 that reaches the insulator 4 from the main surface of the semiconductor layer 5 in the depth direction. Isolated from each other. An insulator 12 formed of, for example, a silicon oxide film is embedded in the separation groove 11. That is, the n-type well region 8 and the n + -type semiconductor region 7
Each of A, the p-type well region 9 and each of the n + type semiconductor regions 7B are insulated and isolated from each other by the isolation groove 11 and the insulator 12.

The n-type well region 8 is fixed at 0 [V] potential, for example. The p-type well region 9 has, for example, -2.5.
It is fixed at the [V] potential. Each of the n + type semiconductor region 7A and the n + type semiconductor region 7B is fixed at, for example, 0 [V] potential. That is, the n + type semiconductor region 7A and the buried type n + type semiconductor region 7B are set to the same potential.

The separation groove 11 is formed by, for example, a dry etching technique. The isolation width of the isolation trench 11 is reduced to about 0.5 [μm], for example, as the memory cell 2 is highly integrated. Along with this miniaturization, minute defects are easily generated in each of the isolation trench 11 and the insulator 12 embedded in the isolation trench 11, but as described above, the n + type semiconductor region 7 is formed.
Since the A and n + type semiconductor regions 7B are set to the same potential, even if a minute defect occurs in the isolation trench 11 or the insulator 12, the P-MIS formation region 6A and the N-MIS formation region 6 are formed.
It is possible to prevent a leak current between B and B.

As described above, the P-MIS formation region (first element formation region) of the semiconductor layer 5 laminated on the main surface of the insulator 4 is formed.
6A and an N-MIS formation region (second element formation region) 6B are separated from each other by an isolation groove 11 that reaches the insulator 4 from the main surface of the semiconductor layer 5, and the P-MIS of the semiconductor layer 5 is formed.
Load MISFETs Qp1 and Qp are formed on the main surface of the formation region 6A.
2, n-type well regions 8 used as respective channel formation regions, and driving MISFETs Qd1 and Qd2 and transfer MI on the main surface of the N-MIS formation region 6B of the semiconductor layer 5.
The p-type well regions 9 used as the channel forming regions of the SFETs Qt1 and Qt2 are formed, respectively, and between the n-type well region 8 of the P-MIS forming region 6A of the semiconductor layer 5 and the insulator 4. n + type semiconductor region 7A, p type well region 9 of N-MIS formation region 6B of the semiconductor layer 5
In the SRAM (semiconductor integrated circuit device) in which each of the n + type semiconductor regions 7B is formed between the insulator 4 and the insulator 4,
The type semiconductor region 7A and the n + type semiconductor region 7B are set to the same potential. With this configuration, even if a minute defect occurs in the isolation trench 11 or the insulator 12 embedded in the isolation trench 11, the n + type semiconductor region 7A and the n + type semiconductor region 7B are set to the same potential. , A leak current between the P-MIS formation region 6A and the N-MIS formation region 6B can be prevented. As a result, the load MISFET Qp
1, Qp2, the driving MISFETs Qd1 and Qd2, and the transfer MISFETs Qt1 and Qt2 can be stabilized in electrical characteristics, so that the electrical reliability of the semiconductor integrated circuit device can be improved.

Further, even if a separation failure that does not reach the insulator 4 occurs in the separation groove 11, the separation failure occurs because the n + type semiconductor region 7A and the n + type semiconductor region 7B are set to the same potential. In the isolation groove 11, the P-MIS formation region 6A,
It is possible to prevent defects in each memory cell 2 in which the N-MIS formation regions 6B are separated from each other.

Further, the P-MIS formation region 6A and the N-MI are formed.
Since leakage current between the S formation region 6B and the S formation region 6B can be prevented, further miniaturization of the isolation trench 11 can be achieved.

Further, the P-MIS formation region 6A and the N-MI are formed.
Since the isolation trench 11 between the S formation region 6B and the S formation region 6B can be formed shallowly, the yield of SRAM can be increased.

(Embodiment 2) FIG. 4 (cross-sectional view) shows a schematic configuration of a memory cell of an SRAM which is Embodiment 2 of the present invention.

As shown in FIG. 4, in the memory cell of the SRAM, in the memory cell array forming region of the semiconductor chip 1, the P-MIS forming region (first element) of the semiconductor layer 5 whose periphery is defined by the field insulating film 10 is formed. In the formation region) 6A, the load MISFET Qp1 is mounted, and the field insulating film 1 is formed.
In the P-MIS formation region (second element formation region) 6B of the semiconductor layer 5 whose periphery is defined by 0, the driving MISFET Qd1 is formed.
To install. This P-MIS formation region 6A, N-MIS
The formation regions 6B are insulated and separated from each other by the isolation trench 11 that reaches the insulator 4 from the main surface of the semiconductor layer 5 in the depth direction thereof and the insulator 12 embedded in the isolation trench 11.

P-MIS formation region 6A of the semiconductor layer 5
An n-type well region 8 is formed on the main surface of. Also, P-
In the MIS formation region 6A, the bottom surface of the n-type well region 8 is in contact with the space between the n-type well region 8 and the insulator 4.
The n + type semiconductor region 7A is formed.

N-MIS formation region 6B of the semiconductor layer 5
A p-type well region 9 is formed on the main surface of. Also, N-
In the MIS formation region 6B, between the p-type well region 9 and the insulator 4 is in contact with the bottom surface of the p-type well region 9.
The n − type semiconductor region 17 is formed. The n − type semiconductor region 17 is set to have an impurity concentration lower than that of the n + type semiconductor region 7, and is composed of, for example, a single-bonded silicon substrate 5A. By thus forming the n − type semiconductor region 17 between the p type well region 9 and the insulator 4, the n + type semiconductor region 15 is the emitter region, the p type well region 9 is the base region, and the n − type semiconductor region 17 is formed. It is possible to prevent the parasitic operation of the parasitic bipolar transistor having the semiconductor region 17 as the collector region.

The load MISFET Qp1 is formed on the main surface of the n-type well region 8 used as a channel forming region thereof. The driving MISFET Qd1 is formed on the main surface of the p-type well region 9 used as its channel forming region.

The n-type well region 8 is fixed at, for example, 0 [V] potential. The p-type well region 9 has, for example, -2.5.
It is fixed at the [V] potential. Each of the n + type semiconductor region 7A and the n − type semiconductor region 17 is fixed to 0 [V] potential, for example. That is, the n + type semiconductor region 7A and the n − type semiconductor region 17
Are set to the same potential.

As described above, by setting the n + type semiconductor region 7A and the n− type semiconductor region 17 to the same potential, the same effect as that of the first embodiment can be obtained.

(Embodiment 3) FIG. 5 (cross-sectional view) shows a schematic configuration of a memory cell of an SRAM which is Embodiment 2 of the present invention.

As shown in FIG. 5, in the memory cell of the SRAM, in the memory cell array forming region of the semiconductor chip 1, the P-MIS forming region (first element) of the semiconductor layer 5 whose periphery is defined by the field insulating film 10 is formed. In the formation region) 6A, the load MISFET Qp1 is mounted, and the field insulating film 1 is formed.
In the P-MIS formation region (second element formation region) 6B of the semiconductor layer 5 whose periphery is defined by 0, the driving MISFET Qd1 is formed.
To install. This P-MIS formation region 6A, N-MIS
The formation regions 6B are insulated and separated from each other by the isolation trench 11 that reaches the insulator 4 from the main surface of the semiconductor layer 5 in the depth direction thereof and the insulator 12 embedded in the isolation trench 11.

N-MIS formation region 6B of the semiconductor layer 5
A p-type well region 9 is formed on the main surface of. Also, N-
In the MIS formation region 6B, between the p-type well region 9 and the insulator 4 is in contact with the bottom surface of the p-type well region 9.
The n − type semiconductor region 17 is formed.

P-MIS formation region 6A of the semiconductor layer 5
An n-type well region 8 is formed on the main surface of. Also, P-
In the MIS formation region 6A, the bottom surface of the n-type well region 8 is in contact with the space between the n-type well region 8 and the insulator 4.
The n + type semiconductor region 7A ₁ is formed. In addition, P-MIS
In the formation region 6A, the n − type semiconductor region 17 is formed between the n + type semiconductor region 7A ₁ and the insulator 4. This n-
The type semiconductor region 17 is set to have an impurity concentration lower than that of the n + type semiconductor region 7A ₁ and is composed of, for example, a single crystal silicon substrate 5A.

Each of the n + type semiconductor region 7A ₁ and the n− type semiconductor region 17 is fixed to 0 [V] potential, for example. That is, the n + type semiconductor region 7A ₁ and the n− type semiconductor region 17 are set to the same potential.

As described above, by setting the n + type semiconductor region 7A ₁ and the n− type semiconductor region 17 to the same potential, the same effect as that of the first embodiment can be obtained.

The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0052]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

The electrical reliability of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a main part of an SRAM that is Embodiment 1 of the present invention.

FIG. 2 is an equivalent circuit diagram of the memory cell of the SRAM.

3 is a cross-sectional view taken along the line AA shown in FIG.

FIG. 4 is a sectional view of a main part of an SRAM which is Embodiment 2 of the present invention.

FIG. 5 is a cross-sectional view of essential parts of an SRAM according to a third embodiment of the present invention.

[Explanation of symbols]

1 ... Semiconductor chip, 2 ... Memory cell, 3 ... Support substrate, 4
... insulator, 5 ... semiconductor layer, 6A ... P-MIS formation region,
6B ... N-MIS formation region, 7A, 7B ... n + type semiconductor region, 8 ... N type well region, 9 ... P type well region, 10 ...
Field insulating film, 11 ... Separation groove, 12 ... Insulator, 13
... Gate insulating film, 14 ... Gate electrode, 15 ... N + type semiconductor region, 16 ... P + type semiconductor region, 17 ... N- type semiconductor region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/08 331 AC

Claims (3)

[Claims] 1. A first element formation region and a second element formation region of a semiconductor layer stacked on a main surface of an insulator are separated from each other by a separation groove that reaches the insulator from the main surface of the semiconductor layer. , Used as a channel formation region of a p-channel MISFET on the main surface of the first element formation region of the semiconductor layer.
A p-type well region used as a channel formation region of an n-channel MISFET is formed on the main surface of the second well formation region of the semiconductor layer, and n of the first formation region of the semiconductor layer is formed. An n-type first semiconductor region is provided between the type well region and the insulator, and an n-type second semiconductor region is provided between the p-type well region and the insulator in the second element forming region of the semiconductor layer.
In a semiconductor integrated circuit device in which each of the semiconductor regions is formed, the n-type first semiconductor region and the n-type second semiconductor region are set to the same potential. . 2. The semiconductor integrated circuit device according to claim 1, wherein the n-type second semiconductor region is set to have an impurity concentration lower than that of the n-type first semiconductor region. 3. Between the n-type first semiconductor region of the first element formation region of the semiconductor layer and the insulator, an n-type first semiconductor region having a lower impurity concentration than that of the first semiconductor region is set. The semiconductor integrated circuit device according to claim 1, wherein three semiconductor regions are formed.