JP2003046087A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, having improved operating speed and reliability by suppressing increase in the area and fixing the body potential of a MOSFET in the semiconductor integrated circuit. SOLUTION: The semiconductor integrated circuit comprises a plurality of MOSFETs, each formed on an SOI substrate and consisting of a gate electrode 1 formed on a substrate, a source and drain region 2 containing n-type impurity, and a body region containing p-type impurity formed below the gate electrode in the substrate; a body contact 8; a low-concentration p-type region 6 interposed between the body regions of the MOSFETs; and a connection region 7 interposed between the low-concentration p-type region 6 and the body contact 8 in the substrate. Since the body region 9 is connected to the body contact 8, its potential is fixed, and the operating speed is increased. Moreover, since one body contact is formed with respect to the plurality of body regions, increase in area can be prevented.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an SOI (Silicon
On Insulator) The present invention relates to a semiconductor integrated circuit formed on a substrate, and more particularly to a semiconductor integrated circuit functioning as a memory device.

[0002]

2. Description of the Related Art Recently, in place of the conventional bulk Si substrate,
SOI (Silicon On) with an insulator layer embedded in a Si substrate
Research and development for constructing semiconductor integrated circuits on an (Insulator) substrate has been actively conducted. MOS SOI substrate
When used as a substrate for a FET, the bottom surface of the source and drain regions of the MOSFET has a thick buried oxide film layer (Bu
Since it is in contact with the ried oxide (BOX layer), the conventional bulk S
Compared with the case of using the i substrate, the junction capacitance between the source region and the drain region and the surrounding region is 1/10 to 1 /
There is an advantage that it is reduced to about 7. Moreover, since the MOSFETs adjacent to each other are completely insulated and separated,
It also has the advantage that latch-up does not occur and it is less susceptible to substrate noise. MO using SOI as a substrate
SFET (hereinafter referred to as SOI MOSFET),
Fully depleted MOSFET (FD type M), in which the region under the channel is completely depleted during operation.
OSFET) and a partial depletion type MOSFET (Partial Depletion MOSFET) where a region called a body that is not depleted is formed under the channel.
ly Depleted MOSFET: PD type MOSFET).

Of these, the FD-type MOSFET is required to form an extremely thin surface oxide film layer with a uniform thickness, and it is becoming difficult to manufacture it with the miniaturization of the process. Is a PD type MOSFET.

However, when the PD type MOSFET is used in a circuit, the potential of the body is in an electrically floating state, and therefore the potential of the body changes during the operation of the circuit, which changes the characteristics of the MOSFET. , A characteristic history effect occurs in which the operation delay time of the circuit changes. Therefore, it is difficult to estimate the operation time when designing the circuit. Furthermore, under the condition of the same threshold voltage, a MOS using a bulk Si substrate
As compared with an FET (hereinafter referred to as a bulk MOSFET), there is a problem that the saturation current is reduced by 20% or more. In the SOI MOSFET, the voltage applied between the body and the source is higher than that in the bulk MOSFET, so that it is necessary to increase the impurity concentration of the channel in order to obtain the same threshold voltage, so that electrons (or holes) It is thought that mobility will decrease. As a result, the operation time of the circuit becomes slower than in the case where the bulk MOSFET is used. Particularly in a large-capacity memory, a large parasitic capacitance is generated in the bit line, resulting in a large decrease in performance.

Since the body potential is in a floating state,
There is also the problem that a parasitic bipolar current flows between the drain and source. Here, the parasitic bipolar current is the current flowing between the source and drain in a MOSFET that is originally off when the parasitic bipolar transistor generated between the source, body and drain turns on when the potential of the drain or source changes. That is.
The parasitic bipolar transistor causes a decrease in operation speed and a malfunction in a circuit using a pass transistor structure.

In order to suppress the disadvantages due to the floating of the body potential, it is effective to form a body contact for fixing the body potential.

FIG. 8A is a plan view showing a conventional n-channel type SOI MOSFET provided with a body contact, FIG. 8B is a sectional view taken along line VIIIb-VIIIb, and FIG. 8C is a sectional view. , VIIIc-VIIIc sectional view.

As shown in FIG. 8C, the conventional SOI
The MOSFET includes a Si support substrate 113, a buried oxide film 112 formed on the Si support substrate 113, an element isolation insulating layer 111 provided on the buried oxide film 112 and surrounding the active region of the substrate, and a substrate. A gate oxide film 110 provided thereon, a gate electrode 101 made of polysilicon formed on the gate oxide film, and a gate electrode 101.
Of the gate contact 105 provided at the end of the gate electrode and the sidewall 100 provided on the side surface of the gate electrode 101.
And a drain region 10 formed on both sides of the gate electrode 101 in the active region of the substrate and containing a high concentration of n-type impurities.
2a and a source region 102b, a body region 109 formed directly below the gate electrode 101 in the active region and containing p-type impurities, a drain contact 104 made of a conductor provided on the drain region 102a, and a source region. And a source contact 103 provided on 102b. Further, as shown in FIGS. 8 (a) and 8 (b),
In the conventional SOI MOSFET, a connection region 107 containing a high concentration of p-type impurities is provided in a region of the active region in contact with one of the element isolation insulating layers 111, and a conductive region provided on the connection region 107. It has a body contact 108 made of a body, and a low concentration p-type region 106 containing a low concentration p-type impurity provided in the active region between the connection region 107 and the body region 109. Further, the width of the polysilicon at the end of the gate electrode 101 on the body contact 108 side is larger than the gate width between the source region 102b and the drain region 102a, which is due to the source region 102b and the drain region. 10
2a when impurities are implanted into the low concentration p-type region 106
This is because it is necessary to cover it with polysilicon so that n-type impurities are not implanted into.

Next, a mask ROM using MOSFETs
The structure of the circuit will be briefly described. FIG. 9 is a plan view showing a partial layout of a memory cell portion of a conventional mask ROM circuit formed on a bulk Si substrate. A mask ROM circuit using a PD type SOI process without body contact has the same layout.

As shown in FIG. 1, a conventional mask ROM circuit includes a bulk Si substrate and a word line 115a and a word line 1 which are provided above the bulk Si substrate and in parallel with each other.
15b, bit lines 117a, 117b, 117c, 117d orthogonal to the word lines 115a, 115b, a plurality of MOSFETs forming memory cells provided between the word lines 115a, 115b and the bulk Si substrate, and grounded. It has the ground line 116 connected.
Data is recorded in this memory cell depending on whether the drain terminals are connected or not connected to the corresponding bit lines.

According to the actual evaluation by the inventors, the power supply voltage is 1.8.
PD type SOI with 0.18 μm process under V condition and threshold value aligned with conventional mask ROM circuit with 1 Mb capacity
When the access time is compared with the mask ROM circuit composed of the MOSFET, the mask ROM circuit composed of the PD type SOI MOSFET has a result that the access time is extended by 30%. This is due to the SO
It is considered that the drive current decreased due to the floating body potential of the I MOSFET.

An SRAM (Static Random Access Memory) memory cell or the like can be cited as a memory cell having a MOSFET. The SRAM memory cell includes a bit line, an inverted bit line, a word line, an access transistor which is a MOSFET connected to each of the bit line and the inverted bit line and controlled by the word line, and between the two access transistors. And two CMOS inverter circuits connected to each other.

In the mask ROM circuit and the SRAM memory cell, when the SOI MOSFET is used as the access transistor, the operation time may be delayed as compared with the normal MOSFET. However, the body contact structure is used. Thus, the potential of the body region can be kept constant and the delay of the operation time can be suppressed. In addition, since the parasitic bipolar current is also suppressed, it is possible to avoid deterioration in operational reliability.

[0014]

However, in the conventional SOI MOSFET having the body contact,
As can be understood from FIGS. 8A to 8C, one S
Since one body contact is formed for each OI MOSFET, there is a problem that the layout area including the body contact is more than doubled as compared with the case where no body contact is provided. Therefore, a mask ROM circuit using this SOI MOSFET and an S
The area of the RAM memory cell is inevitably large, and it has been difficult to meet the demand for miniaturization of semiconductor devices.

An object of the present invention is to provide a means for fixing the potential of the body region of an SOI MOSFET in a semiconductor integrated circuit while suppressing an increase in the area of the device.
An object of the present invention is to provide a semiconductor integrated circuit formed on a substrate and having improved operation speed and operation reliability.

[0016]

A semiconductor integrated circuit of the present invention comprises an SOI substrate having a semiconductor layer on an insulating layer,
A gate electrode provided on the semiconductor layer, a body region of the first conductivity type provided below the gate electrode in the semiconductor layer, and a second region provided on both sides of the gate electrode in the semiconductor layer. A plurality of transistors each having a conductivity type source / drain region, a first conductivity type intermediate region interposed between body regions of the plurality of transistors in the semiconductor layer, and provided in the semiconductor layer, And a body contact region for fixing the potential of the body region connected to the body region of any one of the plurality of transistors.

Since the body contact is connected to the body of each transistor, the accumulation of carriers in the semiconductor layer can be suppressed, and the delay of the operation time due to the operation history of the transistor can be suppressed. Also,
Since one body contact is connected to the body regions of a plurality of transistors, the area can be significantly reduced compared to a semiconductor integrated circuit in which the body contact is provided for each transistor.

Further, since the gate electrodes of the plurality of transistors are integrally provided with each other, the gate electrodes serve as a mask during ion implantation for forming the source / drain regions. It is possible to prevent impurities of the second conductivity type from being mixed in, and the manufacturing process is facilitated.

Since the dimension in the gate length direction in the region between the bodies of the gate electrodes of the plurality of transistors is larger than the gate length of the transistors,
Mixing of the second conductivity type impurity contained in the source / drain regions into the intermediate region is prevented.

Further, a word line connected to the gate electrodes of the plurality of transistors, a bit line arranged to intersect the word line, a ground line for supplying a ground potential, and data can be held. A plurality of memory cells, wherein one of the source / drain regions of each transistor is connected to the bit line and the other is connected to the memory cell, and each transistor functions as an access transistor for controlling data input. By doing
Since the parasitic bipolar current is suppressed when the transistor is off, the operation reliability can be improved as compared with the conventional semiconductor integrated circuit. In addition, it is possible to increase the data transmission speed while suppressing an increase in cell area.

Since the memory cell is an SRAM memory cell having a flip-flop structure, it is possible to improve the speed of data input and output operations while suppressing an increase in cell area.

The transistor further has a word line connected to the gate electrodes of the plurality of transistors, a bit line intersecting with the word line, and a ground line for supplying a ground potential. By functioning as a memory cell of a mask ROM that stores data depending on whether or not one of the drain regions is connected to the bit line, it is possible to improve the data reading speed while suppressing an increase in cell area. it can.

The body contact region is connected to a voltage supply line other than the ground line, and the potential of the body region changes according to the voltage applied to the gate electrode of the transistor, so that, for example, a high voltage is applied to the transistor. When it is applied to the gate electrode, the potential of the body region is changed to near the pn junction potential (about 0.6 V).
Since the potential of the body region can be changed appropriately, the drive current can be increased and the operating speed of the semiconductor integrated circuit can be improved.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) FIG.
3D is a plan view showing the configuration of the memory unit of the mask ROM circuit according to the first embodiment of the present invention, FIG.
It is sectional drawing in the Ib-Ib line, sectional drawing in the Ic-Ic line, and sectional drawing in the Id-Id line.

As shown in FIGS. 3A to 3D, the mask ROM circuit of this embodiment has a Si support substrate 13 and a Si support substrate 13.
A buried oxide film 12 formed on the support substrate 13, an element isolation insulating film 11 that is in contact with the buried oxide film 12 and surrounds an active region, a gate oxide film 10 provided on the substrate,
A gate electrode 1 made of polysilicon formed on the gate oxide film 10 and drain regions 2a, 2b, 2c, 2d provided on both sides of the gate electrode 1 in the SOI substrate and containing high-concentration n-type impurities. And source regions 2e, 2f, 2
g, 2h and drain contacts 4a, 4b, 4 formed on the drain regions 2a, 2b, 2c, 2d, respectively.
c, 4d and source contacts 3a, 3b, 3c, 3 formed on the source regions 2e, 2f, 2g, 2h, respectively.
d, the gate contact 5 provided at one end of the gate electrode 1, and the body regions 9a, 9b, 9 located directly below the gate electrode 1 in the active region and existing at regular intervals.
c and 9d (hereinafter, body regions 9a to 9d are collectively referred to as body region 9) and the gate contact 5 of the SOI substrate from a conductor provided in a region on the opposite side with the gate electrode 1 interposed therebetween. And a connection region 7 formed in a region of the active region located below the body contact 8 and containing a low concentration of p-type impurities in the memory portion. Here, the MOSFET including the drain region 2a, the source region 2e and the body region 9a is a transistor m1, the MOSFET including the drain region 2b, the source region 2f and the body region 9b is a transistor m2, the drain region 2c, the source region 2g and the body region 9c. A MOSFET including a transistor m3 and a drain region 2
d, a source region 2h, and a body region 9d
Let T be a transistor m4. Further, low-concentration p-type regions 6a, 6b, 6c are formed in order between the body regions 9a, 9b, 9c, 9d of the active region, respectively, and between the body region 9d and the connection region 7. A low concentration p-type region 6d is formed in the.

Here, the structure of the mask ROM circuit of this embodiment is the mask ROM in the case where the body contact is not provided.
Compare with the circuit.

FIGS. 7A to 7D respectively show S in order.
A plan view showing a structure of a memory portion of a conventional mask ROM circuit formed on an OI substrate without taking a body contact, VI
It is sectional drawing in the Ib-VIIb line, sectional view in the VIIc-VIIc line, and sectional view in the VIId-VIId line.

From the comparison between FIG. 1A and FIG. 7A, the body region of each MOSFET is insulated by the insulating film in the memory portion of the conventional mask ROM circuit in which the body potential is not fixed. In the memory section of the mask ROM circuit of this embodiment, each MOSFET (transistor m1, m
2, m3, m4) body regions are connected by a low concentration p-type region.

That is, in the memory portion which constitutes the mask ROM circuit of this embodiment, an n-channel type PD type MOS formed on the SOI substrate and functioning as a memory cell is formed.
FETs are arranged at regular intervals, and the body regions of the four MOSFETs are low-concentration p-type regions 6a, 6b, 6c, 6d.
(Hereinafter, the low-concentration p-type regions 6a to 6d are collectively referred to as a low-concentration p-type region 6) and the connection region 7 is connected to the body contact 8. In the mask ROM circuit of this embodiment, the transistors m1 and m
The gate electrodes 2, 2, 3 and m4 are integrally provided.

The gate width of the region of the gate electrode 1 located above each low-concentration p-type region is preferably larger than the gate width of each MOSFET.
This is to protect the low concentration p-type region 6 from being implanted with n-type impurities when the n-type impurities are implanted into the source region and the drain region.

Next, FIG. 2 shows a mask ROM of this embodiment.
2 is a plan view showing a configuration of a memory unit in the circuit, and FIG.
It is a more detailed figure than (a). From the figure, in the mask ROM circuit of the present embodiment, MOSFETs 17a, 17b, 17c, 17d, 17 functioning as memory cells.
It can be seen that the source regions of e, 17f, 17g, and 17h are connected to the ground line 16, and the gate electrodes 1 and 1b are connected to the word line. In this way, the body region of each MOSFET and the ground line 1
Since 6 and 6 are connected via body contacts 8 and 8b, the potential of the body region can be fixed to the potential of the ground line.

Here, in the mask ROM of the present embodiment, it will be verified in detail that the change of the operation delay time of the circuit (characteristic history effect) does not occur due to the change of the body potential.

Minimum gate length is 0.18 μm, MO
In a process in which the minimum distance between SFETs is 0.26 μm, the thickness of the surface Si of the SOI substrate (the depth of the active region) is 150 nm, and the sheet resistance of the body region is 4 (kΩ / square), the gate width is 0.44 μm. There are 8 MOSF
When the body region of ET is electrically connected and body contacts are made at both ends of the body region, the resistance value Rb farthest from the body contact is Rb = 4 [kΩ / square] × (0.44 [μm ] +0.
26 [μm]) ÷ 0.18 [μm] × 4 [pieces] = 62.
It becomes 2 [kΩ]. Rb × Cb, where Cb is the total capacitance between the body region and the source region, the body region and the drain region, and the body region and the gate electrode of the MOSFET.
If the time constant of is sufficiently shorter than the clock cycle, the potential of the body region is always kept constant before the rise of the word line, so that the above-mentioned characteristic history effect does not occur.

Under the above-mentioned conditions, the magnitude of the change in the body potential when the gate potential was changed was estimated by a circuit simulation. The change in the body region potential was about 50 mV at maximum and before the gate potential was changed. It took about 0.5 ns to return to the body potential. Therefore, it is understood that the characteristic history effect does not occur in the operation at the clock frequency of several hundred MHz.

As described above, the mask ROM of this embodiment
In the circuit, four MOs functioning as memory cells
Since the body region of the SFET is electrically connected to the common body contact, one MOSFET is used.
Conventional mask ROM with two body contacts
The area can be significantly reduced as compared with the circuit.

Further, by making the body contact, the potential of the body region can be kept constant, and the reduction of the drive current due to the operation history can be effectively suppressed. As a result, the data read speed can be improved.

Further, in this embodiment, four MOSs are used.
Although an example has been given in which one body contact common to the body region of the FET is taken, if two or more MOSFETs have a common body contact, the area can be reduced as compared with the conventional mask ROM circuit. For example, 8
Since the body regions of the six MOSFETs can be connected to a common body contact, in that case, the area of the mask ROM circuit can be further reduced.

Further, in the memory cell in the mask ROM circuit of this embodiment, the low concentration p-type regions 6a, 6b, 6 are formed.
The concentration of the p-type impurity contained in c, 6d, 6e, 6f, 6g, 6h may be the same as the concentration of the p-type impurity contained in the body region 9, or a higher concentration may be used to reduce the resistance. It doesn't matter.

Further, in this embodiment, an n-channel type MOS is used.
Although an example using a FET is shown, p-channel type MOSFE
A mask ROM circuit can also be created using T.
However, the MOSFETs sharing the body contact must have the same conductivity type.

In the case of an n-channel MOSFET,
Since the body potential is often fixed to the same potential as the source terminal, the line for fixing the body potential is the same as the ground line in this embodiment, but these are separate and the body potential is other than the ground potential. The structure may be controlled to. In the case of adopting this structure, the drive current of the memory cell can be increased by controlling the body potential corresponding to the memory cell selected by the word line to be equal to or near the potential of the word line. The read speed of the memory can be further improved.

In the MOSFET in the mask ROM circuit of this embodiment, a plurality of adjacent MOSFETs are used.
Adjacent body regions are connected to each other by polysilicon containing low-concentration p-type impurities.
Parasitic MOSFETs are formed between the drain and drain of T and between the drain and source. However, this parasitic M
Since the OSFET works in a direction to help discharge the parasitic capacitance of the bit line, it does not hinder the operation of the MOSFET.

In the description of this embodiment, the MOSFET
Although the example of the semiconductor device using is described, the present invention can be similarly applied to a MISFET having a gate insulating film other than an oxide film.

Next, a method of manufacturing the mask ROM circuit of this embodiment will be described with reference to the drawings.

3A to 3C and 4A to 4C.
FIG. 3C is a three-dimensional cross-sectional view for explaining the manufacturing process of the mask ROM circuit of this embodiment shown in FIG.

First, in the step shown in FIG. 3A, by implanting oxygen ions into a Si wafer and then annealing it, Si
A buried oxide film 12 is formed on the Si support substrate 13 in the wafer.
To form. As a result, the Si support substrate 13, the buried oxide film 12, and the surface Si layer 2 on the buried oxide film 12.
An SOI substrate composed of 8 is formed.

Next, in a step shown in FIG. 3B, a group III impurity ion such as boron (B) is added to the surface Si layer 28.
And the surface Si layer 28 is changed to the low concentration p-type region 6 ′. Then, the region for forming the element isolation insulating film in the low-concentration p-type region 6'is etched to form a trench. After that, a silicon oxide film is deposited by the CVD method, and then the surface is polished and flattened by the CMP method to form the element isolation insulating film 11 surrounding the low concentration p-type region 6 ′.

Next, in the step shown in FIG. 3C, a silicon oxide film is formed on the substrate by thermal oxidation of the substrate, and then a polysilicon layer is deposited on the silicon oxide film. Then, the silicon oxide film and the polysilicon layer are dry-etched using an etching mask to form the gate oxide film 10 extending over the low-concentration p-type region 6 ′ and the element isolation insulating film 11. The gate electrode 1 is formed on the gate oxide film 10.

At this time, each MOS of the gate electrode 1
The gate width of the region located between the FET is MOSFET
It should be larger than the gate width. As a result, FIG.
Even when a mask shift or the like occurs in the next step shown in (a), it is possible to prevent the ion implantation from being performed in regions other than the source region and the drain region, and in the low concentration p-type region 6 ′, below the gate electrode 1. It is possible to prevent n-type ions from entering the region located at.

Next, in the step shown in FIG. 4A, a resist 26a which covers the substrate and opens the n-type ion implantation region 25 is formed on the substrate, and then arsenic (As) is formed in the n-type ion implantation region 25. By implanting n-type impurities such as ions, drain regions 2a, 2b, 2c, 2d and source regions 2e, 2f, 2g, 2h are formed on both sides of the gate electrode 1 in the low-concentration p-type region 6 '. (Source region not shown). After that, the resist 26a is removed. As a result, a plurality of MOSFETs are formed on the SOI substrate.

Next, in the step shown in FIG. 4B, a resist 26b which covers the substrate and has an opening in the p-type ion implantation region of the low-concentration p-type region 6'is formed, and a p-type impurity such as boron is formed. Ions are implanted to form a connection region 7 containing high-concentration boron at the end of the low-concentration p-type region 6 '.

Here, among the regions excluding the connection region 7 from the low-concentration p-type region 6 ', the regions sandwiched by the pair of source regions and drain regions are body regions 9a, 9b, 9c ,.
9d, and the region sandwiched between the body regions is the low-concentration p-type region 6.

Next, in a step shown in FIG. 4C, after depositing an interlayer insulating film (not shown) on the substrate, a contact hole and a drain region for connecting the word line 15 and the gate electrode 1 are formed. 2a, 2b, 2c, 2d and bit line 14a,
Contact holes for connecting 14b, 14c, 14d respectively, and contact holes for connecting the connection region 7 and the ground line 16 are opened. After that, each contact hole is filled with a conductor to form a ground line 16 made of metal. Then, after depositing an interlayer insulating film again, contact holes for connecting the word line 15 and the gate electrode 1 and drain regions 2a, 2b,
2c, 2d and bit lines 14a, 14b, 14c, 14d
And a contact hole for connecting each of them with each other. Next, the interlayer insulating film is deposited and each contact hole is formed again. Then, after filling each contact hole with a conductor, the bit lines 14a, 14 made of metal are formed.
b, 14c and 14d are formed respectively. Then, after depositing an interlayer insulating film, a contact hole for connecting the word line 15 and the gate electrode 1 is formed, and this is filled with a conductor to form a plug. Next, the bit lines 14a, 14b, 14c, 1 made of metal, which are connected to this plug, are formed.
4d (hereinafter referred to as bit line 14 when collectively representing bit lines 14a, 14b, 14c, 14d) are formed.

Although the bit line 14 is formed of a three-layer metal and the word line 15 is formed of a four-layer metal here, the number of layers of the bit line 14 and the word line 15 may be appropriately changed.

In the mask ROM of this embodiment, the presence / absence of the connection between the drain of the MOSFET and the bit line is created by this step, and this is recorded as data.

In the mask ROM of this embodiment, the substrate is oxygen-implanted (SIMOX method: Separation b).
Although an SOI substrate manufactured by using y-implanted oxygen was used, an SO manufactured by a method (bonding method) of bonding a Si substrate on a substrate having an oxide film formed on its surface
An I substrate may be used.

In the process shown in FIG. 3B, the low concentration p
The p-type ion concentration may be relatively increased by implanting p-type ions again into the portion of the mold region 6 ′ that will be the body region.

In the step shown in FIG. 3C, four M
The gate electrode 1 of the OSFET is integrally formed of polysilicon, but each MOSFET may have a structure having a separate gate electrode. At this time, when the n-type impurity is introduced in the step shown in FIG.
It is necessary to provide a resist on the exposed portion of the substrate between the gate electrodes so as not to enter the mold region 6.

(Second Embodiment) FIGS. 5A and 5B.
Are circuit diagrams respectively showing a configuration of an SRAM memory cell portion of a semiconductor integrated circuit according to the second embodiment of the present invention, and S of a semiconductor integrated circuit according to the second embodiment of the present invention.
FIG. 3 is a plan view showing a layout of a RAM memory cell section.

Further, FIGS. 6A and 6B respectively show SRA of the semiconductor integrated circuit in the second embodiment of the present invention.
A circuit diagram showing a configuration of an M memory cell portion, and a second embodiment of the present invention.
3 is a plan view showing a simplified layout of the SRAM memory cell portion of the semiconductor integrated circuit in the embodiment of FIG.

The semiconductor integrated circuit of this embodiment is formed on an SOI substrate and is composed of an SRAM memory cell using a MOSFET as an access transistor.

As shown in FIG. 5A, the SRAM memory cell in the semiconductor integrated circuit of this embodiment has the bit line 1
8, 19 and the word line 20, and the source region is the power supply line 21.
And a p-channel transistor mp1 connected to the source region, and an n-channel transistor mn1 having a source region connected to the ground line 22 and a drain region connected to the drain region of the transistor mp1 via the node N3.
And a p-channel transistor mp2 whose source region is connected to the power supply line 21 and the source of the transistor mp1.
And an n-channel transistor m whose source region is connected to the ground line 22 and whose drain region is connected to the drain region of the transistor mp2 via the node N2.
n2 and n-channel type access transistor mn3
and mn4.

The transistor mn1 and the transistor mp1 form a CMOS inverter circuit, and the gates of the transistor mn1 and the transistor mp1 are connected to each other via the node N1. Similarly, the transistor mn2 and the transistor mp2 also form a CMOS inverter, and the gates of the transistor mn2 and the transistor mp2 are connected to each other via the node N4. Further, the node N1 and the node N2 are connected to each other, and the node N3 and the node N4 are also connected to each other. That is, the two CMOS inverters are connected to each other and function as a latch circuit.
Is formed.

The access transistor mn3 and the access transistor mn4 control the input / output of data in the memory cell, and both ON / OFF thereof are controlled by the word line 20. Access transistor mn
When N3 is on, the node N1 and the bit line 18 are electrically connected, and when the access transistor mn4 is on, the node N4 and the bit line 19 are electrically connected.

Further, as shown in FIGS. 5B and 6B, in the semiconductor integrated circuit of this embodiment, a large number of SRAMs are provided.
Memory cells are arranged side by side, and access transistors mn3 and mn4 are formed adjacent to each other while sharing the same gate. The access transistors of the plurality of SRAM memory cells are access transistors mn3, m.
The body regions of the plurality of access transistors including the access transistors mn3 and mn4, which are provided sharing the gate with n4, are electrically connected to the ground line 22 via the body contact 8 by the low concentration p-type region. There is. Here, the reference numerals shown in FIG.
It corresponds to the code in (a).

With this structure, the potential of the body region of each access transistor does not depend on the operation history, but the ground line 22.
Since the voltage is maintained at, the reduction of the drive current due to the operation history is effectively suppressed, and as a result, the speed of data writing and reading operations can be increased.

In addition, by fixing the body potential of the access transistor, the parasitic bipolar current does not flow when the access transistor is off, so that malfunctions such as malfunction of the semiconductor integrated circuit are suppressed and the reliability of the operation is improved. Is improved.

Further, in the semiconductor integrated circuit of the present embodiment, one body contact common to the body regions of two or more access transistors is taken, so that one body contact is provided for each transistor. Compared with semiconductor integrated circuits, the area can be significantly reduced, which is advantageous for high integration.

Also in the semiconductor integrated circuit of this embodiment,
Although it is possible to connect the body regions of a large number of transistors such as 8 and 16 to one body contact,
In order to suppress the characteristic history effect, the sum of the capacitances between the body region and the source region, the body region and the drain region, and the body region and the gate of the access transistor is Cb, and the resistance from the body contact to the furthest point is the resistance. When the value is Rb, the time constant of Rb × Cb needs to be sufficiently shorter than the clock cycle.

In the semiconductor device of this embodiment,
The access transistor is an n-channel transistor, but it may be a p-channel transistor.

Further, in the semiconductor integrated circuit of the present embodiment, the line for fixing the body potential is the same as the ground line, but these are separated and the body potential is controlled to a value other than the ground potential. I don't mind. In the case of adopting this structure, for example, by controlling the body potential corresponding to the memory cell selected by the word line from the ground potential or the negative potential to a positive potential equal to or lower than the pn junction potential (about 0.6 V), the memory cell is driven. The current can be increased and the data input / output speed can be further increased. Alternatively, by setting the body potential corresponding to the memory cell not selected by the word line to 0 or less, the MOS
The leak current from the FET can be reduced, and the data retention can be improved.

In the present embodiment, the example of the semiconductor integrated circuit including the SRAM memory cell in which the CMOS inverter is combined is given.
A structure using a resistance element may be used instead of the channel MOSFET.

Further, in the semiconductor integrated circuit of this embodiment, the MOSFET formed on the SOI substrate is replaced by the SRA.
It was used as an access transistor of the M memory cell.
As long as the MOSFET is used as a pass transistor, it can be used without being limited to the SRAM memory cell.

In addition to this, the semiconductor integrated circuit of the present invention is a DRAM in which a plurality of MOSFETs are arranged in parallel on the circuit.
(Dynamic Random Access Memory) Memory cells and FeRA
It may be composed of M memory cells or the like.

[0074]

According to the semiconductor integrated circuit of the present invention, the SO
By electrically connecting the body regions of a plurality of PD-type MOSFETs formed on the I substrate to one body contact, it becomes possible to fix the body potential while suppressing an increase in area, and it is possible to reduce the operating speed depending on the operation history. The decrease can be effectively suppressed.

[Brief description of drawings]

1A to 1D are, respectively, a plan view showing a configuration of a memory section of a mask ROM circuit according to a first embodiment of the present invention, a cross-sectional view taken along line Ib-Ib, and Ic-.
It is sectional drawing in the Ic line, and sectional drawing in the Id-Id line.

FIG. 2 is a mask ROM according to the first embodiment of the present invention.
It is a top view showing the detailed composition of the memory part of a circuit.

3A to 3C are three-dimensional cross-sectional views showing up to the step of forming a gate electrode in the process of manufacturing the mask ROM circuit according to the first embodiment of the present invention.

FIG. 4A to FIG. 4C are three-dimensional cross-sectional views showing a mask ROM circuit manufacturing process of the first embodiment of the present invention up to the step of forming metal wiring.

5A and 5B are respectively a circuit diagram showing a configuration of an SRAM memory cell portion of a semiconductor integrated circuit according to a second embodiment of the present invention, and a semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 6 is a plan view showing the layout of the SRAM memory cell portion of the circuit.

6A and 6B are respectively a circuit diagram showing a configuration of an SRAM memory cell portion of a semiconductor integrated circuit according to a second embodiment of the present invention, and a semiconductor integrated circuit according to the second embodiment of the present invention. It is a top view which simplifies and shows the layout of the SRAM memory cell part of a circuit.

7A to 7D are plan views showing the structure of a memory portion of a conventional mask ROM circuit formed on an SOI substrate without a body contact, VIIb-VII, respectively.
sectional view taken along line b, sectional view taken along line VIIc-VIIc,
FIG. 7 is a sectional view taken along line VIId-VIId.

8A to 8C are, respectively, a plan view showing a conventional MOSFET with a body contact, VIII.
It is sectional drawing in the b-VIIIb line, and sectional drawing in the VIIIc-VIIIc line.

FIG. 9 is a conventional mask R formed on a bulk Si substrate.
FIG. 6 is a plan view showing a partial layout of a memory cell portion of the OM circuit.

[Explanation of symbols]

1 Gate electrode 2a, 2b, 2c, 2d drain region 2e, 2f, 2g, 2h source region 3a, 3b, 3c, 3d source contact 4a, 4b, 4c, 4d drain contact 5 gate contacts 6,6a, 6b, 6c, 6d Low concentration p-type region 7 connection area 8 body contact 9, 9a, 9b, 9c, 9d body region 10 Gate oxide film 11 Insulation film for element isolation 12 Embedded oxide film 13 Si support substrate 14, 18, 19 bit lines 15,20 word lines 16,22 ground wire 17 MOSFET 21 power line 23 flip-flops 25 n-type ion implantation region 26a, 26b resist 28 Surface Si layer m1, m2, m3, m4 transistor mn1, mn2, mp1, mp2 transistors mn3, mn4 access transistor N1, N2, N3, N4 nodes

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F083 BS02 BS27 CR01 CR03 HA02                       LA12 LA16 LA17 LA18 NA01                 5F110 AA04 AA15 BB05 BB07 BB08                       CC02 DD05 DD13 EE09 EE24                       FF02 FF23 GG02 GG12 GG60                       HJ01 HJ13 NN62 QQ11 QQ19

Claims (7)

[Claims] 1. An SO comprising a semiconductor layer provided on an insulating layer.
An I substrate, a gate electrode provided on the semiconductor layer, a body region of the first conductivity type provided below the gate electrode in the semiconductor layer, and provided on both sides of the gate electrode in the semiconductor layer. A plurality of transistors each having a second conductivity type source / drain region formed therein, a first conductivity type intermediate region interposed between the body regions of the plurality of transistors in the semiconductor layer, and the semiconductor layer. A semiconductor integrated circuit provided with a body contact region for fixing a potential of a body region connected to a body region of any one of the plurality of transistors. 2. The semiconductor integrated circuit according to claim 1, wherein the gate electrodes of the plurality of transistors are integrally provided with each other. 3. The semiconductor integrated circuit according to claim 2, wherein a dimension of the gate electrodes of the plurality of transistors in a region between the bodies in a gate length direction is larger than a gate length of each of the transistors. Integrated semiconductor circuit. 4. The semiconductor integrated circuit according to claim 1, wherein a word line connected to gate electrodes of the plurality of transistors and a bit arranged to intersect the word line. Line, a ground line for supplying a ground potential, and a plurality of memory cells capable of holding data. One of the source / drain regions of each transistor is the bit line, and the other is the memory cell. A semiconductor integrated circuit characterized in that each of the transistors functions as an access transistor for controlling data input. 5. The semiconductor integrated circuit according to claim 4, wherein the memory cell has an SRA having a flip-flop structure.
A semiconductor integrated circuit comprising M memory cells. 6. The semiconductor integrated circuit according to claim 1, wherein a word line connected to the gate electrodes of the plurality of transistors and a bit arranged to intersect the word line. Line and a ground line for supplying a ground potential, and the transistor functions as a memory cell of a mask ROM that stores data depending on whether one of the source / drain regions is connected to the bit line. A semiconductor integrated circuit comprising: 7. The semiconductor integrated circuit according to claim 4, wherein the body contact region is connected to a voltage supply line other than the ground line and applied to a gate electrode of the transistor. A semiconductor integrated circuit characterized in that the potential of the body region changes according to a voltage.