JPH0831925A - Housing container for semiconductor device and test method of semiconductor device - Google Patents

Housing container for semiconductor device and test method of semiconductor device

Info

Publication number
JPH0831925A
JPH0831925A JP16358694A JP16358694A JPH0831925A JP H0831925 A JPH0831925 A JP H0831925A JP 16358694 A JP16358694 A JP 16358694A JP 16358694 A JP16358694 A JP 16358694A JP H0831925 A JPH0831925 A JP H0831925A
Authority
JP
Japan
Prior art keywords
semiconductor device
container
storage container
lead
housing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16358694A
Other languages
Japanese (ja)
Inventor
Hideyasu Hashiba
英靖 橋場
Keiichi Sasamura
計一 笹村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16358694A priority Critical patent/JPH0831925A/en
Publication of JPH0831925A publication Critical patent/JPH0831925A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Packaging Frangible Articles (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To obtain a test method which prevents a lead from being deformed and whose testing efficiency is enhanced by a method wherein an IC can be tested while housed in a container. CONSTITUTION:The housing container for a semiconductor device is provided with a housing part for the semiconductor device 4, with opening parts i2 which are formed in positions corresponding to leads for the housed semiconductor device and with protrusions 3 which are formed on a face on the opposite side of a face, on which the housing part has been formed, and which press the leads for the semiconductor device on the lower side when the housing container is stacked. The device is housed in the housing container, a plurality of housing containers are stacked, contact pins 5 are connected to the leads through the opening parts and the semiconductor device is tested.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は集積回路装置等の半導体
装置の製造工程中及び出荷時に使用される半導体装置の
収納容器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a container for a semiconductor device used during the manufacturing process of semiconductor devices such as integrated circuit devices and during shipping.

【0002】[0002]

【従来の技術】従来の集積回路装置(IC)の運搬に用いら
れる収納容器は,図3に示されるような構造を持つ。
2. Description of the Related Art A conventional container used for carrying an integrated circuit device (IC) has a structure as shown in FIG.

【0003】図3(A) 〜(E) は収納容器の従来例の説明
図である。図3(A) は収納しようとするICの断面図, 図
3(B),(C) はICを収納した容器のIC1個分に対応する断
面図,図3(D) は複数個のICを収納でき, 積層可能な収
納容器の斜視図, 図3(E) はその収納容器を積層した斜
視図である。
FIGS. 3A to 3E are explanatory views of a conventional example of a storage container. 3A is a cross-sectional view of an IC to be stored, FIGS. 3B and 3C are cross-sectional views corresponding to one IC in a container containing ICs, and FIG. 3D is a plurality of ICs. FIG. 3 (E) is a perspective view of a stackable storage container that can store and stack the storage containers.

【0004】図において,31A は収納容器, 31B, 31Cは
収納容器の蓋, 32は収納しようとするIC, 41は複数のIC
を積層できる収納容器, 42はICの収納部 (凹部) であ
る。収納しようとする対象のICのパッケージは, 4方向
にピン(リード)が形成されている平型のQFP (Quad Fl
at Package), 小型のデュアルインラインパッケージの
SOP (Small Outline Package) 等である。
In the figure, 31A is a storage container, 31B and 31C are storage container lids, 32 is an IC to be stored, and 41 is a plurality of ICs.
The storage container 42 in which the ICs can be stacked is a storage part (recess) of the IC. The target IC package is a flat QFP (Quad Fl) with pins (leads) formed in four directions.
at Package), a small dual inline package
For example, SOP (Small Outline Package).

【0005】[0005]

【発明が解決しようとする課題】最近のICは高集積化に
伴い, リード数は増えそのファインピッチ化の影響で脆
弱化している。そのため,ICを収納容器から取り出して
試験装置のソケットに挿入する際に, リードを変形させ
る等の障害がしばしば発生する。リードが変形するとIC
をプリント基板に実装する際に, 例えばはんだ付け不良
等の問題が生ずる。
Recently, ICs have been vulnerable due to the increase in the number of leads with the increase in integration density due to the fine pitch. Therefore, when the IC is taken out from the container and inserted into the socket of the test equipment, there are often problems such as deformation of the leads. IC when lead deforms
When mounting the IC on a printed circuit board, problems such as poor soldering occur.

【0006】本発明はICを容器に収納したままでICの試
験が行えるようにして,リード変形を防止し,試験効率
を向上することを目的とする。
An object of the present invention is to prevent the lead from being deformed and to improve the test efficiency by allowing the IC test to be performed with the IC stored in the container.

【0007】[0007]

【課題を解決するための手段】上記課題の解決は, 1)半導体装置の収納部と, 収納した該半導体装置のリ
ードに相当する部位に形成された開口部と,該収納部が
形成された面の反対側の面に形成され且つ収納容器が積
層された際に下側に存在する半導体装置のリードを押さ
える突起とを有する半導体装置の収納容器,あるいは 2)前記1記載の収納容器に半導体装置を収納して複数
枚積層し,該開口部を通じてコンタクトピンを該リード
に接続して該半導体装置の試験を行う半導体装置の試験
方法により達成される。
Means for Solving the Problems To solve the above-mentioned problems, 1) a housing portion for a semiconductor device, an opening formed at a portion corresponding to the lead of the semiconductor device housed therein, and the housing portion are formed. A semiconductor device storage container having a protrusion formed on the surface opposite to the surface and holding the leads of the semiconductor device existing underneath when the storage containers are stacked, or 2) The semiconductor is added to the storage container described in 1 above. This is achieved by a semiconductor device testing method in which a plurality of devices are housed and stacked, and a contact pin is connected to the lead through the opening to test the semiconductor device.

【0008】[0008]

【作用】本発明は収納容器のリード相当部を開口し,外
部よりこの開口を通じてコンタクトピンを差し込んでIC
の特性を測定するようにしているため,ICを容器から取
り出す必要もなくなるのでリードを変形させることもな
く, 且つ試験工数も低減できる (図1参照)。
According to the present invention, the lead-corresponding portion of the storage container is opened, and the contact pin is inserted from the outside through this opening.
Since the characteristics are measured, it is not necessary to take out the IC from the container, so the leads are not deformed and the test man-hour can be reduced (see Fig. 1).

【0009】この際, 上側に積層される容器の下面に形
成された突起はリードのコンタクト部をコンタクトピン
の反対側から押さえてリードが変形しないようにし,且
つコンタクトピンとリードの接触を確実にすると共に,
この突起の斜面でICの位置ずれを防止している。
At this time, the protrusion formed on the lower surface of the container stacked on the upper side presses the contact portion of the lead from the side opposite to the contact pin to prevent the lead from being deformed and ensures the contact between the contact pin and the lead. With
The slope of this protrusion prevents displacement of the IC.

【0010】[0010]

【実施例】図1は本発明の実施例の説明図である。図は
テスタボード 6に植え込まれたコンタクトピン 5に収納
容器1Aの開口部 2が一致するように位置合わせして収納
容器1A, 1B, ・・・をテスタボード上に載せた状態を示
す断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an illustration of an embodiment of the present invention. The figure shows a cross-section of the tester board 6 with the contact pins 5 implanted in the tester board 6 aligned with the openings 2 of the storage container 1A and the storage containers 1A, 1B, ... placed on the tester board. It is a figure.

【0011】この際, 積層される上側の収納容器1Bの下
面に形成された突起 3は下側の収納容器1Aに収納された
ICのリードのコンタクト部をコンタクトピンの反対側か
ら押さえ, 突起の斜面3Aで当該ICの位置ずれを防止して
いる。
At this time, the protrusions 3 formed on the lower surface of the upper storage container 1B to be stacked are stored in the lower storage container 1A.
The contact portion of the IC lead is pressed from the opposite side of the contact pin, and the slope 3A of the protrusion prevents displacement of the IC.

【0012】図2(A) 〜(C) は実施例の収納容器の構成
の説明図である。図2(A) はSOP タイプのICを実施例の
収納容器 1に収容した状態を示す斜視図である。図2
(B) は収納容器にリードと接触するための開口 2が形成
された状態を示す図で, 収納容器の下面には, その下側
に存在するICの特性を確実に試験できるように突起 3を
設けている。また,この突起の斜面3Aで当該ICの位置ず
れを防止している。
2 (A) to 2 (C) are explanatory views of the construction of the storage container of the embodiment. FIG. 2A is a perspective view showing a state in which an SOP type IC is stored in the storage container 1 of the embodiment. Figure 2
(B) is a diagram showing a state in which the opening 2 for contacting the lead is formed in the container, and the protrusion 3 is provided on the bottom surface of the container so that the characteristics of the IC underneath can be surely tested. Is provided. In addition, the slope 3A of this protrusion prevents displacement of the IC.

【0013】図2(C) はICの電気的特性をより確実に試
験できるように開口 2に仕切りを設けた例である。この
仕切りにより, 隣接するコンタクトピンの接触を防止す
ることができる。
FIG. 2C shows an example in which a partition is provided in the opening 2 so that the electrical characteristics of the IC can be tested more reliably. This partition can prevent contact between adjacent contact pins.

【0014】つぎに,実施例の収納容器に収納されたIC
の試験法について説明する。テスタボードはIC1個分の
ピン配列に対応して植え込まれたコンタクトピンが設け
られ,各コンタクトピンは測定器に接続される。テスタ
ボードまたは収納容器を順次ステップ送りして収納され
たICを順に測定する。
Next, the IC stored in the storage container of the embodiment
The test method will be described. The tester board is provided with contact pins implanted corresponding to the pin arrangement for one IC, and each contact pin is connected to the measuring instrument. The tester board or storage container is sequentially stepped to measure the stored ICs in order.

【0015】また,収納容器は複数個のIC収納部がある
ため, 収納容器1枚分に相当するテスタボードを作製し
て,一度に収納容器1枚分のICの試験を実施することも
できる。
Further, since the storage container has a plurality of IC storage portions, it is possible to fabricate a tester board corresponding to one storage container and perform an IC test for one storage container at a time. .

【0016】なお,収納容器は通常プラスチックで作製
されるため,かなりの重量があるので,リードとコンタ
クトピンの圧接圧力が不足することはないが,そのおそ
れがあるときは最上段の収納容器の上に適当な重量物を
載せるようにするとよい。
Since the storage container is usually made of plastic and therefore has a considerable weight, the pressure contact pressure between the lead and the contact pin does not become insufficient. It is advisable to place an appropriate weight on top.

【0017】[0017]

【発明の効果】本発明によれば,収納容器を試験装置上
に積み重ねることにより, 容器内に収納されているICの
リードと試験装置のコンタクトピンが直接接続されるた
め,容器よりICを出し入れする必要がなくその結果リー
ドの変形がなくなる。従ってICの実装の際のはんだ付け
不良の発生を防止できる。
According to the present invention, by stacking the storage containers on the test device, the leads of the ICs stored in the container are directly connected to the contact pins of the test device. As a result, the lead is not deformed. Therefore, it is possible to prevent the occurrence of defective soldering when mounting the IC.

【0018】また,ICを容器に収納したまま試験できる
ため試験工数を低減でき,さらに収納容器1枚分の複数
のICを同時に試験することも可能であるため,一層試験
効率を上げることができる。
Further, since the IC can be tested while it is stored in the container, the number of test steps can be reduced, and a plurality of ICs for one storage container can be tested at the same time, so that the test efficiency can be further improved. .

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例の説明図FIG. 1 is an explanatory diagram of an embodiment of the present invention.

【図2】 実施例の収納容器の構成の説明図FIG. 2 is an explanatory diagram of the configuration of the storage container of the embodiment.

【図3】 収納容器の従来例の説明図FIG. 3 is an explanatory view of a conventional example of a storage container.

【符号の説明】[Explanation of symbols]

1, 1A, 1B 収納容器 2 開口部 3 突起 3A 突起の斜面 4 被収納IC 5 コンタクトピン 6 テスタボード 1, 1A, 1B Storage container 2 Opening 3 Projection 3A Slope of projection 4 IC to be stored 5 Contact pin 6 Tester board

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 G01R 31/28 H01L 21/66 D 7514−4M ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location G01R 31/28 H01L 21/66 D 7514-4M

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置の収納部と, 収納した該半導
体装置のリードに相当する部位に形成された開口部と,
該収納部が形成された面の反対側の面に形成され且つ収
納容器が積層された際に下側に存在する半導体装置のリ
ードを押さえる突起とを有することを特徴とする半導体
装置の収納容器。
1. A housing for a semiconductor device, an opening formed in a portion corresponding to a lead of the housed semiconductor device,
A storage container for a semiconductor device, which has a protrusion formed on a surface opposite to a surface on which the storage portion is formed and which holds a lead of a semiconductor device existing below when the storage container is stacked. .
【請求項2】 請求項1記載の収納容器に半導体装置を
収納して複数枚積層し,該開口部を通じてコンタクトピ
ンを該リードに接続して該半導体装置の試験を行うこと
を特徴とする半導体装置の試験方法。
2. A semiconductor device, wherein a plurality of semiconductor devices are stored in the storage container according to claim 1 and a plurality of semiconductor devices are stacked, and a contact pin is connected to the lead through the opening to test the semiconductor device. Equipment test method.
JP16358694A 1994-07-15 1994-07-15 Housing container for semiconductor device and test method of semiconductor device Pending JPH0831925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16358694A JPH0831925A (en) 1994-07-15 1994-07-15 Housing container for semiconductor device and test method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16358694A JPH0831925A (en) 1994-07-15 1994-07-15 Housing container for semiconductor device and test method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0831925A true JPH0831925A (en) 1996-02-02

Family

ID=15776737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16358694A Pending JPH0831925A (en) 1994-07-15 1994-07-15 Housing container for semiconductor device and test method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0831925A (en)

Similar Documents

Publication Publication Date Title
JP3690928B2 (en) Carrier for testing unpackaged chips
US6407566B1 (en) Test module for multi-chip module simulation testing of integrated circuit packages
US8242794B2 (en) Socket, and test apparatus and method using the socket
US6320398B1 (en) Semiconductor device testing apparatus
KR100270888B1 (en) Apparatus for manufacturing known good die
US5180974A (en) Semiconductor testing and shipping system
US5644247A (en) Test socket and method for producing known good dies using the test socket
CN112782548A (en) Antistatic test board of charging device model and test board applied to antistatic test board
US6824395B2 (en) Semiconductor device-socket
JPH0831925A (en) Housing container for semiconductor device and test method of semiconductor device
US5455518A (en) Test apparatus for integrated circuit die
WO2006022520A1 (en) Carrier and also test board for semiconductor device test
JPH1098083A (en) Test socket and electric characteristic test device
US6469257B2 (en) Integrated circuit packages
KR0141453B1 (en) Manufacturing method of known-good die
JPH0940068A (en) Test carrying tray for electronic parts and its testing method
JP2953930B2 (en) IC transport tray capable of performing electrical property test and method of electrical property test using the same
JP3256455B2 (en) socket
US6888158B2 (en) Bare chip carrier and method for manufacturing semiconductor device using the bare chip carrier
KR100729052B1 (en) Universal socket for testing a semiconductor package
JPH06180345A (en) Tray for housing semiconductor device and device and method for testing semiconductor device
US6968614B2 (en) Method for positioning an electronic module having a contact column array into a template
JPH09223725A (en) Semiconductor device
JP3052874B2 (en) Probe device for BGA type semiconductor device
JP2606309Y2 (en) IC socket

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20011106