JPH08316589A - Optical semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE: To form an electrode under a condition where open circuit is not present by providing a stripe clad layer of substantially trapezoidal cross-section having the (111) crystal face as the side face in a mesa stripe region and on a semiconductor buried layer. CONSTITUTION: p-type ohmic electrodes 7, an interconnection 8 and bonding pads 9 are patterned by bringing a glass mask into contact with the surface of a substrate. Since a planar surface extends except the region of stripe isolation groove 13, undue stress is not applied to a mesa stripe 12 located on the upper surface of an active layer 2 even during the patterning process and an electrode can be formed without causing any damage on the element (under a condition where open circuit is not present). Furthermore, since the bonding pad 9 is located at substantially same height as the mesa stripe 12, the element is protected against damage due to inadvertent contact with the mesa stripe 12 in the case of bonding an Au wire to the bonding pad 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an optical semiconductor device which can be used as a semiconductor optical modulator and a semiconductor laser device capable of coping with high speed modulation by an electric signal, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, research and development for increasing the capacity of trunk line optical communication systems have been actively conducted. In the direct modulation method in which the semiconductor laser serves both as an oscillator and a modulator, the light source can be composed of a single element, so that the system can be simplified and the cost can be reduced. In order to obtain a high speed modulation operation in a semiconductor laser, a high relaxation oscillation frequency is required. To this end, it is extremely important to reduce the threshold current and increase the output in addition to devising the laser medium itself such as forming the active layer from a multiple quantum well structure, and it is essential to reduce the leakage current. Becomes further,
A semiconductor laser in which the light intensity is directly modulated by an injection current is also required to have a small element parasitic capacitance.

On the other hand, in the external modulator system which has a small wavelength chirp during high-speed modulation and is capable of optical transmission over a long distance, an electroabsorption semiconductor optical modulator which can be monolithically integrated with a semiconductor laser serving as a light source. Is actively being developed. In this electroabsorption type semiconductor optical modulator, the optical absorption coefficient is controlled by externally applying a voltage signal. Here, in order to obtain a high extinction ratio, it is required that an electric field be uniformly applied to the light absorption layer. Furthermore, in order to realize large-capacity optical transmission, it is required that the element parasitic capacitance is small and high-speed modulation operation is possible.

In a conventional optical semiconductor device having a semiconductor-embedded structure used for a semiconductor laser and an optical modulator, the vicinity of an optical waveguide layer stripe of an element formed by flatly embedding it in a semiconductor substrate is processed into a narrow mesa shape. The element parasitic capacitance is reduced. FIG. 18 is a cross-sectional view perpendicular to the waveguide direction of a conventional optical semiconductor device having a semiconductor embedded structure. In the figure, 101 is an n-type InP substrate, 102 is an optical waveguide layer,
103 is an Fe-doped semi-insulating InP buried layer, 104
Is a p-type InP clad layer, 105 is a p-type InGaAs contact layer, 106 is a SiO ₂ film, and 107 is Au / Zn.
P-type ohmic electrode made of / Au, 108 is Ti / P
Wiring made of t / Au, 109 is a bonding pad made of Ti / Pt / Au, and 110 is AuGe / Ni / A
The n-type ohmic electrode which consists of u is shown.

This semiconductor device has an n-type InP substrate 101.
Forming a mesa stripe 111 including an active layer 102 on the
Both sides of the mesa stripe 111 are Fe-doped semi-insulating property I
After the nP layer 103 is buried, a p-type InP clad layer 104 and a p-type InGaAs contact layer 105 are sequentially formed thereon, and then isolation trenches 113 are formed in regions on both sides of the mesa stripe 111 by a wet etching method using a Br-based etchant. It is produced by forming.

[0006]

In the optical semiconductor device having the structure shown in FIG. 18, in order to reduce the element parasitic capacitance, it is necessary to process the vicinity of the mesa stripe 111 into a narrow mesa shape, and the separation groove 113 is formed. It is necessary to reduce the width of the mesa stripe 112 sandwiched between. However, the wet etching method using a Br-based etchant inevitably causes side etching, so that it is difficult to control the width of the mesa stripe 112 to be narrow. Furthermore, since the structure after the narrow mesa processing has poor flatness, it is difficult to form an electrode on the structure.

Further, as shown in FIG. 19, the isolation trench 113 is formed by a dry etching method without side etching.
When the element is formed and the element is subjected to the narrow mesa processing, the width of the mesa stripe 112 is easily controlled, but the side surface of the separation groove 113 is substantially perpendicular to the substrate surface. Therefore, the electrode forming step after the narrow mesa processing becomes extremely difficult. Even if the electrodes are formed, the wiring 1 is formed especially on the side surface of the separation groove 113.
However, there is a problem that the step wiring that connects the p-type ohmic electrode 107 formed on the mesa stripe 112 and the bonding pad 109 formed outside the separation groove 113 is difficult.

The present invention has been made in view of the above points, and it is possible to form electrodes without disconnection.
Moreover, it is an object of the present invention to provide an optical semiconductor device capable of accommodating high-speed modulation having a highly accurate narrow mesa shape and a method of manufacturing an optical semiconductor device in which the mesa width can be easily controlled and electrodes can be easily formed. .

[0009]

SUMMARY OF THE INVENTION The present invention comprises a mesa stripe having at least an optical waveguide layer formed thereon (100)
A semiconductor substrate having a crystal plane as a main surface, semiconductor embedding layers formed on both side surfaces of the mesa stripe, a mesa stripe region and the semiconductor embedding layer,
Provided is an optical semiconductor device comprising a clad layer having a stripe shape having a substantially trapezoidal cross section with a (111) crystal face as a side surface.

Further, according to the present invention, a step of forming a mesa stripe on which at least an optical waveguide layer is formed on a semiconductor substrate having a (100) crystal plane as a main surface, and a semiconductor burying layer on both side surfaces of the mesa stripe. Forming, a step of forming a growth blocking mask having a stripe-shaped opening including a region of the mesa stripe on the semiconductor burying layer, and selective growth using the growth blocking mask to form the mesa. And a step of forming a clad layer having a substantially trapezoidal cross section with a (111) crystal plane as a side surface on the stripe region and the semiconductor burying layer.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. In the optical semiconductor device of the present invention, the side surface of the optical waveguide layer is covered with the semiconductor layer having the current blocking effect. Therefore, when the optical semiconductor device is used as an optical modulator, when a voltage is applied from the outside, the light absorption layer included in the optical waveguide layer has a stacking direction (thickness direction).
It is possible to apply an electric field uniformly to a high extinction ratio. Also, when the optical semiconductor device is used as a semiconductor laser, it is possible to sufficiently reduce the leak current, and it is possible to obtain a low threshold operation and a high output operation.

Further, the clad layer is formed in a substantially trapezoidal cross section having a (111) crystal plane as a side surface. here,
The clad layer can be formed by the selective growth method, and its position and size can be arbitrarily determined by the selective growth blocking mask pattern formed in advance. That is, since the width of the clad layer can be determined by the interval between the selective growth preventing masks, the controllability thereof is extremely excellent. Further, since the side surface of the clad layer is a relatively gentle inclined surface defined by the (111) crystal plane, the electrode forming step can be easily performed.

In the present invention, when the optical semiconductor device is used as a semiconductor laser, an active layer is included in the optical waveguide layer, and a forward bias is applied between the p-type ohmic electrode and the n-type ohmic electrode. It can be used as a semiconductor laser. On the other hand, when the optical semiconductor device is used as an optical modulator, a light absorption layer is included in the optical waveguide layer, and a reverse bias is applied between the p-type ohmic electrode and the n-type ohmic electrode to perform optical modulation. It can be used as a container.

Embodiments of the present invention will be specifically described below with reference to the drawings. (Embodiment 1) FIG. 1 is a sectional view of an optical semiconductor device according to a first embodiment of the present invention, which is perpendicular to the waveguide direction. In the figure, 1 indicates an n-type InP substrate having a (100) crystal plane as a main surface.
A mesa stripe 11 is formed on the surface of the n-type InP substrate 1 by forming the optical waveguide layer 2 and then performing mesa processing. Fe on the side of the mesa stripe 11
A doped semi-insulating InP buried layer 3 is formed,
This Fe-doped semi-insulating InP buried layer 3 has a structure in which the mesa stripe 11 is sandwiched. On the active layer 2 and the Fe-doped semi-insulating InP buried layer 3, a p-type InP clad layer 4 having a substantially trapezoidal cross section with a (111) crystal plane as a side surface is formed. A p-type InGaAs contact layer 5 is formed on the p-type InP clad layer 4. On the p-type InGaAs contact layer 5 and above the active layer 2, p made of Au / Zn / Au is formed.
A type ohmic electrode 7 is formed. Further, a SiO ₂ film 6 is formed in a region other than the p-type ohmic electrode 7. Further, the wiring 8 made of Ti / Pt / Au is formed on the region including the p-type ohmic electrode 7, and the bonding pad 9 made of Ti / Pt / Au is in contact with the wiring 8 to form the SiO ₂ film. It is formed on 6. On the back surface of the n-type InP substrate 1, AuGe /
An n-type ohmic electrode 10 made of Ni / Au is formed.

FIG. 2 shows a manufacturing process of the optical semiconductor device shown in FIG.
This will be described with reference to (A) to FIG. First, FIG.
As shown in (A), n having a (100) crystal plane as a main surface
After forming the optical waveguide layer 2 having an InGaAsP / InGaAsP multiple quantum well structure on the InP substrate 1,
A SiO ₂ film 14 of μm is formed in a stripe shape, and this S
Wet etching was performed using an HBr-HCl-based etchant with the iO ₂ film 14 as a mask, and the width was 1.5 μm.
A mesa stripe 11 having a height of m and a height of 2 μm is formed. Then, as shown in FIG. 2B, both sides of the mesa stripe 11 are Fe-doped semi-insulating layer I by metalorganic vapor phase epitaxy.
The nP layer 3 is formed and embedded. Next, as shown in FIG. 2C, after removing the SiO ₂ film 14, a pair of stripe-shaped SiO ₂ films 1 sandwiching the mesa stripe 11 are sandwiched.
5 is formed. Here, the width of the SiO ₂ film 15 is 5 μm,
The spacing is 6 μm. Then, as shown in FIG. 2 (D), as a selective growth blocking mask an SiO ₂ film 15, p-type InP cladding layer 4 by metal organic chemical vapor deposition and p
Type InGaAs contact layer 5 is sequentially grown selectively.
Further, an optical semiconductor device having a narrow mesa structure shown in FIG. 1 is formed through an electrode forming step.

In the optical semiconductor device having the structure shown in FIG. 1, both side surfaces of the optical waveguide layer 2 are covered with a Fe-doped semi-insulating InP layer 3 having a current blocking effect. Therefore, in the case where the optical semiconductor device is used as an optical modulator, when a reverse bias voltage is applied between the p-type ohmic electrode 7 and the n-type ohmic electrode 10, the optical absorption layer included in the optical waveguide layer 2 is affected. It is possible to apply an electric field uniformly in the stacking direction, and a high extinction ratio can be obtained. Even when the optical semiconductor device is used as a semiconductor laser, it is possible to sufficiently reduce the leak current when a forward bias voltage is applied between the p-type ohmic electrode 7 and the n-type ohmic electrode 10. .

The p-type I formed by the selective growth method
The nP clad layer 4 and the p-type InGaAs contact layer 5 are formed in a stripe shape by the separation groove 13. Here, since the position and size of the separation groove 13 are determined by the SiO ₂ mask 15 formed in advance, the p-type InP clad layer 4 and the p-type InGa are formed.
The As contact layer 5 can be grown at a desired position, and the width of the mesa stripe 12 can be controlled to be narrow. In addition, p-type InP formed by the selective growth method
The side surfaces of the clad layer 4 and the p-type InGaAs contact layer 5 are composed of (111) crystal planes, and high-quality surfaces with few interface states can be obtained. As a result, the leak current on the side surface of the mesa stripe 12 can be reduced.
Furthermore, the p-type InP clad layer 4 and the p-type InGaA
Since the side surface of the s contact layer 5 is a relatively gently inclined surface defined by the (111) crystal plane, the wiring 8 is not cut in the isolation trench 13 and the p formed on the mesa stripe 12 is not cut. Type ohmic electrode 7 and separation groove 1
Stepped wirings connecting to the bonding pads 9 formed on the outer side of the wiring 3 can be easily formed.

In the electrode forming step, the p-type ohmic electrode 7, the wiring 8 and the bonding pad 9 are patterned by bringing a glass mask into contact with the surface of the substrate. Here, since the regions other than the stripe-shaped isolation trenches 13 are flat surfaces having substantially the same height, excessive stress is not applied to the mesa stripe 12 located on the upper surface of the active layer 2 in the patterning process. The electrodes can be formed without damaging the device. Furthermore, since the bonding pad 9 is located at substantially the same height as the mesa stripe 12, Au is bonded to the bonding pad 9.
When bonding the wires, it is possible to prevent accidental contact with the mesa stripes 12 and damage to the device.

In this embodiment, the mesa stripe 1
1 has a structure in which the Fe-doped semi-insulating InP layer 3 is sandwiched, but the mesa stripe 11 is sandwiched by a semiconductor layer having a two-layer structure in which an n-type InP layer is laminated on the upper surface of the Fe-doped semi-insulating InP layer 3. It may be a structure. (Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view perpendicular to the waveguide direction of an optical semiconductor device according to the second embodiment of the present invention. In FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals as those in FIG. 1 and their description is omitted.

In the optical semiconductor device shown in FIG. 3, an undoped InP layer 20 (cap layer) is formed on the optical waveguide layer 2. The undoped InP layer 20 is a p-type I
When growing the nP cladding layer 4, Z which is a p-type impurity
n is prevented from diffusing into the active layer 2. Further, the n-type InP buried layers 21 ₁ and 21 ₂ having a two-layer structure are buried, and the optical waveguide layer 2 and the undoped InP layer 20 are included.
Are the two-layered n-type InP buried layers 21 ₁ and 21
It is sandwiched by _two . In this case, n-type InP
The buried layer may not have a two-layer structure, but may have a difference in impurity concentration between the upper side and the lower side in the thickness direction, for example, a concentration gradient in which the impurity concentration sequentially changes in the thickness direction.

In this element, a pn junction composed of the p-type InP clad layer 4 and the n-type InP layer 21 ₁
An attempt is made to obtain a current blocking effect on both sides of the optical waveguide layer 2. Therefore, it is necessary to form the width of the mesa stripe 12 narrow not only for the purpose of reducing the element parasitic capacitance but also for reducing the leak current. According to the invention, p-type I
The nP clad layer 4 and the p-type InGaAs contact layer 5 can be formed by a selective growth method, and the position and size thereof can be determined by a selective growth blocking mask formed in advance. Therefore, the width of the mesa stripe 12 can be controlled to be narrow. Further, the impurity concentration of the n-type InP buried layer 21 ₁ is 1 × 10 ¹⁷ / cm ^3, and the impurity concentration of the n-type InP buried layer 21 ₂ and the n-type InP substrate 1 (1 × 10 ¹⁸ / cm ³ ). Is set lower than. As a result, the p-type InP clad layer 4 and the n-type InP layer 21 ₁
The width of the depletion layer in the pn junction composed of and can be increased, and the parasitic capacitance per unit area can be reduced.

Furthermore, since the impurity concentration of the n-type InP burying layer 21 ₁ is set low, Zn which is a p-type impurity when growing the p-type InP clad layer 4 is contained in the n-type InP burying layer 21 ₁ . Easy to diffuse into Therefore,
The actual pn junction is formed at a position shifted to the substrate side with respect to the regrowth interface. As a result, the current blocking effect can be obtained at a position different from the regrowth interface having many interface states, so that the leak current can be reduced and the threshold value and the output can be increased.

In this embodiment, the both sides of the mesa stripe 11 are covered with n-type InP layers 21 ₁ and 21 _{2 having} different impurity concentrations, but the impurity concentration of the n-type InP buried layer is in the stacking direction. It may or may not be changed gradually (upward in the thickness direction). (Embodiment 3) Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a sectional view perpendicular to the waveguide direction of an optical semiconductor device according to the third embodiment of the present invention. 4, parts that are the same as those in FIG. 1 are given the same reference numerals as in FIG. 1 and their explanations are omitted.

In the optical semiconductor device shown in FIG. 4, a p-type InP burying layer 22 and an n-type InP burying layer 21 are formed on a region other than the mesa stripe 11 of the n-type InP substrate 1.
A buried layer having a two-layer structure formed by sequentially forming is buried, and the optical waveguide layer 2 is sandwiched by a p-type InP buried layer 22 and an n-type InP buried layer 21. Further, a polyimide film 16 is formed on the SiO ₂ film 6 and is flattened. The wiring 8 and the bonding pad 9 are formed on this.

In this device, the p-type InP cladding layer 4 and the p-type InGaAs contact layer 5 are selectively grown only in the region of the mesa stripe 12 by using the selective growth prevention mask having only one stripe-shaped opening. I am letting you. The side surface of the mesa stripe 12 is filled with a polyimide film 16 to reduce the electrode pad capacitance per unit area. Here, since the side surfaces of the p-type InP clad layer 4 and the p-type InGaAs contact layer 5 are gently inclined surfaces defined by the (111) crystal plane, the step of planarizing the element surface with the polyimide film 16 is performed. Can also be done easily.

Further, according to the present invention, the p-type InP clad layer 4 and the p-type InGaAs contact layer 5 can be formed at arbitrary positions by the selective growth method. Therefore, the width of the mesa stripe 12 can be controlled to be narrow, and the p-type cladding layer 4 and the n-type InP can be formed.
It is possible to suppress the depletion layer capacitance in the pn junction 23 including the buried layer 21 to be small. Furthermore, n-type In
The impurity concentration of the P buried layer 21 is set as low as 1 × 10 ¹⁷ / cm ³ and the width of the depletion layer in the pn junction 23 can be increased, so that the parasitic capacitance per unit area can be reduced at the same time. ing.

In the case where the optical semiconductor device is used as a semiconductor laser, when a forward bias voltage is applied between the p-type ohmic electrode 7 and the n-type ohmic electrode 10, the n-type InP buried layer 21 and the p-type InP buried layer are formed. A current blocking effect is obtained in the pn junction 24 formed of the layer 22. Since the pn junction 24 is not the regrowth interface, it is possible to sufficiently reduce the leak current, and it is possible to obtain a low threshold operation and a high output operation. (Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a perspective view of an optical semiconductor device according to the fourth embodiment of the present invention, which has a structure in which an optical modulator 31 and a DFB laser 33 are monolithically integrated. In the figure, 34 is an optical waveguide layer including an active layer, and 35 is a diffraction grating. The front end face of the device is anti-reflection coated with a SiN _x film 36, and the rear end face is Si / SiO ₂
The multilayer film 37 is highly reflectively coated.

In this device, the p-type InP clad layer 4 and the p-type InGaAs contact layer 5 were formed by the selective growth method using the SiO ₂ mask 15 shown in FIG. 6 as a selective growth blocking mask. As a result, the optical modulator region 31
In the electrode isolation region 32, the p-type InP clad layer 4 is formed.
The p-type InGaAs contact layer 5 has a stripe-shaped groove 13 having a substantially trapezoidal cross section with the (111) plane as a side surface.
In the laser region 33, the p-type InP clad layer 4 and the p-type InGaAs contact layer 5 are flatly grown. As a result, the parasitic capacitance in the optical modulator region 31 is reduced, and a high speed modulation operation can be obtained. Further, the p-type InGaAs contact layer 5 is removed by etching in the electrode isolation region 32, and the electrode isolation resistance between the optical modulator region 31 and the laser region 33 has a high value of 20 kΩ or more.

In this embodiment, the p-type InP clad layer 4 and the p-type InGaAs contact layer 5 are flatly grown in the laser region 33, but the clad layer and the contact layer are also selected in the laser region 33. A structure formed in a stripe shape by a growth method may be used. (Embodiment 5) In order to realize an optical semiconductor device capable of high-speed modulation, it is necessary to reduce the parasitic capacitance per unit area and process the vicinity of the optical waveguide layer stripe into a narrow mesa shape.

In the structure of FIG. 1, the Fe-doped semi-insulating InP buried layer 3 traps electrons but not holes. Therefore, the p-type InP clad layer 4
When holes are injected into the semi-insulating InP buried layer 3 from the above, the injected holes and the trapped electrons are recombined, whereby a leak current flows. In particular, Fe, which is a dopant for the semi-insulating InP buried layer 3, and p-type In
Since Zn, which is a dopant of the P clad layer 4, easily interdiffuses, the semi-insulating InP from the p-type InP clad layer 4
Holes are likely to be injected into the buried layer 3 and the leak current may increase. Furthermore, if Zn, which is a dopant of the InP clad layer 4, diffuses into the semi-insulating InP buried layer 3, the semi-insulating InP buried layer 3 is less likely to be depleted, which may increase the parasitic capacitance per unit area. is there.

In order to reduce the leak current, it is effective to provide an n-type semiconductor layer, for example, an n-type InP current blocking layer, between the semi-insulating InP buried layer 3 and the InP clad layer 4. Since this n-type InP current blocking layer serves as a barrier against holes, holes are prevented from being injected from the p-type InP cladding layer 4 into the semi-insulating InP buried layer 3. At the same time, Fe, which is a dopant for the semi-insulating InP buried layer 3, and Zn, which is a dopant for the p-type InP cladding layer 4, are prevented from interdiffusing. As a result, the leakage current can be sufficiently reduced, and at the same time, the parasitic capacitance per unit area is not increased. However, the n-type InP current blocking layer is usually not formed in a narrow mesa shape, and therefore the Fe-doped semi-insulating I
The electric field applied to the nP buried layer 3 is distributed laterally wider than the width of the mesa stripe through the n-type InP current blocking layer. In this case, although the p-type InP clad layer 4 has a narrow mesa shape, there is a problem that the element parasitic capacitance increases.

Therefore, in the fifth to tenth embodiments, the parasitic capacitance per unit area is reduced and, at the same time, a highly accurate narrow mesa structure in which the electric field is not spread and distributed is realized, thereby reducing the element parasitic capacitance. Then, an optical semiconductor device capable of high-speed modulation operation by an electric signal is provided. That is, the essence of this example is that the side surface of the optical waveguide layer is embedded with a semi-insulating semiconductor layer, the clad layer is formed into a narrow mesa shape with the side surface being a (111) crystal plane, and the semi-insulating semiconductor layer and the clad layer are formed. By providing a stripe-shaped current blocking layer between the two, a narrow mesa structure optical semiconductor device having an extremely small element parasitic capacitance is provided.

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view perpendicular to the waveguide direction of an optical semiconductor device according to the fifth embodiment of the present invention. 7, parts that are the same as those in FIG. 1 are given the same reference numerals as in FIG. 1 and their explanations are omitted.

In the optical semiconductor device shown in FIG. 7, Fe
An n-type InP current blocking layer 40 is interposed between the doped semi-insulating InP buried layer 3 and the p-type InP clad layer 4. The n-type InP current blocking layer 40 is divided by the SiO ₂ film 6 and formed in a stripe shape.

FIG. 8 shows a manufacturing process of the optical semiconductor device shown in FIG.
This will be described with reference to (A) to FIG. First, FIG.
As shown in (A), n having a (100) crystal plane as a main surface
After forming the optical waveguide layer 2 having an InGaAsP / InGaAsP multiple quantum well structure on the InP substrate 1,
A SiO ₂ film 14 of μm is formed in a stripe shape, and this S
Wet etching was performed using a Br-based etchant with the iO ₂ film 14 as a mask, and the width was 1 μm and the height was 2 μm.
To form the mesa stripe 11. Then, FIG. 8 (B)
As shown in FIG. 3, a Fe-doped semi-insulating InP layer 3 having a thickness of 1.8 μm and an n-type InP current blocking layer 40 having a thickness of 0.3 μm are formed on both sides of the mesa stripe 11 by a metal organic chemical vapor deposition method. To embed. Next, as shown in FIG. 8C, after removing the SiO ₂ film 14, the n-type InP current blocking layer 40 on the Fe-doped semi-insulating InP layer 3 is partially etched and removed. The n-type InP current blocking layer 40 is processed into a pair of stripes positioned with the optical waveguide layer 2 interposed therebetween.

Further, as shown in FIG. 8D, n-type I
A pair of stripe-shaped SiO ₂ films 15 are formed in the region where the nP current blocking layer 40 is removed. Here, the SiO ₂ film 15 has a width of 5 μm and an interval of 6 μm. Then, FIG.
As shown in (E), the p-type InP cladding layer 4 and the p-type InGaAs contact layer 5 are sequentially grown selectively by metalorganic vapor phase epitaxy using the SiO ₂ film 15 as a selective growth prevention mask. Further, an optical semiconductor device having a narrow mesa structure shown in FIG. 7 is formed through an electrode forming step.

According to the method of this embodiment, the step of processing the n-type InP current blocking layer 40 into a stripe shape and the step of forming the stripe-shaped SiO ₂ mask 15 are patterned on a substantially flat substrate surface. Therefore, highly accurate patterning is possible. further,
The positions and sizes of the p-type InP clad layer 4 and the p-type InGaAs contact layer 5 formed by the selective growth method are the same as those of the SiO ₂ growth blocking mask 15 formed in advance.
Can be arbitrarily determined by. Therefore, the width of the mesa stripe 12 can be controlled to be narrow, and at the same time, the stripe-shaped n-type InP current blocking layer 40 can be accurately formed under the mesa stripe 12.

Also, the mesa stripe 1 including the optical waveguide layer 2
Since both side surfaces of No. 1 are filled with the Fe-doped semi-insulating InP layer 3, it is possible to sufficiently reduce the parasitic capacitance per unit area. Here, the n-type InP current blocking layer 40 reduces the leak current in order to prevent Fe, which is the dopant of the semi-insulating InP buried layer 3, and Zn, which is the dopant of the p-type InP cladding layer 4, from interdiffusing. At the same time, the parasitic capacitance per unit area does not increase. Further, the n-type InP current blocking layer 40
Is formed below the mesa stripe 12 in a stripe shape, and therefore, the electric field applied to the semi-insulating InP buried layer 3 does not spread laterally beyond the width of the mesa stripe 12. As a result, it is possible to make the element parasitic capacitance extremely small. (Embodiment 6) Next, a sixth embodiment of the present invention is shown in FIG.
~ It demonstrates using FIG. 9 (E). 9 (A) to 9
(E) is sectional drawing perpendicular to the waveguide direction in each manufacturing process of the optical-semiconductor device concerning the 6th Example of this invention.
9, parts that are the same as those in FIG. 7 are given the same reference numerals as in FIG. 7 and their explanations are omitted.

First, as shown in FIG.
0) A mesa stripe 11 is formed by laminating an optical waveguide layer 2 on an n-type InP substrate 1 having a crystal plane as a main surface. Then
As shown in FIG. 9B, both sides of the mesa stripe 11 are made of Fe-doped semi-insulating InP by metalorganic vapor phase epitaxy.
Fill with layer 3 and n-type InP current blocking layer 40. Next, as shown in FIG. 9C, after removing the SiO ₂ mask 14, a pair of stripe-shaped SiO ₂ films 15 are formed on the n-type InP current blocking layer 40 so as to sandwich the mesa stripe 11.

Then, as shown in FIG.
_{2 The} film 15 is used as a mask for selective growth, and the p-type InP clad layer 4 and the p-type InGa are formed by metalorganic vapor phase epitaxy.
The As contact layer 5 is sequentially grown selectively. Next, as shown in FIG. 9E, the n-type InP current blocking layer 40 under the SiO ₂ growth blocking mask 15 is removed by etching. Further, a narrow mesa structure optical semiconductor device having a structure similar to that of FIG. 7 is formed through an electrode forming step.

In this embodiment, the step of processing the n-type InP current blocking layer 40 into a stripe shape can be performed in a self-aligned manner as shown in FIG. That is, as shown in FIG. 10A, after selectively growing the p-type InP cladding layer 4 and the p-type InGaAs contact layer 5, a resist layer 17 having an opening is formed on the SiO ₂ growth blocking mask 15. . Next, as shown in FIG. 10B, the SiO ₂ growth blocking mask 15 is removed by etching using side etching. This allows
Since the n-type InP current blocking layer 40 under the SiO ₂ growth blocking mask 15 is exposed, the exposed n-type InP current blocking layer 40 is removed by etching as shown in FIG. 10C. It is possible to accurately form the stripe-shaped n-type InP current blocking layer 40 under the mesa stripe 12. (Embodiment 7) Next, a seventh embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (A) to FIG. 11 (F). FIG. 11 (A)
11F is a cross-sectional view perpendicular to the waveguide direction in each manufacturing process of the optical semiconductor device according to the seventh embodiment of the present invention. 11, parts that are the same as those in FIG. 7 are given the same reference numerals as in FIG. 7 and their explanations are omitted.

First, as shown in FIG.
0) A mesa stripe 11 is formed by laminating an optical waveguide layer 2 on an n-type InP substrate 1 having a crystal plane as a main surface. Then
As shown in FIG. 11B, the both sides of the mesa stripe 11 are made of Fe-doped semi-insulating In by metalorganic vapor phase epitaxy.
Embed with P layer 3. Next, as shown in FIG. 11C, after the SiO ₂ mask 14 is removed, the SiO ₂ film 18 is formed on the mesa stripe 11 by the Fe-doped semi-insulating In.
A pair of stripe-shaped SiO ₂ films 19 are formed on the P layer 3 with the mesa stripe 11 interposed therebetween.

Then, as shown in FIG.
Using the O ₂ film 18 and the SiO ₂ film 19 as a selective growth blocking mask, the n-type InP current blocking layer 40 is selectively grown by the metal organic chemical vapor deposition method. After that, as shown in FIG. 11E, the SiO ₂ film 18 on the mesa stripe 11 is removed by etching. Next, as shown in FIG. 11F, the p-type InP clad layer 4 and the p-type InGaAs contact layer 5 are selectively grown by metal organic chemical vapor deposition using the SiO ₂ film 19 as a selective growth prevention mask. Further, a narrow mesa structure optical semiconductor device having a structure similar to that of FIG. 7 is formed through an electrode forming step.

In this embodiment, the n-type InP current blocking layer 40 is used.
The SiO ₂ film 19 is used as a common growth-preventing mask when selectively growing the p-type InP clad layer 4 and the p-type InGaAs contact layer 5, so that the same width as the mesa stripe 12 is formed. It is possible to form the stripe-shaped n-type InP current blocking layer 40 that has. (Embodiment 8) Next, an eighth embodiment of the present invention will be described with reference to FIG. FIG. 12 is a sectional view perpendicular to the waveguide direction of an optical semiconductor device according to the eighth embodiment of the present invention. FIG.
2, the same parts as those in FIG. 7 are designated by the same reference numerals as those in FIG. 7 and their explanations are omitted.

In the present embodiment, both sides of the mesa stripe 11 including the optical waveguide layer 2 are filled with the Fe-doped semi-insulating InP layer 3 and the n-type InGaAsP current blocking layer 41, and the p-type InP clad layer 4 and p-type InGaAs are provided. After selectively growing the contact layer 5, n-type InGaAs
The P current blocking layer 41 is processed into a stripe shape by etching. In this case, as shown in FIG. 12, side etching can be used to perform stripe processing so that the width of the n-type InGaAs current blocking layer 41 is narrower than the width of the mesa stripe 13. Further, the polyimide film 16 is embedded in the region where the n-type InGaAsP current blocking layer 41 is removed by etching. As a result, the distribution of the electric field applied to the semi-insulating InP buried layer 3 extends only to the width of the n-type InGaAsP current blocking layer 41, so that an extremely small element parasitic capacitance can be obtained. (Ninth Embodiment) Next, a ninth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a sectional view of the optical semiconductor device according to the ninth embodiment of the present invention, which is perpendicular to the waveguide direction. FIG.
3, the same parts as those in FIG. 7 are designated by the same reference numerals as those in FIG. 7 and their explanations are omitted.

In this embodiment, the n-type InP current blocking layer 40, the p-type InP clad layer 4, and the p-type InGaAs contact layer 5 are provided only in the region of the mesa stripe 12, and the side surface of the mesa stripe 12 is made of polyimide. Membrane 16
Is embedded by. As a result, under the bonding pad (electrode pad) 9, the polyimide film 16 and SiO
It has a structure in which the _two films 6 and the semi-insulating InP buried layer 3 are laminated, and has a structure in which the electrode pad capacitance per unit area is reduced. Also, mesa stripe 1
Since the side surface 2 is a relatively gentle inclined surface defined by the (111) crystal plane, the step of planarizing the element surface with the polyimide film 16 can be easily performed. (Tenth Embodiment) Next, a tenth embodiment of the present invention will be described with reference to FIG.
Will be explained. FIG. 14 is a sectional view perpendicular to the waveguide direction of an optical semiconductor device according to the tenth embodiment of the present invention. 14, parts that are the same as those in FIG. 7 are given the same reference numerals as in FIG. 7, and description thereof will be omitted.

In this embodiment, the n-type InP current blocking layer 40 is not provided below the bonding pad 9. Further, after selectively growing the p-type InP clad layer 4 and the p-type InGaAs contact layer 5, the p-type InGaAs contact layer 5 under the bonding pad 9 is removed by etching, and the p-type InP is further implanted by proton implantation.
The clad layer 4 is semi-insulated. As a result, under the bonding pad 9, the SiO ₂ film 6, the proton-implanted semi-insulating InP layer 42, and the semi-insulating InP buried layer 3 are laminated, and the electrode pad capacitance per unit area is reduced. It has a reduced structure. (Embodiment 11) In a narrow mesa optical semiconductor device including a mesa stripe having a semi-insulating InP layer on an optical waveguide layer, it is necessary to form a narrow mesa stripe width in order to reduce element parasitic capacitance. is there. However, if this width is made narrow, the area of the p-type ohmic electrode formed on the p-type InGaAs contact layer becomes small, and the element series resistance becomes large. Therefore, in the optical semiconductor device having the mesa stripe structure, it is difficult to simultaneously reduce the parasitic capacitance and the series resistance.

Further, in the step of forming the mesa stripe, the mask is patterned according to the position of the optical waveguide layer. Therefore, the narrower the width of the mesa stripe, the higher the accuracy of mask alignment required. Is difficult to control narrowly, and it is difficult to reduce the manufacturing cost.

Further, since the surface after processing the mesa stripe lacks flatness, it becomes difficult to form an electrode on it. In particular, the wiring formed on the side surface of the mesa stripe is easily cut, and it is also difficult to form a stepped wiring connecting the p-type ohmic electrode and the bonding pad.

Therefore, in the eleventh and twelfth embodiments, an optical semiconductor device capable of simultaneously reducing the parasitic capacitance and series resistance and capable of high-speed modulation operation by an electric signal, and such an optical semiconductor device are provided. Provided is a method for manufacturing an optical semiconductor device which can easily form electrodes at low cost.

Next, an eleventh embodiment of the present invention will be described with reference to FIG. FIG. 15 is a sectional view perpendicular to the waveguide direction of an optical semiconductor device according to the eleventh embodiment of the present invention.
15, parts that are the same as those in FIG. 1 are given the same reference numerals as in FIG. 1 and their explanations are omitted.

In the optical semiconductor device shown in FIG. 15, the InP cap layer 50 is formed on the optical waveguide layer 2 in the mesa stripe. Therefore, the Fe-doped semi-insulating InP layer 3 is formed on both sides of the optical waveguide layer 2 and the InP cap layer 50.
Is embedded.

Further, the p-type InP clad layer 4 is provided with an eave portion 4a. The SiO ₂ film 6 extends below the eaves portion 4a of the p-type InP clad layer 4, and the InGaAsP spacer layer 52 is provided below the p-type InP clad layer 4 in the region other than the mesa stripe 12. ing.

Next, a manufacturing process of the optical semiconductor device shown in FIG. 15 will be described with reference to FIGS. 16 (A) to 16 (E). First, as shown in FIG. 16A, an optical waveguide layer 2 and InP are formed on an n-type InP substrate 1 having a (100) crystal plane as a main surface.
After stacking the cap layer 50, the SiO ₂ film 5 having a width of 4 μm
1 is formed in a stripe shape. Using the SiO ₂ film 51 as a mask, the InP cap layer 50, the optical waveguide layer 2, and the n-type InP substrate 1 are etched to have a width of 1 μm and a height of 2.
A mesa stripe 11 of μm is formed.

Next, as shown in FIG. 16B, the both sides of the mesa stripe 11 are F-shaped by metal organic chemical vapor deposition.
Embedding with e-doped semi-insulating InP layer 3, followed by Si
InGaAsP spacer layers 52 are selectively grown on both sides of the O ₂ film 51. Then, as shown in FIG.
After removing the iO ₂ mask 51, a pair of stripe-shaped SiO ₂ films 53 having openings with a width of 12 μm are formed on the InGaAsP spacer layer 52.

Then, as shown in FIG.
Using the O ₂ film 53 as a selective growth prevention mask, the p-type InP clad layer 4 and the p-type InG are formed by the metal organic chemical vapor deposition method.
The aAs contact layer 5 is selectively grown. Then, FIG.
As shown in FIG. 6 (E), the SiO ₂ film 53 is removed and In
The GaAsP spacer layer 52 is side-etched. Further, an optical semiconductor device having the structure shown in FIG. 15 is formed through an electrode forming step.

In this embodiment, Si is used as a common mask when the mesa stripe 11 is formed by etching and when the InGaAsP spacer layer 52 is selectively grown.
The O ₂ film 51 is used. Therefore, the position of the bottom surface of the p-type InP clad layer 4 can be determined in a self-aligned manner. Further, the width of the bottom surface of the p-type InP clad layer 4 is S
The width is determined by the width of the iO ₂ film 51 and is extremely narrow, for example, 4 μm. As a result, an extremely small element parasitic capacitance can be obtained.

Further, the p-type InP clad layer 4 has the eaves portion 4a.
Since the p-type InP clad layer 4 has a narrow bottom surface, the top surface of the p-type InP clad layer 4 has a sufficient width. It can be formed widely. Therefore,
The width of the p-type ohmic electrode 7 formed on the p-type InGaAs contact layer 5 is as wide as 8 μm. As a result, the element parasitic capacitance can be reduced, and at the same time, the element series resistance can be made sufficiently small.

Further, the p-type InP clad layer 4 and p
The type InGaAs contact layer 5 is previously formed in a stripe shape by the selective growth method. In this case, the side surface of the p-type InP clad layer 4 formed by the selective growth method is a relatively gentle inclined surface defined by the (111) crystal plane. Therefore, if the eave portion 4a of the p-type InP clad layer 4 is filled with a dielectric film, the wiring is not cut at the side surface of the narrow mesa 12, and the p-type ohmic electrode 7 and the bonding pad 9 are not separated. It is also possible to easily form a stepped wiring that connects the two.

In this embodiment, the SiO ₂ film 6 is buried under the eaves 4a of the p-type InP clad layer 4 by using spin-on glass. The SiO ₂ film 6 has a problem that cracks occur if the film thickness is made too thick.
The thickness of the void below the eaves portion 4a of the P clad layer 4 is, for example, 0.
The thickness is 5 μm, and the SiO ₂ film 6 is not cracked. Further, the thickness of this void is determined by the thickness of the InGaAsP spacer layer 52, and its controllability is also excellent. Furthermore, in this case, since it is not necessary to thicken the dielectric film, it is not necessary to use a polymer material such as a polyimide film, and the reliability of the device is high. (Embodiment 12) Next, a twelfth embodiment of the present invention will be described with reference to FIG. FIG. 17 is a sectional view perpendicular to the waveguide direction of an optical semiconductor device according to the twelfth embodiment of the present invention. 17, parts that are the same as those in FIG. 15 are given the same reference numerals as in FIG. 15 and their explanations are omitted.

In this embodiment, by using the selective growth prevention mask having only one stripe-shaped opening, the p-type InP clad layer 4 is formed only in the region of the narrow mesa 12.
The p-type InGaAs contact layer 5 is selectively grown. After the side surface of the narrow mesa 12 is covered with the SiO ₂ film 6,
It is embedded by the polyimide film 54, and has a structure in which the capacitance per unit area of the bonding pad 9 is reduced. In this case, since the side surfaces of the p-type InP clad layer 4 and the p-type InGaAs contact layer 5 are relatively gently inclined surfaces defined by the (111) plane, the step of flattening the element surface with the polyimide film 54 is performed. Can be done easily. Also in this structure, the stripe-shaped p-type InP clad layer 4 having a substantially T-shaped cross section can reduce the parasitic capacitance of the element and at the same time make the element series resistance sufficiently small.

According to this embodiment, it is possible to easily form an extremely accurate narrow mesa structure, and an optical semiconductor device capable of high-speed modulation by an electric signal can be realized at low cost.

The present invention is not limited to the above embodiment. In this embodiment, InGaAsP
Although a semiconductor device of the system is explained, AlGaIn
The present invention can be applied to other material systems such as P system, InGaAsSb system, and ZnCdSSe system. Also,
In this embodiment, the structure in which the contact layer is laminated on the clad layer is described, but if a sufficiently low contact resistance can be obtained between the clad layer and the electrode metal, the contact layer is laminated. You don't have to. Further, in the present embodiment, the single semiconductor modulator, the single semiconductor laser, and the integrated light source of the optical modulator and the semiconductor laser have been described, but in addition, in the device structure in which the optical waveguide, the optical amplifier, and the like are integrated. However, the present invention is effective.

Further, the conductivity type of the semiconductor burying layer is not limited to the semi-insulating semiconductor layer, but other p-type semiconductor layers,
You may use an n-type semiconductor layer or the structure which laminated these. Further, a bulk material or a multiple quantum well structure may be used for the optical waveguide layer (active layer). Further, the semiconductor burying layer is not limited to the InP layer.
An InGaAsP layer or a semiconductor layer in which an InP layer and an InGaAsP layer are stacked may be used. Also, various semiconductor layers can be used for the conductivity type and the impurity concentration of the semiconductor burying layer. Furthermore, the semiconductor substrate is (10
0) An off-substrate from the crystal plane may be used, and the conductivity type is n.
It is not limited to the mold substrate. In addition, various modifications can be made without departing from the scope of the present invention.

[0065]

As described in detail above, according to the present invention,
Since the striped clad layer having a substantially trapezoidal cross section with the (111) crystal face as the side surface can be formed at any position, the mesa width can be controlled easily, and the electrode formation process can be easily performed. A mesa structure can be obtained. As a result, an optical semiconductor device capable of high-speed modulation by an electric signal can be realized without involving a difficult manufacturing process.

Further, since both side surfaces of the optical waveguide layer are filled with the current blocking layer, when the optical semiconductor device is used as an optical modulator, an electric field can be uniformly applied to the optical waveguide layer. A high extinction ratio can be obtained. Also, when the optical semiconductor device is used as a semiconductor laser, it is possible to sufficiently reduce the leak current, and it is possible to obtain a low threshold operation and a high output operation.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a first embodiment of an optical semiconductor device of the present invention, which is perpendicular to the waveguide direction.

2A to 2D are cross-sectional views perpendicular to the waveguide direction in the manufacturing process of the optical semiconductor device shown in FIG.

FIG. 3 is a sectional view of a second embodiment of the optical semiconductor device of the present invention, which is perpendicular to the waveguide direction.

FIG. 4 is a sectional view of a third embodiment of the optical semiconductor device of the present invention, which is perpendicular to the waveguide direction.

FIG. 5 is a perspective view showing an optical semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a perspective view showing an example of a selective growth blocking mask used in a method of manufacturing an optical semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view of a fifth embodiment of the optical semiconductor device of the present invention, which is perpendicular to the waveguide direction.

8A to 8E are cross-sectional views perpendicular to the waveguide direction in the manufacturing process of the optical semiconductor device shown in FIG.

9A to 9E are cross-sectional views perpendicular to the waveguide direction in the manufacturing process of the optical semiconductor device according to the sixth embodiment of the present invention.

10A to 10C are cross-sectional views perpendicular to the waveguide direction in the manufacturing process of the optical semiconductor device according to the sixth embodiment of the present invention.

11A to 11F are cross-sectional views perpendicular to the waveguide direction in the manufacturing process of the optical semiconductor device according to the seventh embodiment of the present invention.

FIG. 12 is a sectional view of an optical semiconductor device according to an eighth embodiment of the present invention, which is perpendicular to the waveguide direction.

FIG. 13 is a sectional view of a ninth embodiment of an optical semiconductor device of the present invention, which is perpendicular to the waveguide direction.

FIG. 14 is a sectional view of a tenth embodiment of the optical semiconductor device of the present invention, which is perpendicular to the waveguide direction.

FIG. 15 is a sectional view of an optical semiconductor device according to an eleventh embodiment of the present invention, which is perpendicular to the waveguide direction.

16A to 16E are cross-sectional views perpendicular to the waveguide direction in the manufacturing process of the optical semiconductor device shown in FIG.

FIG. 17 is a sectional view of a twelfth embodiment of an optical semiconductor device of the present invention, which is perpendicular to the waveguide direction.

FIG. 18 is a cross-sectional view of a conventional semiconductor device having a semiconductor-embedded structure, which is perpendicular to the waveguide direction.

FIG. 19 is a cross-sectional view of a conventional semiconductor device having a semiconductor-embedded structure, which is perpendicular to the waveguide direction.

[Explanation of symbols]

1 ... n-type InP substrate, 2,34 ... optical waveguide layer, 3 ... Fe-doped semi-insulating InP buried layer, 4 ... p-type InP clad layer, 4a ... eave part, 5 ... p-type InGaAs contact layer, 6,53 ... SiO ₂ film, 7 ... p-type ohmic electrode,
8 ... Wiring, 9 ... Bonding pad, 10 ... N-type ohmic electrode, 11, 12 ... Mesa stripe, 13 ... Separation groove, 14, 15, 51 ... SiO ₂ mask, 16, 54 ...
Polyimide film, 20 ... Undoped InP layer, 21, 21
₁ , 21 ₂ ... n-type InP buried layer, 22 ... p-type InP
Buried layer, 23, 24, 25 ... Pn junction, 31 ... Optical modulator region, 32 ... Laser region, 33 ... Electrode separation region, 3
5 ... Diffraction grating, 36 ... Anti-reflection coating film, 37 ... High-reflection coating film, 40 ... N-type InP current blocking layer, 4
1 ... N-type InGaAsP current blocking layer, 42 ... Proton-implanted semi-insulating InP layer, 50 ... InP cap layer, 5
2 ... InGaAsP spacer layer.

Claims (4)

[Claims] 1. A semiconductor substrate having a mesa stripe in which at least an optical waveguide layer is formed and having a (100) crystal plane as a main surface, semiconductor embedding layers formed on both sides of the mesa stripe, and a mesa stripe. An optical semiconductor device comprising: a region and the clad layer formed on the semiconductor burying layer and having a stripe shape having a substantially trapezoidal cross section with a (111) crystal plane as a side surface. 2. A semiconductor substrate having a mesa stripe in which at least an optical waveguide layer is formed and having a (100) crystal plane as a main surface, and a semi-insulating semiconductor embedded on both sides of the mesa stripe. A layer, a stripe-shaped clad layer formed on the mesa stripe region and the semiconductor burying layer and having a substantially trapezoidal cross section with a (111) crystal plane as a side surface, and between the semiconductor burying layer and the clad layer. An optical semiconductor device comprising: a stripe-shaped current blocking layer provided. 3. A semiconductor substrate having a mesa stripe in which at least an optical waveguide layer is formed and having a (100) crystal plane as a main surface, semiconductor embedding layers formed on both sides of the mesa stripe, and a mesa stripe. A striped clad layer formed on the region and the semiconductor burying layer, having a (111) crystal plane as a side surface, having a substantially trapezoidal cross section, and having a flange portion wider than at least a surface in contact with the mesa stripe; An optical semiconductor device comprising: 4. A step of forming a mesa stripe on which at least an optical waveguide layer is formed on a semiconductor substrate having a (100) crystal plane as a main surface, and a step of forming a semiconductor burying layer on both side surfaces of the mesa stripe. Forming a growth blocking mask having a stripe-shaped opening including the mesa stripe region on the semiconductor burying layer; and selectively growing using the growth blocking mask to form the mesa stripe region and A step of forming a clad layer having a substantially trapezoidal cross section with a (111) crystal plane as a side surface on the semiconductor burying layer.