JPH08316113A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH08316113A JPH08316113A JP12215595A JP12215595A JPH08316113A JP H08316113 A JPH08316113 A JP H08316113A JP 12215595 A JP12215595 A JP 12215595A JP 12215595 A JP12215595 A JP 12215595A JP H08316113 A JPH08316113 A JP H08316113A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- wafer
- chip
- semiconductor wafer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
係り、特に高熱を発生するパワーＩＣ等の半導体装置の
製造に用いて有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective for manufacturing a semiconductor device such as a power IC which generates high heat.
【０００２】[0002]
【従来の技術】従来、高熱を発生する半導体装置の製造
方法においては、半導体素子が取り付けられているタブ
等の背面が露出していたり、放熱板に取り付けられてい
る。これら高熱を発生する半導体素子では熱がこもると
温度により素子の特性に変化をきたし、その放熱性の確
保が半導体装置の重要な課題の一つとなっている。2. Description of the Related Art Conventionally, in a method of manufacturing a semiconductor device that generates high heat, a back surface of a tab or the like on which a semiconductor element is mounted is exposed or is mounted on a heat sink. In these semiconductor elements that generate high heat, the characteristics of the elements change depending on the temperature when the heat is accumulated, and securing the heat dissipation is one of the important issues of the semiconductor device.
【０００３】一般的にはパワーＩＣ等ではリードとは別
体の放熱板上に半導体素子をボンディングし、その後リ
ードと素子をワイヤボンディングし、放熱板の片方の面
を露出させモールドを行うものである。Generally, in a power IC or the like, a semiconductor element is bonded on a heat sink which is separate from the leads, and then the lead and the element are wire-bonded, and one surface of the heat sink is exposed to perform molding. is there.
【０００４】また他の高熱を発生する素子における方法
は、パッケージにフィン等を取り付けたものを使用し放
熱効果の向上を図るものもある。Another method for producing a high heat element is to use a package having fins or the like attached to improve the heat radiation effect.
【０００５】このようなものを示したものの一例として
特公昭５８−１１７３８号や、特開昭６０−２０２９５
５号がある。[0005] As an example showing such a thing, Japanese Patent Publication No. 58-11738 and Japanese Patent Laid-Open No. 60-20295.
There is number 5.
【０００６】[0006]
【発明が解決しようとする課題】上記したような手段に
おいては、放熱板やフィンを有するパッケージとするこ
とにより、放熱効果を上げる効果が記載されている。本
願発明者はこのような手段とは別の手段を用いてさらに
放熱効果を上げることができないか考えた。The above-mentioned means describes the effect of improving the heat dissipation effect by using a package having a heat dissipation plate and fins. The inventor of the present application wondered whether it is possible to further improve the heat radiation effect by using a means other than such means.
【０００７】本願発明の目的は上記したような問題を解
決し、さらに放熱効果の優れた半導体装置の製造方法を
確立することにある。An object of the present invention is to solve the above-mentioned problems and to establish a method of manufacturing a semiconductor device having an excellent heat dissipation effect.
【０００８】[0008]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの手段において説明すれば下
記のとおりである。[Means for Solving the Problems] The typical means of the invention disclosed in the present application will be described below.
【０００９】すなわち半導体ウエハを研削し所望の厚さ
にする工程と、前記研削した半導体ウエハの素子形成側
でない面全面に磁性体からなる金属板を貼付ける工程
と、前記半導体ウエハ上に半導体素子を形成する工程
と、前記ウエハを個々となるべきチップに分割する工程
と、前記分割されたチップとリードとを接続する工程
と、前記素子を金属板の一部を露出して封止することに
より放熱効果の優れた半導体装置を得るものである。That is, a step of grinding a semiconductor wafer to a desired thickness, a step of attaching a metal plate made of a magnetic material to the entire surface of the ground semiconductor wafer that is not the element forming side, and a semiconductor element on the semiconductor wafer. Forming the wafer, dividing the wafer into individual chips, connecting the divided chips and leads, and sealing the element by exposing a part of a metal plate. Thus, a semiconductor device having an excellent heat dissipation effect is obtained.
【００１０】[0010]
【作用】上記した手段によれば積極的に半導体チップを
薄く形成することが可能となるため大幅に放熱効果が上
がるという効果が得られる。According to the above-mentioned means, it is possible to positively form the semiconductor chip thinly, so that the effect of greatly improving the heat radiation effect can be obtained.
【００１１】[0011]
【実施例】図１は本願発明の半導体装置の製造方法を用
いて製造した半導体装置を示した側面断面図、図２は本
実施例の半導体ウエハの張り合わせについて示した斜視
図、図３は本実施例に使用する治具を示した上面図と側
面断面図、図４は本実施例において治具にリードフレー
ムと半導体チップを配置したものを示した上面図と一部
側面断面図、図５は図４に示した半導体チップにワイヤ
ボンディングを行った例について示した一部側面断面
図、図６は図５に示したものを樹脂封止した状態を示し
た一部断面側面図である。FIG. 1 is a side sectional view showing a semiconductor device manufactured by using the method for manufacturing a semiconductor device of the present invention, FIG. 2 is a perspective view showing bonding of semiconductor wafers of this embodiment, and FIG. 5 is a top view and a side sectional view showing a jig used in the embodiment, FIG. 4 is a top view and a partial side sectional view showing a jig in which a lead frame and a semiconductor chip are arranged in this embodiment, and FIG. 6 is a partial side cross-sectional view showing an example in which the semiconductor chip shown in FIG. 4 is wire-bonded, and FIG. 6 is a partial cross-sectional side view showing the state shown in FIG. 5 which is resin-sealed.
【００１２】図１に示したように、本実施例による半導
体装置は表面に半導体素子の形成された半導体チップ１
と前記チップ１の下部に取付けられた鉄等の磁性体から
なる金属板２と、前記半導体チップ１上の電極と外部リ
ード４とを接続するワイヤ３と、前記半導体チップ１、
金属板２、ワイヤ３およびリード４の一部を含むように
形成される樹脂封止体５とからなる。また前記半導体チ
ップ１の裏面に取り付けられた金属板２は樹脂封止体５
から露出して形成される。As shown in FIG. 1, the semiconductor device according to the present embodiment has a semiconductor chip 1 having semiconductor elements formed on its surface.
A metal plate 2 made of a magnetic material such as iron attached to the lower part of the chip 1, a wire 3 for connecting an electrode on the semiconductor chip 1 and an external lead 4, the semiconductor chip 1,
It includes a metal plate 2, a wire 3, and a resin sealing body 5 formed so as to include a part of the lead 4. In addition, the metal plate 2 attached to the back surface of the semiconductor chip 1 is a resin sealing body 5.
It is exposed and formed.
【００１３】図２に示したように本実施例においては、
まず半導体ウエハ６を研削し、所望の厚さにしたものを
用意する。本半導体ウエハ６は通常に使用される半導体
ウエハより薄いもの、または最大限に薄く形成したもの
であることが望ましい。例えば約１００ミクロン程度に
研削したものが適当である。As shown in FIG. 2, in this embodiment,
First, the semiconductor wafer 6 is ground to prepare a wafer having a desired thickness. It is desirable that the present semiconductor wafer 6 is thinner than a normally used semiconductor wafer or is formed as thin as possible. For example, those ground to about 100 microns are suitable.
【００１４】次に半導体ウエハ６の半導体素子の形成さ
れない面に鉄等の磁性体からなる金属板２を接着剤によ
り貼付る。これにより薄くなったウエハ１でも通常のウ
エハと同様なハンドリングが可能となる。Next, the metal plate 2 made of a magnetic material such as iron is attached to the surface of the semiconductor wafer 6 on which the semiconductor elements are not formed by an adhesive. As a result, even the thinned wafer 1 can be handled in the same manner as a normal wafer.
【００１５】次に上記半導体ウエハ６の金属板２の貼付
られていない面に通常の前工程処理を行い、ウエハ６上
に半導体素子を形成する。Next, the surface of the semiconductor wafer 6 on which the metal plate 2 is not attached is subjected to a normal pre-process to form semiconductor elements on the wafer 6.
【００１６】次に前記前工程処理を行った後、各々の半
導体ウエハ６をウエハ下に貼付られた金属板７と一緒に
個々となるべきチップにダイシングにより分割する。Next, after the above-mentioned pre-process is performed, each semiconductor wafer 6 is divided by dicing into individual chips together with the metal plate 7 attached below the wafer.
【００１７】次に図３に示したように治具８を用意す
る。この治具８は各半導体チップ１および各個として形
成されたリードフレームに対応して形成されており、そ
の中央には封止されるべき形となるキャビティ９が形成
されている。前記キャビティ９中央の下部にチップ載置
部１０を有し、前記載置部１０は磁石で形成されてい
る。これによりチップを載置部１０に置いた場合は磁力
により半導体チップ下の金属板２が引き付けられ位置決
めがされる。Next, a jig 8 is prepared as shown in FIG. The jig 8 is formed corresponding to each semiconductor chip 1 and each lead frame formed as an individual, and a cavity 9 to be sealed is formed in the center thereof. A chip mounting portion 10 is provided below the center of the cavity 9, and the mounting portion 10 is formed of a magnet. Thus, when the chip is placed on the mounting portion 10, the metal plate 2 under the semiconductor chip is attracted and positioned by the magnetic force.
【００１８】図３に示したように上記治具８にリードフ
レーム１２が配置され、キャビティの半導体チップ載置
部１０に半導体チップ１が載せ置かれると内部リード１
３の先端部が半導体チップ１の周囲に配置されるように
なる。As shown in FIG. 3, when the lead frame 12 is placed on the jig 8 and the semiconductor chip 1 is placed on the semiconductor chip placing portion 10 of the cavity, the internal lead 1
The tip portion of 3 is arranged around the semiconductor chip 1.
【００１９】次にこの状態で内部リード１３と半導体チ
ップ１上の電極とをワイヤボンディングにより接続す
る。Next, in this state, the internal leads 13 and the electrodes on the semiconductor chip 1 are connected by wire bonding.
【００２０】その後この治具をこの状態でモールド金型
に組込、一般のものと同じようにモールドする。この際
金属板２は外部に露出した状態となって封止される。こ
の他の工程については他のものと同一である。After that, this jig is incorporated in a molding die in this state and molded in the same manner as a general one. At this time, the metal plate 2 is exposed to the outside and sealed. The other steps are the same as other steps.
【００２１】以上本願発明を本願の背景となった技術に
基づいて説明したが、本願は上記実施例に限定されるも
のではなく、その技術的範囲において種々変更可能であ
ることはいうまでもない。すなわち磁性体については鉄
以外のものも使用することが可能である。また治具とフ
レームを多連化し形成しても良い。The invention of the present application has been described above based on the technology as the background of the application, but it is needless to say that the application of the present invention is not limited to the above-described embodiments and various modifications can be made within the technical scope thereof. . That is, it is possible to use a magnetic material other than iron. Further, the jig and the frame may be formed in multiples.
【００２２】[0022]
【発明の効果】本願において開示される発明によって得
られるものの効果を記載すれば下記の通りである。The effects of the invention obtained by the invention disclosed in the present application are as follows.
【００２３】すなわちチップ厚を極めて薄く構成するこ
とが可能となり、また裏面に放熱効果の優れた磁性体を
使用することが可能と成るため、放熱効果の優れた半導
体装置を得ることができる。That is, the chip thickness can be made extremely thin, and a magnetic material having an excellent heat dissipation effect can be used on the back surface, so that a semiconductor device having an excellent heat dissipation effect can be obtained.
【図１】本願発明の半導体装置の製造方法を用いて製造
した半導体装置を示した側面断面図。FIG. 1 is a side sectional view showing a semiconductor device manufactured using a method for manufacturing a semiconductor device of the present invention.
【図２】本実施例の半導体ウエハの張り合わせについて
示した斜視図。FIG. 2 is a perspective view showing bonding of semiconductor wafers of this embodiment.
【図３】本実施例に使用する治具を示した上面図と側面
断面図。FIG. 3 is a top view and a side sectional view showing a jig used in this embodiment.
【図４】本実施例において治具にリードフレームと半導
体チップを配置したものを示した上面図と一部側面断面
図。4A and 4B are a top view and a partial side sectional view showing a jig in which a lead frame and a semiconductor chip are arranged in this embodiment.
【図５】図４に示した半導体チップにワイヤボンディン
グを行った例について示した一部側面断面図。5 is a partial side sectional view showing an example in which wire bonding is performed on the semiconductor chip shown in FIG.
【図６】図５に示したものを樹脂封止した状態を示した
一部断面側面図。6 is a partial cross-sectional side view showing the state shown in FIG. 5 sealed with resin.
１・・・半導体チップ、２・・・金属板、３・・・ボンディング
ワイヤ、４・・・リード、５・・・封止樹脂、６・・・半導体ウ
エハ、７・・・金属薄板、８・・・治具、９・・・キャビティ、
１０・・・チップ載置部、１１・・・枠、１２・・・リードフレ
ーム、１３・・・内部リード、1 ... Semiconductor chip, 2 ... Metal plate, 3 ... Bonding wire, 4 ... Lead, 5 ... Sealing resin, 6 ... Semiconductor wafer, 7 ... Metal thin plate, 8 ... Jigs, 9 ... cavities,
10 ... Chip mounting part, 11 ... Frame, 12 ... Lead frame, 13 ... Internal lead,
───────────────────────────────────────────────────── フロントページの続き (72)発明者 工藤 勝美 埼玉県入間郡毛呂山町大字旭台15番地 日 立東部セミコンダクタ株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsumi Kudo 15 Asahidai, Moroyama Town, Iruma-gun, Saitama Prefecture
Claims (2)
程と、前記研削した半導体ウエハの素子形成側でない面
全面に磁性体を貼付ける工程と、前記半導体ウエハ上に
半導体素子を形成する工程とを有することを特徴とする
半導体装置の製造方法。1. A step of grinding a semiconductor wafer to a desired thickness, a step of attaching a magnetic material to the entire surface of the ground semiconductor wafer that is not the element forming side, and a semiconductor element is formed on the semiconductor wafer. A method of manufacturing a semiconductor device, comprising:
程と、前記研削した半導体ウエハの素子形成側でない面
全面に磁性体からなる金属板を貼付ける工程と、前記半
導体ウエハ上に半導体素子を形成する工程と、前記ウエ
ハを個々となるべきチップに分割する工程と、前記分割
されたチップとリードとを接続する工程と、前記素子を
金属板を露出して樹脂により封止する工程とを有するこ
とを特徴とする半導体装置の製造方法。2. A step of grinding a semiconductor wafer to a desired thickness, a step of attaching a metal plate made of a magnetic material to the entire surface of the ground semiconductor wafer, which is not the element forming side, and a semiconductor on the semiconductor wafer. A step of forming an element, a step of dividing the wafer into individual chips, a step of connecting the divided chips and leads, and a step of sealing the element with a resin by exposing a metal plate A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12215595A JPH08316113A (en) | 1995-05-22 | 1995-05-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12215595A JPH08316113A (en) | 1995-05-22 | 1995-05-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08316113A true JPH08316113A (en) | 1996-11-29 |
Family
ID=14828968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12215595A Pending JPH08316113A (en) | 1995-05-22 | 1995-05-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08316113A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7126825B2 (en) * | 2004-12-07 | 2006-10-24 | Cleavage Enterprise Co., Ltd. | Combined chip/heat-dissipating metal plate and method for manufacturing the same |
-
1995
- 1995-05-22 JP JP12215595A patent/JPH08316113A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7126825B2 (en) * | 2004-12-07 | 2006-10-24 | Cleavage Enterprise Co., Ltd. | Combined chip/heat-dissipating metal plate and method for manufacturing the same |
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