JPH0831537B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, particularly a memory device.

(Prior Art) In recent years, semiconductor devices, particularly memory devices, have been highly demanded for higher integration, and a multi-gate structure has come to be widely used for read-only memory devices (hereinafter abbreviated as ROM) ( See, for example, Japanese Laid-Open Patent Publication No. 57-120367).

An example of a conventional method of manufacturing a ROM having a multi-gate structure will be described with reference to FIG. As shown in FIG.
A resist pattern 2 for forming an impurity diffusion layer corresponding to a ROM code to be stored is formed on a silicon substrate 1, and impurity ion implantation is performed to form an impurity diffusion layer 3 for controlling a threshold voltage on the silicon substrate 1. Next, as shown in FIG. 2B, a first gate oxide film 4 and a first gate electrode polysilicon film 5 are formed on the surface. Next, as shown in FIG. 2C, a resist pattern is formed by photolithography and etching is performed to form the first gate electrode 6. Next, as shown in FIG. 2 (d),
A second gate oxide film 7 and a polysilicon film 8 for a second gate electrode are formed on the surface. Next, as shown in FIG. 2 (e), a resist pattern 9 is formed by photolithography and etched to form a second gate electrode 10 as a first gate electrode as shown in FIG. 2 (f). It forms between 6.

(Problems to be Solved by the Invention) In the above-described conventional manufacturing method, when the second gate electrode is formed, the gate electrode material is directly etched using the resist pattern formed by photolithography. The second gate electrode is not completely formed between the first gate electrodes, that is, on the impurity diffusion layer of the channel portion of the MOS type transistor due to the shift of the distance, which adversely affects the transistor characteristics as the multi-gate structure. There was a flaw. Therefore, in the past, the second
At the time of forming the gate electrode, the resist dimension of the portion where the gate electrode material is left is made large so as to have a margin for misalignment, but this method inevitably causes the portion where the second gate electrode material is etched, that is, resist. The size of the part that does not remain is narrowed. As the circuit becomes highly integrated, the resolution in photolithography is limited, and this method has a drawback in that it is not possible to form a fine portion where a resist is not left in a fine pattern.

The object of the present invention is to eliminate the conventional drawbacks, and even if the resolution of photolithography itself cannot cope with miniaturization,
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can provide a margin for a patterning shift.

(Means for Solving Problems) According to a method of manufacturing a semiconductor device of the present invention, a gate is formed on a semiconductor substrate located between one source diffusion layer and one drain diffusion layer formed under the surface of the semiconductor substrate. A MOS type transistor having a plurality of gate electrodes arranged in series via an insulating film, and having an impurity diffusion layer for controlling two or more kinds of threshold voltages under the surface of a semiconductor substrate under each gate electrode, A first gate insulating film and a step of selectively forming a plurality of first gate electrodes on the first gate insulating film at equal intervals;
Forming a separation insulating film and a second gate insulating film for insulatingly separating the first gate electrode and the second gate electrode; forming a material of the second gate electrode on the surface; A step of forming a first insulating film as an intermediate layer on a material of the second gate electrode, a step of forming a second gate electrode pattern with the first insulating film by photolithography, and an intermediate layer Forming a second insulating film on the surface and forming a side frame of the second insulating film on the side wall of the first insulating film by anisotropic etching, and the first insulating film and the second insulating film. Is used to form a second gate electrode by etching the material of the second gate electrode using the pattern formed by the side frame of the above as a mask, and the first insulating film and the second insulating film serving as an intermediate layer. Silicon dioxide film or silicon nitride film It is intended to be used.

(Operation) According to the present invention, the alignment margin in forming the second gate electrode with respect to the impurity diffusion layer in the channel portion of the MOS transistor is expanded.

(Example) An example of the present invention will be described with reference to FIG. First
The drawings are sectional views showing a method of manufacturing a ROM having a multi-gate structure of the present invention in the order of steps. In the figure, the same parts as those of the conventional example shown in FIG. 2 are denoted by the same reference numerals, and the description thereof is partially omitted.

In FIG. 1A, the data is stored in the silicon substrate 1.
A resist pattern 2 for forming an impurity diffusion layer corresponding to the ROM code is formed, and an impurity diffusion layer 3 for controlling the threshold voltage is formed on the silicon substrate 1 by ion implantation of impurities. Next, as shown in FIG. 1B, a first gate oxide film 4 and a first gate electrode polysilicon film 5 are formed on the surface. Next, as shown in FIG. 1C, a resist pattern is formed by photolithography and etching is performed to form the first gate electrode 6. Next, FIG. 1 (d)
As shown in FIG. 3, an oxide film is formed on the surface to form a second gate oxide film 7 and an isolation oxide film 7'for separating the first gate electrode 6 and the second gate electrode. A polysilicon film 8 for two gate electrodes is formed, and a first oxide film 11 serving as an intermediate layer is further formed thereon by a chemical vapor deposition method (hereinafter abbreviated as a CVD method). Next, as shown in FIG. 1E, a resist pattern for forming a second gate electrode is formed by photolithography, and only the intermediate layer first oxide film 11 is etched to form a first oxide film pattern 12. To form. Next, as shown in FIG. 1 (f), the first oxide film
After the second oxide film is further formed on the 12 pattern by the CVD method, the side frame of the second oxide film is formed on the sidewall of the first oxide film pattern 12 by the anisotropic dry etching method.
Form 13. Next, as shown in FIG. 1 (g), the second
The second gate electrode polysilicon film 8 is etched by using the pattern of the oxide film having the oxide film side frame 13 as a mask to form the second gate electrode 14 between the first gate electrodes 6.

In this embodiment, the oxide film formed by the CVD method is used as a mask for etching the polysilicon film 8 for the second gate electrode, but it may be a silicon nitride film. Further, although polysilicon is used for the gate electrode, this may be a metal compound with silicon.

(Effects of the Invention) According to the present invention, the second gate electrode pattern is formed by photolithography by providing the step of etching the second gate electrode material using the pattern of the insulating film having the side frame. Since the alignment margin in this case is improved, it is possible to miniaturize without greatly depending on the resolving power of photolithography and the alignment accuracy of the mask aligner, and an ultra-large capacity memory device can be easily produced. Further, since the width of the side frame can be adjusted by designating the thickness of the second insulating film as the intermediate layer, the dimensional control of the second gate electrode is easy, and its practical effect is Is large.

[Brief description of drawings]

FIG. 1 is a sectional view showing the order of manufacturing steps of a semiconductor device in one embodiment of the present invention, and FIG. 2 is a sectional view showing the order of manufacturing steps of a conventional example. 1 ... Silicon substrate, 2 ... Impurity diffusion layer forming resist pattern, 3 ... Impurity diffusion layer for controlling threshold voltage, 4 ... First gate oxide film, 5 ... For first gate electrode Polysilicon film, 6 ... First gate electrode, 7 ... Second gate oxide film, 7 '... Isolation oxide film, 8 ... Second gate electrode polysilicon film, 11 ... Intermediate layer first Oxide film, 12 ... first oxide film pattern, 13 ... second oxide film side frame, 14 ... second gate electrode.

Claims (2)

[Claims] 1. A plurality of gate electrodes arrayed via a gate insulating film on a semiconductor substrate located between one source diffusion layer and one drain diffusion layer formed below the surface of the semiconductor substrate. In a MOS transistor having two or more kinds of impurity diffusion layers for controlling threshold voltages below the surface of a semiconductor substrate below each gate electrode, a first gate insulating film and a first gate electrode on the first gate insulating film are provided. A step of selectively forming a plurality of pieces at equal intervals, the first gate electrode and the second
Forming an insulating film for isolation and a second gate insulating film for insulatingly separating the gate electrode of the second gate electrode, forming a material of the second gate electrode on the surface, and forming a first intermediate layer.
Second insulating film is formed on the material of the second gate electrode, and the second insulating film is formed on the first insulating film by photolithography.
Forming a pattern for the gate electrode, and forming a second insulating film as an intermediate layer on the surface, and forming a side frame of the second insulating film on the side wall of the first insulating film by anisotropic etching. And a step of forming the second gate electrode by etching the material of the second gate electrode using the pattern formed by the first insulating film and the second insulating film as a mask. Of manufacturing a semiconductor device. 2. A semiconductor device according to claim 1, wherein a silicon dioxide film or a silicon nitride film is used for the first insulating film and the second insulating film as the intermediate layer. Method.