JPH08314407A - Display device - Google Patents

Abstract

PURPOSE: To suppress malfunction at the time of turning on/turning off a power source of a plasma display panel. CONSTITUTION: This device has a power source section 11 for generating low voltage Vcc, a ground potential GND and high voltage Vs, a display section 12 for performing prescribed display using low voltage Vcc, a ground potential GND and high voltage Vs as power source voltage, and a feedback circuit FC for feeding back low voltage Vcc and the ground potential GND inputted to the display section 12 from the power source section 11 to the power source section 11. The power source section 11 outputs high voltage Vs to the display section 12 after low voltage Vcc fed back from the display section 12 or the ground potential GND is inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to suppression of malfunction of a PDP (plasma display panel) when the power is turned on / off.

[0002]

2. Description of the Related Art A conventional PDP will be described below with reference to the drawings. The conventional PDP is shown in FIG.
As shown in (a), it has a power supply section 81 and a display section 82 (hereinafter, this apparatus is referred to as a first apparatus). Power supply 81
Is a circuit for generating a low voltage Vcc of about 5V, a high voltage Vs of about 185V and a ground potential GND from an AC voltage.

The display unit 82 is a device for performing a predetermined display by using the low voltage Vcc, the high voltage Vs and the ground potential GND generated by the power supply unit 81 as the power supply voltage. The power supply unit 81 is provided with connection terminals p1, p2, p3, the display unit 82 is provided with connection terminals q1, q2, q3, and the connection terminals p1, p2, p3 and the connection terminal q1 are provided. , Q2, q3 are respectively connected by a connector such as a connector.

According to the above apparatus, the power supply section 81 changes the AC voltage to the low voltage Vcc, the high voltage Vs, and the ground potential GN.
D is generated and supplied to the display unit 82 from the connection terminals p1, p2, p3 via the connection terminals q1, q2, q3.
At this time, the low voltage Vcc is input to the control circuit (not shown) in the display unit 82, and the high voltage Vs is input to the PDP via the X and Y drivers (not shown) in the display unit 82.
If the low voltage Vcc is not input to the control circuit and the high voltage Vs of about 185V is input before the device is ready to start up, the X and Y drivers may be damaged. , Especially when the power is turned on, the low voltage Vc
It is necessary to supply the high voltage Vs after supplying c to the display unit.

Therefore, in order to avoid this, a delay circuit D0 including a resistor R and a grounded capacitor C as shown in FIG. 11B is provided between the terminals p2 and q2 for transmitting Vs.
Is provided, and as a result, Vs is delayed, and Vs is supplied after Vcc is supplied, as shown in FIG. Further, FIG. 12 shows a circuit configuration of another conventional PDP (hereinafter, this device is referred to as a second device).

This second device has a power source section 91 and a display section 9
2, and the display unit 92 further includes an X driver 93, a Y driver 94, a control circuit 95, and a PDP panel 96. According to the above device, the low voltage Vcc generated by the power supply unit 91 is applied to the control circuit 95 and the high voltage Vs is applied to the X driver 93 and the Y driver 94 as power supply voltage, respectively, and X voltage is controlled under the control of the control circuit 95. Driver 9
3, the Y driver 94 applies a high voltage Vs to the PDP panel 96 and performs a predetermined operation, so that display is performed on the PDP panel 96.

[0007]

However, the above-described display device has the following problems. That is, in the first device as shown in FIG. 11, the terminal p for transmitting the high voltage Vs is provided for the purpose of protecting the circuit when the power is turned on.
A delay circuit D0 is inserted between 2 and q2, but Vs
Is a very high voltage of about 185 V, the elements of the resistor R and the capacitor C that can cope with this are considerably large, and it is difficult to reduce the device scale.

Further, in the second device as shown in FIG. 12, when the power is turned off, due to the electric charge remaining between the X electrode X and the Y electrode Y of the PDP panel (hereinafter referred to as residual electric charge), As shown in FIG. 13, the potential of the Y electrode Y becomes an indefinite potential, and this indefinite potential causes a malfunction of the circuit inside the display unit, which eventually leads to a circuit failure.

The present invention has been made in view of the problems of the conventional example, and avoids an unstable state of an internal circuit which occurs at the time of turning on the power while reducing the scale of the apparatus, and also, when the power is turned off, the inside of the panel is It is an object of the present invention to provide a display device capable of suppressing malfunction of a circuit due to residual charges as much as possible.

[0010]

The first object of the present invention is to provide a power supply unit for generating a low voltage, a ground potential and a high voltage as shown in FIG. 1, and a power supply voltage for supplying the low voltage, the ground potential and a high voltage. And a display unit for performing a predetermined display, and a feedback circuit for returning a low voltage or a ground potential input from the power supply unit to the display unit to the power supply unit, and the power supply unit,
The first display device is characterized in that the high voltage is output to the display unit after the low voltage or the ground potential fed back from the display unit is input.
3, a power supply unit for generating a low voltage, a ground potential and a high voltage as shown in FIG. 3, a display unit for performing a predetermined display using the low voltage, the ground potential and a high voltage as a power supply voltage, and the power supply unit. Has a recognition signal generation circuit that outputs a recognition signal to the power supply unit by recognizing that a low voltage or a ground potential is input from the power supply unit, and the power supply unit has the high voltage after the recognition signal is input. Is output to the display unit, and thirdly, the power supply unit is configured to output the low voltage or ground returned from the display unit as shown in FIG. 1 (b). The present invention is achieved by a first display device characterized in that it has a delay circuit that outputs the high voltage after a lapse of a fixed time from the time when an electric potential was input, and fourthly, the recognition signal generation circuit includes the power source. Low voltage or contact Be achieved by the second display device characterized by comprising a delay circuit for outputting a recognition signal after a predetermined time has elapsed from the time the potential is input, the fifth
In addition, as shown in FIG. 4, the certain time is longer than the time after the power is turned off until the high voltage drops to the initial value before the power is turned on after the power is turned off. A sixth display device is provided, and sixthly, a power supply unit for supplying a power supply voltage and a display panel are provided as shown in FIGS. 5 and 8, and a predetermined display is displayed on the display panel based on the power supply voltage. A display device having a display section for performing a power-off, and a detection circuit for detecting the power-off,
A sixth display device comprising a residual charge erasing circuit for erasing charges remaining on the display panel after the power-off is detected.
The present invention is achieved by a sixth display device characterized in that an internal battery is used as a power supply voltage for driving the residual charge erasing circuit. Eighth, the power supply voltage is selected from two types of voltages, a low voltage and a high voltage. This is achieved by a sixth display device characterized in that the high voltage is used as a power supply voltage for driving the residual charge erasing circuit. Ninth, the residual charge erasing circuit is provided at a time point when power-off is detected. Is achieved by the sixth, seventh or eighth display device characterized by having a delay circuit for erasing the electric charge remaining in the display panel after a lapse of a predetermined time from The display device according to the sixth, seventh, eighth, or ninth is characterized in that the residual charge erasing circuit includes: The present invention is achieved by the display device according to the sixth, seventh, eighth, ninth or tenth aspect, which outputs a power re-inhibit signal for prohibiting the power re-on at the time of erasing. In addition, the display unit is a plasma display panel, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, first
This is achieved by the 0 or 11th display device.

[0011]

[Operation] According to the first display device of the present invention, as shown in FIG. 1, the power supply unit has a feedback circuit for feeding back the low voltage or the ground potential input from the power supply unit to the display unit. Outputs a high voltage to the display unit after the low voltage or the ground potential fed back from the display unit is input.

Therefore, it is possible to surely output the high voltage to the display unit after the low voltage is input to the display unit, and like the conventional first device as shown in FIG. Since it is not necessary to provide a delay circuit composed of a large resistance and a capacitor of an element between the power supply section and the display section, it is possible to surely prevent malfunctions that may occur at power-on without increasing the scale of the device. It will be possible.

According to the second display device of the present invention,
As shown in FIG. 3, the power supply unit includes a recognition signal generation circuit that recognizes that a low voltage or a ground potential is input to the display unit and outputs a recognition signal to the power supply unit. High voltage is output to the display unit after is input. Therefore, it is possible to surely output the high voltage to the display unit after the low voltage is input to the display unit, and like the first conventional device shown in FIG. Since it is not necessary to provide the delay circuit D0 composed of a large resistance and a capacitor of the element between and, it is possible to surely suppress the malfunction that tends to occur at power-on without increasing the scale of the device.

Further, according to the third display device of the present invention, as shown in FIG. 1 (b), the power supply unit of the first display device of the present invention is a low voltage or ground potential fed back from the display unit. It has a delay circuit that outputs a high voltage after a lapse of a certain time from the time when the input signal is input. For this reason, the high voltage is output from the power supply unit after a certain period of time has elapsed after the low voltage or the ground potential was input, and the high voltage is output to the display unit after the low voltage is input to the display unit. The operation of turning on the power can be performed more reliably, and the operation when the power is turned on is more stable than the case of inputting the high voltage immediately after the low voltage or the ground potential is input to the display unit.

According to the fourth display device of the present invention,
The recognition signal generation circuit of the second display device of the present invention includes a delay circuit that outputs the recognition signal after a predetermined time has elapsed from the time when the low voltage or the ground potential was input from the power supply unit. Therefore, the recognition signal is output from the recognition signal generation circuit after a lapse of a certain time after the low voltage or the ground potential is input, and the high voltage is output to the display unit after the recognition signal is input, After the low voltage is input to the display unit, the operation of outputting the high voltage to the display unit can be surely executed.

Further, according to the fifth display device of the present invention, as shown in FIG. 4, the high voltage is applied after the power is turned on and off for a certain period of time in the third or fourth display device of the present invention. Since it is more than the time from the time of turning off the power to the initial value, the power is turned on again and the high voltage is applied to the display again before the high voltage in the display is sufficiently decreased to the initial value. It is possible to suppress the unstable circuit operation of (1) as much as possible.

Further, according to the sixth display device of the present invention, as shown in FIGS. 5 and 8, a power supply unit for supplying a power supply voltage and a display panel are provided, and a predetermined display panel is provided on the display panel based on the power supply voltage. A display device having a display unit for displaying, a detection circuit for detecting the power-off when the power is turned off,
It has a residual charge erasing circuit for erasing the electric charge remaining in the display panel after the power-off is detected.

Therefore, even if electric charges remain on the display panel when the power is turned off, the detection circuit detects the time when the power is turned off, and then the electric charges remaining on the display panel are erased by the residual charge erasing circuit. It is possible to prevent the malfunction of the circuit in the display unit and the circuit breakage caused by the residual charge. Furthermore, according to the seventh display device of the present invention, since the built-in battery is used as the power supply voltage for driving the residual charge erasing circuit in the sixth display device of the present invention,
A stable power supply voltage can be supplied to the residual charge erasing circuit even after the power is turned off, and the residual charge erasing circuit operates stably.
It is possible to surely erase the residual charges.

According to the eighth display device of the present invention,
The power supply voltage in the sixth display device of the present invention is composed of two types of voltage, a low voltage and a high voltage, and the high voltage is used as the power supply voltage for driving the residual charge erasing circuit. In the case of a circuit that gradually drops, even if this high voltage is used as the power supply voltage, the residual charge erasing circuit can be stably operated as in the seventh display device of the present invention.

Further, according to the ninth display device of the present invention, in the sixth, seventh or eighth residual charge erasing circuit of the present invention, the display panel is provided after a predetermined time has elapsed from the time when the power-off was detected. Since the residual charge is erased, it is possible to stabilize the residual charge erasing operation as compared with the case where the residual charge erasing is started from the unstable state of the circuit immediately after the power is turned off.

Further, according to the tenth display device of the present invention, the sixth, seventh, eighth or ninth display device of the present invention is provided with a storage means for storing the operation procedure after power-off. Therefore, it becomes possible to smoothly perform the residual charge erasing operation according to the operation procedure stored in the storage means. According to the eleventh display device of the present invention, in the sixth, seventh, eighth, ninth or tenth display device of the present invention, the residual charge erasing circuit is configured to prevent leakage of residual charges after power-off. Occasionally, a power-on prohibition signal that prohibits power-on again is output to the power supply unit, so the power is turned on again while the residual charge is being erased, and the charge is charged in the display panel. It is possible to suppress malfunctions and the like.

Further, according to the twelfth display device of the present invention, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth or tenth aspect of the present invention are provided. Since a plasma display panel which is a display panel to which a high voltage is applied and which has a capacitive component is used as the display unit of the eleventh display device, it is suitable as an example of the display device of the present invention.

[0023]

Embodiments of the present invention will now be described with reference to the drawings. (1) First Example A display device according to a first example of the present invention will be described below. As shown in FIG. 1A, this display device is a device including a display unit 12 having a PDP that displays a predetermined image and a power supply unit 11 that supplies a power supply voltage to the display unit 12.

As shown in FIG. 1A, the power supply unit 11 is a circuit that generates a low voltage Vcc of about 5V, a high voltage Vs of about 185V, and a ground potential GND from an AC voltage and supplies them to the display unit 12. . This is the connection terminals p11, p12, p1
3, p14, of which connection terminals p11, p1
3 and p14 are output terminals for the low voltage Vcc, the high voltage Vs, and the ground potential GND, respectively, and the connection terminal p12 is an input terminal for a feedback voltage Vr described later.

Further, the power supply section 11 is provided with a high voltage generation circuit 13 which outputs a high voltage Vs after receiving the feedback voltage Vr. The display unit 12 is a device having a PDP (not shown) that displays a predetermined image, and includes a PDP (not shown) and connection terminals q11, q12, q13, q14, among which the connection terminals q11, q13, q14 are The low voltage Vcc, the high voltage Vs, and the ground potential GND are input terminals, and the connection terminal q12 is an output terminal of a feedback voltage Vr described later.

The low voltage Vcc of about 5V input from the connection terminal q11 is input to a control circuit (not shown), and the high voltage Vs of about 185V input from the connection terminal q13 is passed through an X driver and a Y driver (not shown). Are supplied to a PDP (not shown). Under the control of this control circuit, the X driver and the Y driver are driven, whereby a predetermined display is made on the PDP.

A feedback circuit FC is formed in the display section 12 from the connection terminals q11 to q12, whereby the low voltage Vcc is used as the feedback voltage Vr and the connection terminal q1.
It is input to the connection terminal p12 via 2 and fed back to the power supply unit 11. Further, the power supply unit 11 and the display unit 12 have connection terminals p11, p12, p13, p14 and connection terminals q11, q.
It is connected via a connector such as a connector via 12, q13, and q14, respectively.

The operation of the above apparatus will be described below. First, when the power is turned on, the connection terminal p1
The low voltage Vcc and the ground potential GND are output via 1 and p14, respectively. At this point, the high voltage Vs has not been output yet. The low voltage Vcc and the ground potential GND output from the connection terminals p11 and p14 are the connection terminal q1.
1, q14 are input to the display unit 12.

When the low voltage Vcc is input to the display unit 12, the low voltage is connected to the connection terminal q12 via the feedback circuit FC.
Is output from the connection terminal p12 to the high voltage generation circuit 13 as the feedback voltage Vr. The high voltage generation circuit 13 is a circuit having a comparator 13A, a delay circuit 13B, and a high voltage output circuit 13C as shown in FIG. 1B, and the feedback voltage Vr is 0 in the initial state before the power is turned on. The output of the comparator 13A is at a high level (hereinafter referred to as "H").

As shown in FIG. 4A, when the low voltage Vcc is output and the feedback voltage Vr is fed back at almost the same time and input to the high voltage generation circuit 13, this is divided by the bleeder ratio of the resistors R1 and R2. , And is input to the inverting input (-) of the comparator 13A. At this point comparator 1
Since the high voltage Vs to be input to the non-inverting input (+) of 3A has not yet been output, the output of the comparator 13A becomes low level (hereinafter referred to as "L"). When this "L" is input to the delay circuit 13B, it is input to the high voltage output circuit 13C after being delayed by a predetermined time T1 by the delay circuit 13B as shown in FIG. 4 (a). Thus, when "L" is input to the high voltage output circuit 13C,
The high voltage Vs is output from the high voltage output circuit 13C.

The high voltage Vs thus output is input to the display unit 12 from the connection terminal p13 via the connection terminal q13. Through the above operation, after the feedback voltage Vr is input to the high voltage generation circuit 13, the high voltage Vs is output from the high voltage generation circuit 13 and input to the display unit 12 via the connection terminals p13 and q13. It will be.

In the display device having the above PDP, the low voltage Vcc is input to the control circuit (not shown),
The high voltage Vs is input to the PDP via the X and Y drivers (not shown), but the low voltage Vcc is not input to the control circuit,
If a high voltage Vs of about 185V is input before the device is ready to start up, there is a problem such as damage to the X and Y drivers. Therefore, especially when the power is turned on, the low voltage Vcc is displayed. Although it is necessary to supply the high voltage Vs after supplying the high voltage Vs to the power supply unit, in the display device according to the present embodiment, the low voltage Vcc is used as the feedback voltage Vr for the display unit 12 in the power supply unit 1.
A feedback circuit FC for returning to 1 is provided, and the power supply unit 11 is provided with a high voltage generation circuit 13 that outputs a high voltage Vs to the display unit 12 after the feedback voltage Vr is input, so that a low voltage is provided. It is possible to surely output the high voltage Vs to the display unit 12 after Vcc is input to the display unit 12.

As a result, the display unit 12 does not have to include a delay circuit having a large element size and having a large element size as in the conventional case, and is not inserted in the connection portion between the power supply unit 11 and the display unit 12.
Since the high voltage Vcc can be supplied after the low voltage Vcc has been input to, it is possible to reliably prevent malfunctions at power-on without increasing the device scale.

In the present embodiment, the high voltage output circuit 13 has a circuit configuration as shown in FIG. 1B, but the present invention is not limited to this, and as shown in FIG. Vr
It suffices if the output delay circuit 13D that outputs the high voltage Vs after delaying for a predetermined time from the time when the input is input is built in. Further, in this embodiment, as shown in FIG.
Is referred to as the feedback voltage Vr, but the present invention is not limited to this, and the same applies to the case where the ground potential GND is fed back to the power supply unit 11 as the feedback voltage Vr as shown in FIG. Produce the effect of.

(2) Second Example A display device according to a second example of the present invention will be described below with reference to the drawings. Note that the description of the items common to the first embodiment is omitted to avoid duplication. As shown in FIG. 3A, the display device according to the present embodiment is a device including a display unit 32 having a PDP that displays a predetermined image and a power supply unit 31 that supplies a power supply voltage to the display unit 32.

As shown in FIG. 3A, the power supply unit 31 is a circuit for generating a low voltage Vcc of about 5V, a high voltage Vs of about 185V, and a ground potential GND from an AC voltage and supplying them to the display unit 32. . This is the connection terminals p31, p32, p3
3, p34, of which connection terminals p31, p3
Low voltage Vcc, high voltage Vs, and ground potential GND are output from 3 and p34, respectively. The connection terminal p32 is an input terminal for a recognition signal Von described later.

The display unit 32 is a device having a PDP (not shown) that displays a predetermined image, and includes a PDP (not shown) and connection terminals q31, q32, q33, q34, among which connection terminals q31, q33. , Q34 are input terminals for the low voltage Vcc, the high voltage Vs, and the ground potential GND, respectively, and the connection terminal q32 is an output terminal for a recognition signal Von described later.

The display unit 32 also includes a recognition signal generation circuit 33 that outputs the recognition signal Von to the power supply unit 31 after the low power supply Vcc is input. The low voltage Vcc of about 5V input from the connection terminal q31 is input to the control circuit (not shown), and the high voltage Vs of about 185V input from the connection terminal q33 is input to the PDP via the X driver and the Y driver (not shown). Supplied. Under the control of this control circuit, the X driver and the Y driver are driven, whereby a predetermined display is made on the PDP.

Further, the power supply section 31 and the display section 32 have connection terminals p31, p32, p33, p34 and a connection terminal q31.
Connections such as connectors are provided via q32, q33, and q34, respectively. The operation of the above device will be described below. First, when the power is turned on, the low voltage Vcc and the ground potential GND are output from the power supply unit 31 via the connection terminals p31 and p34, respectively. At this point in time, the high voltage Vs has not been output from the power supply unit 31.

The low voltage Vcc and the ground potential GND output from the connection terminals p31 and p34 respectively correspond to the connection terminal q3.
1, q34 are input to the display unit 32. When the low voltage Vcc is input to the display unit 32, the low voltage Vcc is also input to the recognition signal generation circuit 33 connected to the connection terminal q31 at the same time. The recognition signal generation circuit 33 is a circuit including a comparator 33A and a delay circuit 33B as shown in FIG.

When a low voltage Vcc is input to this circuit,
The output of the comparator 33A becomes "H", which is input to the delay circuit 33B and delayed by the delay circuit 33B for a certain period of time to generate the recognition signal Von. The recognition signal Von is output from the recognition signal generation circuit 33 to the connection terminal q32 and is input to the power supply unit 31 via the connection terminal p32, and the connection terminal p of the power supply unit 31 is not input until this is input.
The high voltage Vs is output from 33 and input to the display unit 32 via the connection terminal q33.

A timing chart of the operation during this period is shown in FIG.
It shows in (b). As shown in FIG. 4B, the low voltage V
After the cc rises and is input to the display unit 32, the recognition signal Von rises and is output to the power supply unit after being delayed for a predetermined time T3, and at the same time as the rise, the high voltage Vs rises and is output to the display unit 32. You can see that it is done.

As described above, in the display device according to the present embodiment, the recognition signal generation circuit 3 that outputs the recognition signal Von to the power supply unit 31 after the low voltage Vcc is input into the display unit 32.
3 is provided, and the power supply unit 31 uses the recognition signal Von.
Since the high voltage Vs is output to the display unit 32 after is input, it is possible to reliably output the high voltage Vs to the display unit 12 after the low voltage Vcc is input to the display unit 12.

As a result, similarly to the first embodiment,
It is possible to supply the high voltage Vcc after the low voltage Vcc is input to the display unit 32 without inserting a delay circuit having a large scale such as a resistor and a capacitor into the connection unit as in the conventional case. It is possible to reliably prevent malfunctions when the power is turned on without increasing the number. (3) Third Example A display device according to a third example of the present invention will be described below with reference to the drawings. As shown in FIG. 5, this display device is a device having a display section 42 having a PDP panel PP for displaying a predetermined image and a power supply section 41 supplying a power supply voltage to the display section 42.

The power supply section 41 is a circuit for outputting to the display section 42 a low voltage Vcc of about 5V and a high voltage Vs of about 185V which are power supply voltages for driving. The display unit 42 includes an X driver XD, a Y driver YD, a power supply cutoff detection circuit 43, a residual charge erasing circuit 44, a control circuit 45, and a PDP panel PP, and uses a low voltage Vcc and a high voltage Vs as power supply voltages for PD.
It is a device for displaying a predetermined display on a P panel.

The X driver XD and the Y driver YD are circuits that apply the high voltage Vs supplied from the power supply section 41 to the X electrodes X and Y electrodes Y of the PDP panel PP as sustain voltages. As shown in FIG. 5, the power-off detection circuit 43 includes an auxiliary power source 43A composed of a battery, a CPU 43B,
It has a ROM 46, detects the time when the high voltage Vs and the low voltage Vcc are no longer supplied from the power supply unit 41 (hereinafter referred to as power-off), and transmits a disconnection recognition signal CS as the detection result to the control circuit 45. Circuit.

The auxiliary power supply 43A is a circuit for supplying the power supply voltage Vcc2 of the power supply cutoff detection circuit 43 and the control circuit 45 after the power supply is cut off. The CPU 43B is a circuit device that controls the operation of the power-off detection circuit 43, and the ROM 46 is an example of a storage unit, and has a table 1 and a table 2 in which a sequence indicating an operation procedure of the entire display unit 42 is stored. . Table 1 stores a first sequence showing an operation procedure at the time of performing a normal display after power is turned on, and Table 2 stores a second sequence showing an operation procedure after turning off the power.

The residual charge erasing circuit 44 is a switching circuit connected to the X electrode X, and is turned on when the leak signal LS output from the control circuit 45 when the power is turned off is input, and remains on the PDP panel PP. This is a circuit for erasing the electric charges that are generated. The control circuit 45 is a circuit that controls all operations related to the display of the display unit 42. When the power is turned off, the leak signal LS is output to the residual charge erasing circuit 44. Further, this power supply voltage is a low voltage Vc during normal operation.
c.

The operation of the above apparatus will be described below.
First, the power is turned on, and the low voltage Vcc and the high voltage Vs are applied from the power supply unit 41 to the display unit 42. At this time, the residual charge erasing circuit 44 is off. The low voltage Vcc is applied to the control circuit 45, which controls the low voltage Vc.
It operates using c as the power supply voltage. In addition, this low voltage Vcc
Is also input to the power-off detection circuit 43 at the same time, specifically, is input to the CPU 43B via the diode D41. At this time, the power-off detection circuit 43 outputs the low voltage V
It operates using cc as the power supply voltage.

The high voltage Vs is supplied to the X driver XD and the Y driver YD as their power supply voltage, and PD
The high voltage Vs is applied to the X electrode X and the Y electrode Y of the P panel PP. Then, under the control of the control circuit 45, the X driver X
The D, Y driver YD applies a sustain voltage to the PDP panel PP, and a predetermined image is displayed on the PDP panel PP.

Up to this point, the device described above is
It is driven in the first sequence stored in the table 1 built in the ROM 46. That is, Xup and Xdown which are switching signals when the voltage is supplied / not supplied to the X electrode X.
The potential of the X electrode X rises / falls in synchronism with the rising edge of the Y electrode, and similarly Yup and Ydown, which are switching signals when the voltage is supplied / not supplied to the Y electrode Y.
The potential of the Y electrode Y rises / falls in synchronism with the rising edge of.

After that, the operation in the case where the power supply is cut off and the low voltage Vcc and the high voltage Vs are not supplied from the power supply unit 41 will be described below. PDP when power is off
The charges accumulated by the application of the high voltage Vs still remain in the panel PP. Since the low voltage Vcc is no longer supplied from the power supply unit, instead of this, the auxiliary power supply voltage Vcc2 (Vcc2 <Vcc,
In this case, about 3V) is the CPU 43B and the control circuit 45.
Power supply voltage.

The CPU 43B recognizes that the power supply is cut off by changing the power supply voltage from the low voltage Vcc to the auxiliary power supply voltage Vcc2, and outputs the power supply cutoff recognition signal CS to the control circuit 45. As a result, the control circuit 45 switches the control sequence from the first sequence in the table 1 built into the ROM 46 to the second sequence in the table 2 as shown in FIG. 6, and at the same time, outputs the leak signal LS to the residual charge erasing circuit 44. Output.

When the leak signal LS is output to the residual charge erasing circuit 44, the switching circuit is turned on and the potential of the X electrode X of the PDP panel PP is forcibly lowered to the ground potential GND and remains on the PDP panel PP. The electric charges that have been applied fall to the ground potential GND, and the residual electric charges are erased (FIG. 6). During this period, the CPU 43B simultaneously inputs the power re-inhibit signal Vchk as shown in FIG.
During this period, the power is not turned on again.

As described above, according to the display device of the present embodiment, after the power is turned off, it is detected and the electric charge remaining between the PDP panels PP is erased. It is possible to prevent the malfunction of the device due to the uncertain potential of the X electrode and the circuit breakdown. Further, during the residual charge erasing period, the power re-inhibit signal Vchk is output to the power supply unit 41, and even if the power is mistakenly turned on, the power is not turned on again during this period. It is possible to prevent malfunctions and the like that occur when the power is turned on again.

In this embodiment, a built-in battery of about 3 V is used as the auxiliary power source 43A, but the present invention is not limited to this, and a circuit in which the high voltage Vs falls gently as shown in FIG. When a constant is set, this high voltage Vs is divided by the bleeder ratio of resistors connected in series to generate a DC voltage of about 3V, and the same effect can be obtained by replacing the auxiliary power source 43A.

(4) Fourth Embodiment A display device according to the fourth embodiment of the present invention will be described below with reference to the drawings. Descriptions of matters common to the third embodiment will be omitted to avoid duplication. This display device, as shown in FIG. 8, is a PDP that displays a predetermined image.
The device includes a display unit 52 having a panel PP and a power supply unit 51 supplying a power supply voltage to the display unit 52.

The power supply section 51 is a circuit for outputting to the display section 52 a low voltage Vcc and a high voltage Vs which are power supply voltages for driving. The display unit 52 includes an X driver XD, a Y driver YD, a power supply cutoff detection circuit 53, a residual charge erasing circuit 54, a control circuit 55, and a PDP panel PP, and the low voltage Vcc and the high voltage Vs are used as power supply voltages to the PDP panel. Is a device for displaying.

The power-off detection circuit 53 uses the auxiliary power source 53A,
It has a CPU 53B and a ROM 56. Since the circuit components up to the above are almost the same as those in the third embodiment, detailed description thereof will be omitted. The feature of the circuit of this embodiment different from that of the third embodiment is the configuration of the residual charge erasing circuit 54 and the operation procedure when the ROM 56 storing the control sequence performs a normal display operation after power is turned on. The two points are that only the first sequence is stored.

The residual charge erasing circuit 54 is provided in the final stage of the X driver XD as shown in FIG. 8 and is a MOS transistor T1 to T serving as a switching element as shown in FIG.
4 and turns on / off based on the high voltage Vs, the leak signal LS, the disconnection recognition signal Cdown, and the auxiliary power supply voltage Vcc2 (low voltage Vcc during normal operation), and P when power off.
This is a circuit for erasing the residual charges of the DP panel PP.

The operation of the above apparatus will be described below.
First, the power is turned on, and the low voltage Vcc and the high voltage Vs are applied from the power supply unit 51 to the display unit 52. The low voltage Vcc is applied to the control circuit 55, and the control circuit 55 controls the low voltage Vc.
It is driven with c as the power supply voltage. In addition, this low voltage Vc
c is also input to the power-off detection circuit 53 at the same time,
Specifically, it is input to the CPU 53B via the diode D51. At this time, the power supply cutoff detection circuit 53 is driven with the low voltage Vcc as the power supply voltage.

The high voltage Vs is supplied to the X driver XD and the Y driver YD as their power supply voltage, and PD
The high voltage Vs is applied to the X electrode X and the Y electrode Y of the P panel PP. Then, under the control of the control circuit 55, the X driver X
The sustain voltage is applied / not applied to the PDP panel PP by the D and Y drivers YD, and a predetermined image is displayed on the PDP panel PP.
Is displayed in.

At this time, in the residual charge erasing circuit 54, the low voltage Vcc, the disconnection recognition signal Cdown of "L", and the high voltage Vs.
And the leak signal LS of "H" are input, the MOS transistor T1 is ON, and the MOS transistor T2 is OF.
F, the MOS transistor T3 is on, and the MOS transistor T4 is off. Therefore, the high voltage Vs output from the X driver XD is directly applied to the X electrode X shown in FIG. At this time, the control circuit is driven in the sequence as shown in FIG. 10, that is, the first sequence stored in the table 1 built in the ROM 56.

After that, when the power supply is cut off and the low voltage Vcc and the high voltage Vs are not supplied from the power supply unit 51, when the power supply is cut off, the charges accumulated by the application of the high voltage Vs still remain in the PDP panel PP. ing. Low voltage Vc
Since c is not supplied from the power supply unit 51, instead of this, the auxiliary power supply voltage Vcc output from the auxiliary power supply 53A is output.
2 (Vcc2 <Vcc) is the CPU 53B and the control circuit 55.
Power supply voltage.

The CPU 53B recognizes that the power supply is cut off by changing the power supply voltage from the low voltage Vcc to the auxiliary power supply voltage Vcc2, and outputs the cutoff recognition signal Cdown to the residual charge erasing circuit 54. At the same time, the control circuit 55 also recognizes that the power supply is cut off because the power supply voltage has changed to the auxiliary power supply voltage Vcc2, and outputs the leak signal LS of "L" to the residual charge erase circuit 54.

At this time, the residual charge erasing circuit 54 has a low voltage Vcc, a disconnection recognition signal Cdown of "H", and a high voltage Vs.
And the leak signal LS of "L" are input, the MOS transistor T1 is OFF, and the MOS transistor T2 is O.
Since N, the MOS transistor T3 is OFF, and the MOS transistor T4 is ON, the potential of the X electrode X drops to the ground potential GND, and the residual charge remaining in the PDP panel PP is erased.

As described above, according to the display device of this embodiment, as in the third embodiment, after the power is turned off, it is detected and the electric charge remaining between the PDP panels PP is erased. Therefore, it is possible to prevent the malfunction of the device and the circuit breakdown due to the undefined potential of the X electrode, which has been conventionally caused by the residual charge.

[0068]

As described above, according to the first display device of the present invention, the display section has the feedback circuit for returning the low voltage or the ground potential from the power supply section to the power supply section, and the power supply section is The low voltage or the ground potential fed back from the display unit is input, and then the high voltage is output to the display unit.

Therefore, it is possible to surely output the high voltage to the display unit after the low voltage is input to the display unit, without causing an increase in the size of the apparatus, and to prevent malfunctions that are likely to occur when the power is turned on. It is possible to surely suppress it. Further, according to the second display device of the present invention, the display unit has a recognition signal generation circuit that recognizes that a low voltage or a ground potential is input from the power supply unit and outputs a recognition signal to the power supply unit. Moreover, the power supply unit outputs the high voltage to the display unit after the recognition signal is input.

Therefore, it is possible to surely output the high voltage to the display unit after the low voltage is input to the display unit, and the malfunction which tends to occur at power-on without increasing the scale of the device. It is possible to surely suppress it. Further, according to the third display device of the present invention,
Since the power supply unit of the display device has a delay circuit that outputs a high voltage after a lapse of a certain time from the time when the low voltage or the ground potential fed back from the display unit is input, the low voltage is input to the display unit. After that, the operation of outputting a high voltage to the display unit can be executed more reliably.

According to the fourth display device of the present invention,
Since the recognition signal generation circuit of the second display device of the present invention includes the delay circuit that outputs the recognition signal after a predetermined time has elapsed from the time point when the low voltage or the ground potential is input from the power supply unit, the low voltage After the is input to the display unit, the operation of outputting a high voltage to the display unit can be surely executed.

Furthermore, according to the fifth display device of the present invention, the power is turned on for a certain period of time in the third or fourth display device of the present invention, and after the power is turned off, the high voltage is initially set from the time when the power is turned off. Since it is more than the time to drop to the value, the power is turned on again and the high voltage is applied to the display again before the high voltage in the display falls to the initial value sufficiently, which causes the circuit operation of the display to be unstable. It becomes possible to suppress becoming.

Further, according to the sixth display device of the present invention, the power supply section for supplying the power supply voltage and the display panel having the capacitive load are provided, and the display for performing a predetermined display on the display panel based on the power supply voltage. And a residual charge erasing circuit for erasing charges remaining on the display panel after the power-off is detected when the power is turned off.

Therefore, even if electric charge remains in the display panel having a capacitive load when the power is turned off, it is possible to prevent the malfunction of the circuit in the display unit and the circuit destruction which have been conventionally caused by the residual electric charge. become. Further, according to the seventh display device of the present invention, since the built-in battery is used as the power supply voltage for driving the residual charge erasing circuit in the sixth display device of the present invention, the residual charge erasing circuit can be used even after the power is turned off. It is possible to supply a stable power supply voltage, stably operate the residual charge erasing circuit, and surely erase the residual charge.

According to the eighth display device of the present invention,
The power supply voltage in the sixth display device of the present invention is composed of two types of voltage, a low voltage and a high voltage, and the high voltage is used as the power supply voltage for driving the residual charge erasing circuit. In the case of a circuit that gradually drops, even if this high voltage is used as the power supply voltage, the residual charge erasing circuit can be stably operated as in the seventh display device of the present invention.

Further, according to the ninth display device of the present invention, in the sixth, seventh or eighth residual charge erasing circuit of the present invention, the display panel is provided after a certain time has elapsed from the time when the power-off was detected. Since the residual charge is erased, it is possible to stabilize the residual charge erasing operation as compared with the case where the residual charge erasing is started from the unstable state of the circuit immediately after the power is turned off.

Further, according to the tenth display device of the present invention, the sixth, seventh, eighth or ninth display device of the present invention is provided with a storage means for storing the operation procedure after power-off. Therefore, it becomes possible to smoothly perform the residual charge erasing operation according to the operation procedure stored in the storage means. According to the eleventh display device of the present invention, in the sixth, seventh, eighth, ninth or tenth display device of the present invention, the residual charge erasing circuit is configured to prevent leakage of residual charges after power-off. Occasionally, a power-on prohibition signal that prohibits power-on again is output to the power supply unit, so the power is turned on again while the residual charge is being erased, and the charge is charged in the display panel. It is possible to suppress malfunctions and the like.

Furthermore, according to the twelfth display device of the present invention, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, or tenth aspect of the present invention can be obtained. Since a plasma display panel which is a display panel to which a high voltage is applied and which has a capacitive component is used as the display unit of the eleventh display device, it is suitable as an example of the display device of the present invention.

[Brief description of drawings]

FIG. 1 is a first diagram illustrating a display device according to a first embodiment of the present invention.

FIG. 2 is a second diagram illustrating the display device according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a display device according to a second embodiment of the present invention.

FIG. 4 is a timing chart explaining the operation of the display device according to the first and second embodiments of the present invention.

FIG. 5 is a circuit configuration diagram of a display device according to a third embodiment of the present invention.

FIG. 6 is a first timing chart explaining the operation of the display device according to the third embodiment of the present invention.

FIG. 7 is a second timing chart explaining the operation of the display device according to the third embodiment of the present invention.

FIG. 8 is a circuit configuration diagram illustrating a display device according to a fourth embodiment of the present invention.

FIG. 9 is a circuit configuration diagram illustrating an essential part of a display device according to a fourth example of the present invention.

FIG. 10 is a timing chart explaining the operation of the display device according to the fourth example of the present invention.

FIG. 11 is a diagram illustrating a first conventional display device.

FIG. 12 is a circuit configuration diagram of a second conventional display device.

FIG. 13 is a diagram illustrating a problem of the conventional second display device.

[Explanation of symbols]

 11 Power Supply Section 12 Display Section 13 High Voltage Generation Circuit 13A Comparator 13B Delay Circuit 13C High Voltage Output Circuit 13D Output Delay Circuit 21 Power Supply Section 22 Display Section 23 High Voltage Generation Circuit 31 Power Supply Section 32 Display Section 33 Recognition Signal Generation Circuit 33A Comparator 33B Delay circuit 41 Power supply unit 42 Display unit 43 Current disconnection detection circuit 43A Auxiliary power supply 43B CPU 44 Residual charge erasing circuit 45 Control circuit 46 ROM X X electrode Y Y electrode XD X driver YD Y driver 51 Power supply unit 52 Display unit 53 Current disconnection detection Circuit 53A Auxiliary power supply 53B CPU 54 Residual charge erasing circuit 55 Control circuit 56 ROM Vcc Low voltage Vs High voltage GND Ground potential Vr Feedback voltage Von Recognition signal LS Leak signal CS Disconnection recognition signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Fujisaki 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Hideo Kimura 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Tomokatsu Kishi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (12)

[Claims] 1. A power supply unit that generates a low voltage, a ground potential, and a high voltage, a display unit that performs a predetermined display using the low voltage, the ground potential, and a high voltage as a power supply voltage, and the display from the power supply unit. A feedback circuit for feeding back a low voltage or ground potential input to the power supply unit to the power supply unit, and the power supply unit outputs the high voltage after the low voltage or ground potential fed back from the display unit is input. A display device which outputs to the display unit. 2. A power supply unit for generating a low voltage, a ground potential and a high voltage, a display unit for performing a predetermined display using the low voltage, a ground potential and a high voltage as a power supply voltage, and a low voltage from the power supply unit. A recognition signal generating circuit that recognizes that a voltage or a ground potential is input and outputs a recognition signal to the power supply unit, wherein the power supply unit displays the high voltage after the recognition signal is input. A display device characterized by outputting to a section. 3. The power supply unit includes a delay circuit that outputs the high voltage after a lapse of a certain time from a time point when the low voltage or the ground potential fed back from the display unit is input. Item 2. A display device according to item 1. 4. The recognition signal generation circuit includes a delay circuit that outputs a recognition signal after a lapse of a fixed time from a time point when a low voltage or a ground potential is input from the power supply unit. 2. The display device according to item 2. 5. The constant time is longer than the time after the power is turned off until the high voltage drops from the power-off time to the initial value before the power was turned on.
Alternatively, the display device according to claim 4. 6. A display device comprising: a power supply unit for supplying a power supply voltage; and a display unit, which includes a display panel and displays a predetermined display on the display panel based on the power supply voltage. A display device comprising: a detection circuit for detecting power-off; and a residual charge erasing circuit for erasing charges remaining on the display panel after the power-off is detected. 7. The display device according to claim 6, wherein a built-in battery is used as a power supply voltage for driving the residual charge erasing circuit. 8. The display device according to claim 6, wherein the power supply voltage is composed of two kinds of voltages, a low voltage and a high voltage, and the high voltage is used as a power supply voltage for driving the residual charge erasing circuit. . 9. The residual charge erasing circuit has a delay circuit for erasing the electric charge remaining in the display panel after a lapse of a predetermined time from the time when the power-off is detected. The display device according to claim 7 or 8. 10. The display device according to claim 6, further comprising storage means for storing an operation procedure after power-off. 11. The residual charge erasing circuit outputs, to the power supply unit, a power re-inhibit signal for prohibiting the re-turn-on of the power when erasing the residual charge after the power is turned off. The display device according to claim 7, claim 8, claim 9, or claim 10. 12. The display unit is a plasma display panel, claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 7. The display device according to claim 8, claim 9, claim 10, or claim 11.