JP2003263126A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress malfunction occurring when supplying the power source of a plasma display panel and when interrupting the power source. <P>SOLUTION: This device is provided with a power source part 41 for supplying a power source voltage Vs to a display part 42; and the display part 42 having a display panel PP and for performing prescribed display on the display panel based on the power source voltage Vs. Moreover, the display device has a detecting circuit 43 for detecting the interruption of the power source when the power source is interrupted and a residual electric charge erasing circuit 44 for erasing electric charges remaining on the display panel after the interruption of the power source is detected. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to suppression of malfunction of a PDP (plasma display panel) when the power is turned on / off.

[0002]

2. Description of the Related Art A conventional PDP will be described below with reference to the drawings.

A conventional PDP has a power supply section 81 and a display section 82 as shown in FIG. 11 (a) (hereinafter, this apparatus is referred to as a first apparatus).

The power supply unit 81 has a low voltage Vcc of about 5V, a high voltage Vs of about 185V and a ground potential G from an AC voltage.
This is a circuit for generating ND.

The display unit 82 is a device for performing a predetermined display by using the low voltage Vcc, the high voltage Vs and the ground potential GND generated by the power supply unit 81 as the power supply voltage. The power supply unit 81 is provided with connection terminals p1, p2, p3, the display unit 82 is provided with connection terminals q1, q2, q3, and the connection terminals p1, p2, p3 and the connection terminal q1 are provided. , Q2, q3 are respectively connected by a connector such as a connector.

According to the above apparatus, the power supply unit 81 changes the AC voltage to the low voltage Vcc, the high voltage Vs and the ground potential GN.
D is generated and supplied to the display unit 82 from the connection terminals p1, p2, p3 via the connection terminals q1, q2, q3.

At this time, the low voltage Vcc is input to a control circuit (not shown) in the display section 82, and the high voltage Vs is displayed in the display section 82.
The low voltage Vcc is not input to the control circuit, and the high voltage Vs of about 185V is first input before the device is ready to start. If it is input to, there is a problem that the X and Y drivers are damaged. Therefore, especially when the power is turned on, it is necessary to supply the high voltage Vs after supplying the low voltage Vcc to the display unit.

Therefore, in order to avoid this, a delay circuit D0 consisting of a resistor R and a grounded capacitor C as shown in FIG. 11B is provided between the terminals p2 and q2 for transmitting Vs.
Is provided, and as a result, Vs is delayed, and Vs is supplied after Vcc is supplied, as shown in FIG.

FIG. 12 shows the circuit configuration of another conventional PDP (hereinafter, this device will be referred to as a second device).

This second device has a power supply section 91 and a display section 9
2, and the display unit 92 further includes an X driver 93, a Y driver 94, a control circuit 95, and a PDP panel 96.

According to the above apparatus, the low voltage Vcc generated by the power supply unit 91 is applied to the control circuit 95, and the high voltage Vs is applied to the X driver 93 and the Y driver 94, respectively, as the power supply voltage, thereby controlling the control circuit 95. Based on the X driver 93 and the Y driver 94, the high voltage V is applied to the PDP panel 96.
By applying s for a predetermined operation, the PDP panel 96
Is displayed.

[0012]

However, the above-described display device has the following problems.

That is, in the first device as shown in FIG. 11, the high voltage V is used for the purpose of protecting the circuit when the power is turned on.
Although the delay circuit D0 is inserted between the terminals p2 and q2 for transmitting s, since Vs is an extremely high voltage of about 185V, the elements of the resistor R and the capacitor C that can cope with this are considerably large, and the device It becomes difficult to reduce the scale.

Further, in the second device as shown in FIG. 12, when the power is turned off, the electric charge remaining between the X electrode X and the Y electrode Y of the PDP panel (hereinafter referred to as residual electric charge) causes As shown in FIG. 13, the potential of the Y electrode Y becomes an indefinite potential, and this indefinite potential causes a malfunction of the circuit inside the display unit, which eventually leads to a circuit failure.

The present invention was made in view of the problems of the conventional example, and avoids an unstable state of an internal circuit which occurs when the power is turned on while reducing the scale of the apparatus, and when the power is turned off, the inside of the panel is reduced. It is an object of the present invention to provide a display device capable of suppressing malfunction of a circuit due to residual charges as much as possible.

[0016]

The above-mentioned problems are as follows. First, as shown in FIGS. 5 and 8, a power supply unit for supplying a power supply voltage and a display panel are provided, and the display panel is provided based on the power supply voltage. A display device having a display unit for displaying a predetermined display, wherein a detection circuit for detecting the power-off when the power is turned off,
The present invention is achieved by the first display device, further comprising: a residual charge erasing circuit that erases electric charges remaining in the display panel after the power-off is detected.
The present invention is achieved by a second display device characterized in that an internal battery is used as a power supply voltage for driving the residual charge erasing circuit. Thirdly, the power supply voltage is composed of two types of voltage, a low voltage and a high voltage. This is achieved by a third display device characterized in that the high voltage is used as a power supply voltage for driving the residual charge erasing circuit, and fourth, the residual charge erasing circuit is provided at a time point when power-off is detected. Is achieved by the display device according to any one of the first to third aspects, which has a delay circuit for erasing the electric charge remaining in the display panel after a lapse of a predetermined time from the fifth to the fifth. The present invention is achieved by any one of the first to fourth display devices, characterized in that the residual charge erasing circuit erases the residual charge after the power is turned off. Be achieved by the first to fifth display device having any one of and outputs the power is turned on again prohibiting signal for prohibiting the power cycle to the power supply unit in,
Seventh, the display unit is achieved by any one of the first to sixth display devices, which is a plasma display panel.

[0017]

According to the first display device of the present invention, as shown in FIG.
A display device having a power supply unit for supplying a power supply voltage as shown in FIG. 8 and a display unit that includes a display panel and performs a predetermined display on the display panel based on the power supply voltage. It has a detection circuit for detecting disconnection and a residual charge erasing circuit for erasing charges remaining on the display panel after the power-off is detected.

Therefore, even if electric charges remain on the display panel when the power is turned off, the detection circuit detects the time when the power is turned off, and then the electric charges remaining on the display panel are erased by the residual charge erasing circuit. It is possible to prevent the malfunction of the circuit in the display unit and the circuit breakage caused by the residual charge.

Further, according to the second display device of the present invention,
Since the built-in battery is used as a power supply voltage for driving the residual charge erasing circuit in the first display device of the present invention, a stable power supply voltage can be supplied to the residual charge erasing circuit even after the power is turned off, and the residual charge erasing can be performed. It is possible to operate the circuit stably and surely erase the residual charges.

According to the third display device of the present invention,
The power supply voltage in the first display device of the present invention is composed of two types of voltage, a low voltage and a high voltage, and the high voltage is used as the power supply voltage for driving the residual charge erasing circuit. In the case of a circuit that gradually drops, even if this high voltage is used as the power supply voltage, the residual charge erasing circuit can be stably operated as in the second display device of the present invention.

Further, according to the fourth display device of the present invention, in the residual charge erasing circuit according to any one of the first to third embodiments of the present invention, the display panel is provided after a predetermined time has elapsed from the time when the power-off was detected. Since the electric charge remaining in is erased,
It becomes possible to stabilize the residual charge erasing operation as compared with the case where the residual charge erasing is started from the unstable state of the circuit immediately after the power is turned off.

Further, according to the fifth display device of the present invention, the display device according to any one of the first to fourth embodiments of the present invention is provided with the storage means for storing the operation procedure after the power is turned off. The residual charge erasing operation can be smoothly performed according to the operation procedure stored in the means.

According to the sixth display device of the present invention,
In the first to fifth display devices of the present invention, the residual charge erasing circuit outputs to the power supply unit a power-recycle prohibition signal that prohibits power-on again when residual charge leaks after power-off. The power is turned on again while the residual charges are being erased, and it is possible to prevent malfunctions and the like caused by the charges being charged in the display panel.

Further, according to the seventh display device of the present invention, a display panel to which a high voltage is applied and which has a capacitive component is used as the display portion of any one of the first to sixth display devices of the present invention. Since a certain plasma display panel is used, it is suitable as an example of the display device of the present invention.

[0025]

Embodiments of the present invention will now be described with reference to the drawings.

(1) First Embodiment A display device according to the first embodiment of the present invention will be described below. As shown in FIG. 1A, this display device is a device including a display unit 12 having a PDP that displays a predetermined image and a power supply unit 11 that supplies a power supply voltage to the display unit 12.

As shown in FIG. 1A, the power supply unit 11 is a circuit that generates a low voltage Vcc of about 5V, a high voltage Vs of about 185V, and a ground potential GND from an AC voltage and supplies them to the display unit 12. . This is the connection terminals p11, p12, p1
3, p14, of which connection terminals p11, p1
3 and p14 are output terminals for the low voltage Vcc, the high voltage Vs, and the ground potential GND, respectively, and the connection terminal p12 is an input terminal for a feedback voltage Vr described later.

Further, the power supply section 11 is provided with a high voltage generation circuit 13 which outputs a high voltage Vs after receiving the feedback voltage Vr.

The display unit 12 is a device having a PDP (not shown) for displaying a predetermined image, and includes a PDP (not shown) and connection terminals q11, q12, q13, q14, among which connection terminals q11, q13. , Q14 are input terminals for the low voltage Vcc, the high voltage Vs, and the ground potential GND, respectively, and the connection terminal q12 is an output terminal for a feedback voltage Vr described later.

A low voltage Vcc of about 5V input from the connection terminal q11 is input to a control circuit (not shown), and a high voltage Vs of about 185V input from the connection terminal q13 is passed through an X driver and a Y driver (not shown). Are supplied to a PDP (not shown). Under the control of this control circuit, the X driver and the Y driver are driven, whereby a predetermined display is made on the PDP.

A feedback circuit FC is formed in the display unit 12 from the connection terminals q11 to q12, whereby the low voltage Vcc is used as the feedback voltage Vr and the connection terminal q1.
It is input to the connection terminal p12 via 2 and fed back to the power supply unit 11.

Further, the power supply unit 11 and the display unit 12 are connected to the connection terminals p11, p12, p13, p14 and the connection terminal q11.
Connections such as connectors are provided via q12, q13, and q14, respectively.

The operation of the above apparatus will be described below.

First, when the power is turned on, the low voltage Vcc and the ground potential G are supplied from the power source section 11 via the connection terminals p11 and p14.
ND is output respectively. High voltage V still at this point
s is not output.

The low voltage Vcc and the ground potential GND output from the connection terminals p11 and p14 are the connection terminal q1.
1, q14 are input to the display unit 12.

When the low voltage Vcc is input to the display unit 12, the low voltage is supplied to the connection terminal q12 via the feedback circuit FC.
Is output from the connection terminal p12 to the high voltage generation circuit 13 as the feedback voltage Vr.

The high voltage generation circuit 13 is a circuit having a comparator 13A, a delay circuit 13B and a high voltage output circuit 13C as shown in FIG. 1B, and the feedback voltage Vr is 0 in the initial state before the power is turned on. Therefore, the comparator 1
The output of 3A is at a high level (hereinafter referred to as "H").

As shown in FIG. 4A, when the low voltage Vcc is output and the feedback voltage Vr is fed back at almost the same time and input to the high voltage generation circuit 13, this is divided by the bleeder ratio of the resistors R1 and R2. , And is input to the inverting input (-) of the comparator 13A.

At this point, the high voltage Vs to be input to the non-inverting input (+) of the comparator 13A has not yet been output, so the output of the comparator 13A becomes low level (hereinafter referred to as "L"). When this "L" is input to the delay circuit 13B, it is input to the high voltage output circuit 13C after being delayed by a predetermined time T1 by the delay circuit 13B as shown in FIG. 4 (a). Thus, when "L" is input to the high voltage output circuit 13C, the high voltage Vs is output from the high voltage output circuit 13C.

The high voltage Vs thus output is input to the display section 12 from the connection terminal p13 via the connection terminal q13.

Through the above operation, after the feedback voltage Vr is input to the high voltage generation circuit 13, the high voltage generation circuit 13
The high voltage Vs is output from the input terminal and input to the display unit 12 via the connection terminals p13 and q13.

In the display device having the PDP as described above, the low voltage Vcc is input to the control circuit (not shown),
The high voltage Vs is input to the PDP via the X and Y drivers (not shown), but the low voltage Vcc is not input to the control circuit,
If a high voltage Vs of about 185V is input before the device is ready to start up, there is a problem such as damage to the X and Y drivers. Therefore, especially when the power is turned on, the low voltage Vcc is displayed. Although it is necessary to supply the high voltage Vs after supplying the high voltage Vs to the power supply unit, in the display device according to the present embodiment, the low voltage Vcc is used as the feedback voltage Vr for the display unit 12 in the power supply unit 1.
A feedback circuit FC for returning to 1 is provided, and the power supply unit 11 is provided with a high voltage generation circuit 13 that outputs a high voltage Vs to the display unit 12 after the feedback voltage Vr is input, so that a low voltage is provided. It is possible to surely output the high voltage Vs to the display unit 12 after Vcc is input to the display unit 12.

As a result, the display unit 12 does not have to include a delay circuit having a large element size, which is composed of a resistor and a capacitor, as in the conventional case, and is not inserted in the connection portion between the power supply unit 11 and the display unit 12.
Since the high voltage Vcc can be supplied after the low voltage Vcc has been input to, it is possible to reliably prevent malfunctions at power-on without increasing the device scale.

In the present embodiment, the high voltage output circuit 13 has a circuit configuration as shown in FIG. 1B, but the present invention is not limited to this, and as shown in FIG. Vr
It suffices if the output delay circuit 13D that outputs the high voltage Vs after delaying for a predetermined time from the time when the input is input is built in.

Further, in the present embodiment, as shown in FIG. 1, the voltage for feeding back the low power source Vcc to the power source section 11 is a feedback voltage Vr.
However, the present invention is not limited to this, and as shown in FIG. 2, even if the ground potential GND is fed back to the power supply unit 11 and the feedback voltage Vr is obtained, the same effect can be obtained.

(2) Second Embodiment A display device according to the second embodiment of the present invention will be described below with reference to the drawings. Note that the description of the items common to the first embodiment is omitted to avoid duplication.

As shown in FIG. 3A, the display device according to the present embodiment comprises a display section 32 having a PDP for displaying a predetermined image and a power supply section 31 for supplying a power supply voltage to the display section 32. Is.

As shown in FIG. 3A, the power supply unit 31 is a circuit that generates a low voltage Vcc of about 5V, a high voltage Vs of about 185V, and a ground potential GND from an AC voltage and supplies them to the display unit 32. . This is the connection terminals p31, p32, p3
3, p34, of which connection terminals p31, p3
Low voltage Vcc, high voltage Vs, and ground potential GND are output from 3 and p34, respectively. The connection terminal p32 is an input terminal for a recognition signal Von described later.

The display unit 32 is a device having a PDP (not shown) for displaying a predetermined image, and includes a PDP (not shown) and connection terminals q31, q32, q33, q34, among which connection terminals q31, q33. , Q34 are input terminals for the low voltage Vcc, the high voltage Vs, and the ground potential GND, respectively, and the connection terminal q32 is an output terminal for a recognition signal Von described later.

The display unit 32 also includes a recognition signal generation circuit 33 that outputs the recognition signal Von to the power supply unit 31 after the low power supply Vcc is input.

A low voltage Vcc of about 5V input from the connection terminal q31 is input to a control circuit (not shown), and a high voltage Vs of about 185V input from the connection terminal q33 is passed through an X driver and a Y driver (not shown). Are supplied to the PDP. Under the control of this control circuit, the X driver and the Y driver are driven, whereby a predetermined display is made on the PDP.

Further, the power supply section 31 and the display section 32 have connection terminals p31, p32, p33 and p34 and a connection terminal q31.
Connections such as connectors are provided via q32, q33, and q34, respectively.

The operation of the above apparatus will be described below.

First, when the power is turned on, the low voltage Vcc and the ground potential G are supplied from the power source section 31 via the connection terminals p31 and p34.
ND is output respectively. At this point, the power supply unit 3 is still
The high voltage Vs is not output from 1.

The low voltage Vcc and the ground potential GND output from the connection terminals p31 and p34 are the connection terminal q3.
1, q34 are input to the display unit 32.

When the low voltage Vcc is input to the display section 32, the low voltage Vcc is also input to the recognition signal generating circuit 33 connected to the connection terminal q31.

The recognition signal generation circuit 33 is a circuit composed of a comparator 33A and a delay circuit 33B as shown in FIG. 3 (b).

When a low voltage Vcc is input to this circuit,
The output of the comparator 33A becomes "H", which is input to the delay circuit 33B and delayed by the delay circuit 33B for a certain period of time to generate the recognition signal Von.

This recognition signal Von is the recognition signal generation circuit 3
3 is output to the connection terminal q32 and is input to the power supply unit 31 via the connection terminal p32. Only when this is input, the high voltage Vs is output from the connection terminal p33 of the power supply unit 31, and the display unit is output via the connection terminal q33. Will be input to 32.

A timing chart of the operation during this period is shown in FIG.
It shows in (b). As shown in FIG. 4B, the low voltage V
After the cc rises and is input to the display unit 32, the recognition signal Von rises and is output to the power supply unit after being delayed for a predetermined time T3, and at the same time as the rise, the high voltage Vs rises and is output to the display unit 32. You can see that it is done.

As described above, in the display device according to the present embodiment, the recognition signal generation circuit 3 that outputs the recognition signal Von to the power supply unit 31 after the low voltage Vcc is input into the display unit 32.
3 is provided, and the power supply unit 31 uses the recognition signal Von.
Since the high voltage Vs is output to the display unit 32 after is input, it is possible to reliably output the high voltage Vs to the display unit 12 after the low voltage Vcc is input to the display unit 12.

As a result, similarly to the first embodiment,
It is possible to supply the high voltage Vcc after the low voltage Vcc is input to the display unit 32 without inserting a delay circuit having a large scale such as a resistor and a capacitor into the connection unit as in the conventional case. It is possible to reliably prevent malfunctions when the power is turned on without increasing the number.

(3) Third Embodiment A display device according to the third embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 5, this display device is a device having a display section 42 having a PDP panel PP for displaying a predetermined image and a power supply section 41 supplying a power supply voltage to the display section 42.

The power supply section 41 is a circuit for outputting to the display section 42 a low voltage Vcc of about 5V and a high voltage Vs of about 185V which are power supply voltages for driving.

The display section 42 includes an X driver XD, a Y driver YD, a power-off detection circuit 43, a residual charge erasing circuit 44,
It has a control circuit 45 and a PDP panel PP, and has a low voltage Vc.
This is a device for performing a predetermined display on the PDP panel using c and the high voltage Vs as power supply voltages.

The X driver XD and the Y driver YD are circuits that apply the high voltage Vs supplied from the power supply section 41 to the X electrodes X and Y electrodes Y constituting the PDP panel PP as a sustain voltage.

As shown in FIG. 5, the power-off detection circuit 43 includes an auxiliary power source 43A composed of a battery, a CPU 43B, and a ROM.
46 having a high voltage Vs and a low voltage Vcc from the power supply unit 41.
Is a circuit for detecting a time point when the power supply is stopped (hereinafter referred to as power-off time) and transmitting a disconnection recognition signal CS as a detection result to the control circuit 45.

The auxiliary power supply 43A is a circuit for supplying the power supply voltage Vcc2 of the power supply cutoff detection circuit 43 and the control circuit 45 after the power supply is cut off. The CPU 43B is a circuit device that controls the operation of the power-off detection circuit 43, and the ROM 46 is an example of a storage unit, and has a table 1 and a table 2 in which a sequence indicating an operation procedure of the entire display unit 42 is stored. . Table 1 stores a first sequence showing an operation procedure at the time of performing a normal display after power is turned on, and Table 2 stores a second sequence showing an operation procedure after turning off the power.

The residual charge erasing circuit 44 is a switching circuit connected to the X electrode X, and is turned on when the leak signal LS output from the control circuit 45 when the power is turned off is input, and remains on the PDP panel PP. This is a circuit for erasing the electric charges that are generated.

The control circuit 45 is a circuit for controlling all operations related to the display of the display section 42. When the power is turned off, the leak signal LS is output to the residual charge erasing circuit 44. Further, this power supply voltage is the low voltage Vcc in the normal operation.

The operation of the above apparatus will be described below.
First, the power is turned on, and the low voltage Vcc and the high voltage Vs are applied from the power supply unit 41 to the display unit 42. At this time, the residual charge erasing circuit 44 is off.

The low voltage Vcc is applied to the control circuit 45,
The control circuit 45 operates using this low voltage Vcc as a power supply voltage. The low voltage Vcc is also input to the power-off detection circuit 43 at the same time, and specifically, the diode D4
1 is input to the CPU 43B. At this time, the power supply cutoff detection circuit 43 operates with the low voltage Vcc as the power supply voltage.

The high voltage Vs is supplied to the X driver XD and the Y driver YD as their power supply voltage, and PD
The high voltage Vs is applied to the X electrode X and the Y electrode Y of the P panel PP.

Then, under the control of the control circuit 45, the X driver XD and the Y driver YD apply the sustain voltage to the PDP panel PP, and a predetermined image is displayed on the PDP panel PP.

Up to this point, the device described above is
It is driven in the first sequence stored in the table 1 built in the ROM 46.

That is, the potential of the X electrode X rises / falls in synchronization with the rise of switching signals Xup and Xdown when the voltage is supplied / not supplied to the X electrode X, respectively. The potential of the Y electrode Y rises / falls in synchronization with the rise of Yup and Ydown, which are switching signals when the voltage is supplied / not supplied to the Y electrode Y, respectively.

After that, the operation in the case where the power supply is cut off and the low voltage Vcc and the high voltage Vs are not supplied from the power supply unit 41 will be described below. PDP when power is off
The charges accumulated by the application of the high voltage Vs still remain in the panel PP.

Since the low voltage Vcc is no longer supplied from the power supply unit, the auxiliary power supply voltage Vcc2 (Vcc2 <Vcc, in this case about 3V) output from the auxiliary power supply 43A is supplied to the CPU 43B and the control circuit 45 instead. It becomes a voltage.

The CPU 43B recognizes that the power supply is cut off by changing the power supply voltage from the low voltage Vcc to the auxiliary power supply voltage Vcc2, and outputs the power supply cutoff recognition signal CS to the control circuit 45. As a result, the control circuit 45 switches the control sequence from the first sequence in the table 1 built into the ROM 46 to the second sequence in the table 2 as shown in FIG. 6, and at the same time, outputs the leak signal LS to the residual charge erasing circuit 44. Output.

When the leak signal LS is output to the residual charge erasing circuit 44, the switching circuit is turned on, the potential of the X electrode X of the PDP panel PP is forcibly lowered to the ground potential GND, and remains on the PDP panel PP. The electric charges that have been applied fall to the ground potential GND, and the residual electric charges are erased (FIG. 6).

During this time, the CPU 43B and the power supply unit 4 simultaneously.
A power-on prohibition signal Vchk as shown in FIG. 6 is input to 1 and the power is not turned on again during this period.

As described above, according to the display device of this embodiment, after the power is turned off, it is detected and the electric charge remaining between the PDP panels PP is erased. It is possible to prevent the malfunction of the device due to the uncertain potential of the X electrode and the circuit breakdown.

In the residual charge erasing period, the power re-inhibit signal Vchk is output to the power supply section 41, and even if the power is accidentally turned on, the power is not re-energized during this period. It is possible to prevent malfunctions and the like that occur when the power is turned on again during erasing.

In this embodiment, the built-in battery of about 3 V is used as the auxiliary power source 43A, but the present invention is not limited to this, and the circuit in which the high voltage Vs falls gently as shown in FIG. When a constant is set, this high voltage Vs is divided by the bleeder ratio of resistors connected in series to generate a DC voltage of about 3V, and the same effect can be obtained by replacing the auxiliary power source 43A.

(4) Fourth Embodiment A display device according to the fourth embodiment of the present invention will be described below with reference to the drawings. Descriptions of matters common to the third embodiment will be omitted to avoid duplication.

As shown in FIG. 8, this display device has a display section 52 having a PDP panel PP for displaying a predetermined image.
And a power supply unit 51 that supplies a power supply voltage thereto.

The power supply section 51 is a circuit for outputting to the display section 52 a low voltage Vcc and a high voltage Vs which are power supply voltages for driving.

The display section 52 includes an X driver XD, a Y driver YD, a power-off detection circuit 53, a residual charge erasing circuit 54,
It has a control circuit 55 and a PDP panel PP, and has a low voltage Vc.
This is a device for performing a predetermined display on the PDP panel using c and the high voltage Vs as power supply voltages.

The power-off detection circuit 53 uses the auxiliary power source 53A,
It has a CPU 53B and a ROM 56. Since the circuit components up to the above are almost the same as those in the third embodiment, detailed description thereof will be omitted.

The feature of the circuit of this embodiment that is different from that of the third embodiment is that the structure of the residual charge erasing circuit 54 and the operation when the ROM 56 storing the control sequence performs a normal display operation after the power is turned on. The two points are that only the first sequence indicating the procedure is stored.

The residual charge erasing circuit 54 is provided at the final stage of the X driver XD as shown in FIG. 8 and is a MOS transistor T1 to T serving as a switching element as shown in FIG.
4 and turns on / off based on the high voltage Vs, the leak signal LS, the disconnection recognition signal Cdown, and the auxiliary power supply voltage Vcc2 (low voltage Vcc during normal operation), and P when power off.
This is a circuit for erasing the residual charges of the DP panel PP.

The operation of the above apparatus will be described below.
First, the power is turned on, and the low voltage Vcc and the high voltage Vs are applied from the power supply unit 51 to the display unit 52.

The low voltage Vcc is applied to the control circuit 55, and the control circuit 55 is driven by using the low voltage Vcc as a power supply voltage. The low voltage Vcc is also input to the power-off detection circuit 53 at the same time, and specifically, the diode D
It is input to the CPU 53B via 51. At this time, the power supply cutoff detection circuit 53 is driven with the low voltage Vcc as the power supply voltage.

The high voltage Vs is supplied to the X driver XD and the Y driver YD as their power supply voltage, and PD
The high voltage Vs is applied to the X electrode X and the Y electrode Y of the P panel PP.

Then, under the control of the control circuit 55, the X driver XD and the Y driver YD apply / non-apply the sustain voltage to the PDP panel PP, and a predetermined image is displayed on the PDP panel PP.

At this time, the residual charge erasing circuit 54 has a low voltage Vcc, a disconnection recognition signal Cdown of "L", and a high voltage Vs.
And the leak signal LS of "H" are input, the MOS transistor T1 is ON, and the MOS transistor T2 is OF.
F, the MOS transistor T3 is on, and the MOS transistor T4 is off. Therefore, the high voltage Vs output from the X driver XD is directly applied to the X electrode X shown in FIG. At this time, the control circuit is driven in the sequence as shown in FIG. 10, that is, the first sequence stored in the table 1 built in the ROM 56.

After that, when the power supply is cut off and the low voltage Vcc and the high voltage Vs are no longer supplied from the power supply unit 51, when the power supply is cut off, the charges accumulated by the application of the high voltage Vs still remain in the PDP panel PP. ing.

Since the low voltage Vcc is not supplied from the power supply unit 51, the auxiliary power supply voltage Vcc2 (Vcc2 <Vcc) output from the auxiliary power supply 53A is replaced by CP.
It becomes the power supply voltage for U53B and the control circuit 55.

The CPU 53B recognizes that the power supply is cut off by changing the power supply voltage from the low voltage Vcc to the auxiliary power supply voltage Vcc2, and outputs the cutoff recognition signal Cdown to the residual charge erasing circuit 54. At the same time, the control circuit 55 also recognizes that the power supply is cut off because the power supply voltage has changed to the auxiliary power supply voltage Vcc2, and outputs the leak signal LS of "L" to the residual charge erase circuit 54.

At this time, the residual charge erasing circuit 54 has the low voltage Vcc, the disconnection recognition signal Cdown of "H", and the high voltage Vs.
And the leak signal LS of "L" are input, the MOS transistor T1 is OFF, and the MOS transistor T2 is O.
Since N, the MOS transistor T3 is OFF, and the MOS transistor T4 is ON, the potential of the X electrode X drops to the ground potential GND, and the residual charge remaining in the PDP panel PP is erased.

As described above, according to the display device of the present embodiment, as in the third embodiment, after the power is turned off, it is detected and the electric charge remaining between the PDP panels PP is erased. Therefore, it is possible to prevent the malfunction of the device and the circuit breakdown due to the undefined potential of the X electrode, which has been conventionally caused by the residual charge.

[0102]

As described above, according to the first display device of the present invention, it is provided with the power supply unit for supplying the power supply voltage and the display panel having the capacitive load, and the display panel is predetermined based on the power supply voltage. A display device having a display section for displaying, and a detection circuit for detecting the power-off when the power is turned off,
It has a residual charge erasing circuit for erasing the electric charge remaining in the display panel after the power-off is detected.

Therefore, even if electric charge remains on the display panel having a capacitive load when the power is turned off, it is possible to prevent the malfunction of the circuit in the display section and the circuit destruction which have been conventionally caused by the residual electric charge. become.

Further, according to the second display device of the present invention,
Since the built-in battery is used as a power supply voltage for driving the residual charge erasing circuit in the first display device of the present invention, a stable power supply voltage can be supplied to the residual charge erasing circuit even after the power is turned off, and the residual charge erasing can be performed. It is possible to operate the circuit stably and surely erase the residual charges.

According to the third display device of the present invention,
The power supply voltage in the first display device of the present invention is composed of two types of voltage, a low voltage and a high voltage, and the high voltage is used as the power supply voltage for driving the residual charge erasing circuit. In the case of a circuit that gradually drops, even if this high voltage is used as the power supply voltage, the residual charge erasing circuit can be stably operated as in the second display device of the present invention.

Further, according to the fourth display device of the present invention, in the residual charge erasing circuit according to any one of the first to third embodiments of the present invention, the display panel is provided after a lapse of a certain time from the time when the power-off is detected. Since the electric charge remaining in is erased,
It becomes possible to stabilize the residual charge erasing operation as compared with the case where the residual charge erasing is started from the unstable state of the circuit immediately after the power is turned off.

Further, according to the fifth display device of the present invention, any one of the first to fourth display devices of the present invention is provided with the storage means for storing the operation procedure after the power is turned off. The residual charge erasing operation can be smoothly performed according to the operation procedure stored in the means.

According to the sixth display device of the present invention,
In the display device according to any one of the first to fifth aspects of the present invention,
The residual charge erasing circuit outputs a power-on prohibition signal to the power supply section that prohibits the power to be turned on again when the residual charge leaks after the power is turned off. As a result, it is possible to prevent malfunctions and the like caused by the charge in the display panel.

Further, according to the seventh display device of the present invention, a display panel to which a high voltage is applied and which has a capacitive component is used as a display portion of any one of the first to sixth display devices of the present invention. Since a certain plasma display panel is used, it is suitable as an example of the display device of the present invention.

[Brief description of drawings]

FIG. 1 is a first diagram illustrating a display device according to a first embodiment of the present invention.

FIG. 2 is a second diagram illustrating the display device according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a display device according to a second embodiment of the present invention.

FIG. 4 is a timing chart explaining the operation of the display device according to the first and second embodiments of the present invention.

FIG. 5 is a circuit configuration diagram of a display device according to a third embodiment of the present invention.

FIG. 6 is a first timing chart explaining the operation of the display device according to the third embodiment of the present invention.

FIG. 7 is a second timing chart explaining the operation of the display device according to the third embodiment of the present invention.

FIG. 8 is a circuit configuration diagram illustrating a display device according to a fourth embodiment of the present invention.

FIG. 9 is a circuit configuration diagram illustrating an essential part of a display device according to a fourth example of the present invention.

FIG. 10 is a timing chart explaining the operation of the display device according to the fourth example of the present invention.

FIG. 11 is a diagram illustrating a first conventional display device.

FIG. 12 is a circuit configuration diagram of a second conventional display device.

FIG. 13 is a diagram illustrating a problem of the conventional second display device.

[Explanation of symbols]

11 power supply 12 Display 13 High voltage generation circuit 13A comparator 13B delay circuit 13C high voltage output circuit 13D output delay circuit 21 power supply 22 Display 23 High voltage generation circuit 31 power supply 32 display 33 Recognition signal generation circuit 33A comparator 33B delay circuit 41 power supply 42 Display 43 Current disconnection detection circuit 43A auxiliary power supply 43B CPU 44 Residual charge erase circuit 45 Control circuit 46 ROM X X electrode YY electrode XD X driver YD Y driver 51 power supply 52 display 53 Current disconnection detection circuit 53A auxiliary power supply 53B CPU 54 Residual charge erase circuit 55 Control circuit 56 ROM Vcc low voltage Vs high voltage GND ground potential Vr feedback voltage Von recognition signal LS leak signal CS disconnection recognition signal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takashi Fujisaki             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited (72) Inventor Hideo Kimura             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited (72) Inventor Tomokatsu Kishi             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited F-term (reference) 5C080 AA05 BB05 DD09 DD19 FF03                       FF12 GG12 HH02 HH07 JJ02                       JJ04

Claims (7)

[Claims] 1. A display device comprising: a power supply unit for supplying a power supply voltage; and a display unit, which includes a display panel and displays a predetermined display on the display panel based on the power supply voltage. A display device comprising: a detection circuit for detecting power-off; and a residual charge erasing circuit for erasing charges remaining on the display panel after the power-off is detected. 2. The display device according to claim 1, wherein a built-in battery is used as a power supply voltage for driving the residual charge erasing circuit. 3. The display device according to claim 1, wherein the power supply voltage is composed of two types of voltage, a low voltage and a high voltage, and the high voltage is used as a power supply voltage for driving the residual charge erasing circuit. . 4. The residual charge erasing circuit includes a delay circuit for erasing the electric charge remaining in the display panel after a lapse of a certain time from the time when the power-off is detected. The display device according to claim 3. 5. The display device according to claim 1, further comprising a storage unit that stores an operation procedure after the power is turned off. 6. The residual charge erasing circuit outputs, to the power supply unit, a power re-inhibit signal that prohibits the power to be turned on again when the residual charge is erased after the power is turned off. The display device according to claim 5. 7. The display device according to claim 1, wherein the display unit is a plasma display panel.