KR100536242B1 - Plasma display device and driving method thereof - Google Patents

Abstract

The present invention relates to a plasma display device and a driving method thereof. According to the present invention, the plasma display device comprises a power-on reset circuit as a female processor, detects a configuration completion signal of an FPGA, and varies the reset signal in software according to the signal. This prevents burnout of the circuit due to reset time mismatch.

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a plasma display device including a plasma display panel (PDP).

Recently, flat display devices such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display have been actively developed.

Among the flat panel display devices, the plasma display device has advantages of higher luminance and luminous efficiency and a wider viewing angle than other flat panel display devices. Accordingly, the plasma display panel is in the spotlight as a display device to replace a conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

Plasma display devices are flat display devices that display characters or images using plasma generated by gas discharge, and dozens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display device is classified into a direct current type and an alternating current type according to the shape of a driving voltage waveform to be applied and the structure of a discharge cell.

In the DC plasma display device, the electrode is exposed without the discharge space insulated, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for limiting the current must be made. On the other hand, in the AC plasma display device, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the electrode is protected from the impact of ions during discharge.

In order to satisfy the power factor, the PDP power supply is provided with a power factor correction (PFC) circuit that compensates for power factor by receiving power from an input AC power source and provides stable power to the PDP. do.

That is, when the AC rated voltage is input to the PDP power supply and the basic power is applied to each device, a signal for starting the PFC, that is, a signal for turning on a relay in the PDP power supply, is output from the device performing the image signal processing. The output is input to the PDP power supply.

Then, the PDP power supply outputs the power for the image signal, outputs the power for the driving driver switch, and outputs the driving power for driving the PDP so that the PDP can perform a normal operation.

On the other hand, a boot storage capacitor is respectively connected to a power supply terminal for supplying a voltage to the driving circuit. The boot storage capacitor charges the boot storage capacitor in consideration of the pulsation of the power input from the power supply unit. Even if unstable, it plays a role to supply stable power to the driving circuit.

Also included in the logic circuit is a power-on reset circuit. When power is applied to the logic circuit, a configuration time of a field programmable gate array (FPGA) is required.When the configuration is completed, the FPGA reads data from memory to generate driving waveforms and data. PDP works. At this time, in order to prevent the FPGA from malfunctioning during the configuration time, a power on reset (n-reset) signal is applied to the FPGA. When the configuration is completed, the power on reset signal is cleared to allow the FPGA to operate normally.

Figure 1 is a timing diagram of such a conventional FPGA operation.

As shown in FIG. 1, when the 3.3V power supply for operating the FPGA is turned on, the power-on reset signal is turned off and configuration starts to proceed with the gate array of the FPGA, and a signal indicating completion when the configuration is completed. (Conf-Done) is displayed. After a predetermined time according to the RC time constant of the power-on reset circuit, the power-on reset signal is turned on again and the FPGA starts normal operation.

However, if the logic program is executed without the power-on reset circuit or the data is not sufficiently written in the FPGA, the circuit may malfunction. Therefore, the time when the boot storage capacitor is charged and the time when the logic data is output There is a fear that the driving circuit may be burned out when the power is turned on because there is no match. Therefore, it is necessary to apply the correct power-on reset signal according to the configuration data size of the FPGA used for each logic circuit.

On the other hand, the conventional power-on reset circuit is composed of a resistor (R) and a capacitor (C), the RC time constant adjusted the application time (reset time) of the power-on reset signal. Therefore, in order to adjust the reset time, it is not only cumbersome to change the values of the resistors (R) and capacitors (C). In addition, since the power-on reset circuit is hardware-configured, it is almost impossible to adjust the accurate reset time for each FPGA. It was. Therefore, in the case of a configuration that requires a large amount of data, the reset time may elapse before the configuration is completed, causing abnormal operation of the FPGA or damage to the driver board. Unnecessary time is wasted.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device including a power-on reset circuit capable of adjusting the reset time in software and a driving method thereof.

According to an aspect of the present invention, a plasma display device includes: a power supply unit supplying power; A driver to drive the plasma display panel using the voltage and current supplied from the power source; A logic unit including a memory in which data for driving the plasma display panel is stored, and a field programmable gate array (FPGA) which downloads data stored in the memory and outputs a driving waveform according to the data to the driver; And a panel unit which displays the output image data.

The logic unit,

A configuration completion signal output from the FPGA is detected and a signal for operating the FPGA after a predetermined time is output to the FPGA.

The logic unit,

A configuration detector for detecting the configuration completion signal from the FPGA; A reset time, which is a time required to initialize the FPGA, is stored, and an internal timer is operated during the preset reset time according to an output signal of the configuration detection unit, and the reset time has elapsed to operate the internal timer. The stop time further comprises a reset time control unit for outputting a reset signal for operating the FPGA to the FPGA.

In the method of driving a plasma display device according to an aspect of the present invention, a plasma display panel is driven by using a power supply unit for supplying power, a voltage and a current supplied from the power supply unit, and are connected to each power supply terminal to supply stable power to a circuit. A drive unit including a plurality of boot storage capacitors, a memory storing data for driving the plasma display panel, and an FPGA configured to download data stored in the memory and output driving waveforms according to the data to the driving unit; A method of driving a plasma display device comprising a logic unit including a gate array and a panel unit configured to display the output image data.

a) after the power is applied to the logic unit from the power supply unit, the FPGA performing configuration and outputting a configuration completion signal; And b) the logic unit detects the configuration completion signal and outputs a signal for operating the FPGA to the FPGA after a predetermined time elapses.

The predetermined time is a time reset time required to initialize the FPGA,

B),

Operating, by the logic unit, an internal timer for a preset reset time according to an output signal of the configuration detection unit; And outputting a reset signal for operating the FPGA to the FPGA when the reset timer elapses and the operation of the internal timer stops.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

2 is a detailed internal configuration diagram of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the plasma display device 100 according to an exemplary embodiment of the present invention includes a power supply unit 100, a driving unit 200, an image unit 300, a logic unit 400, and a panel unit 500. do. The logic unit 400 includes an FPGA 410 and a reset time controller 420, and the driver 400 includes a Y driver 220 and a sustain electrode (X electrode) for generating a pulse applied to the scan electrode (Y electrode). X driver 210 to generate a pulse applied to the () and the address driver 230 to generate a pulse applied to the address electrode.

In detail, first, the power supply unit 100 supplies a voltage and a current having a predetermined size to each component such as the driving unit 200, the imaging unit 300, the logic unit 400, and the panel unit 500, and the driving unit 200. ) Causes the plasma display device to be driven using the voltage and current supplied from the power supply unit 100.

The image unit 300 outputs image data and a control signal according to a signal input from the outside, and the logic unit 400 outputs image data including a character and an image according to the output control signal, and the panel unit 500. ) Restores the output image data.

In addition, the reset time controller 420 according to the embodiment of the present invention uses a arm processor or a microcontroller operating on a standby power source to reset the power-on reset signal according to the configuration time of the FPGA. And a configuration detecting unit 421 and a reset time adjusting unit 422.

The configuration detector 421 detects the signal Conf_Done output when the configuration is completed in the FPGA 410, and the reset time controller 422 according to the signal output from the configuration detector 421. An internal timer (not shown) is operated to adjust the reset time.

Next, the configuration and operation of the reset time controller 420 according to the embodiment of the present invention will be described in detail with reference to FIG. 3.

3 illustrates an FPGA operation timing diagram according to an embodiment of the present invention.

As shown in FIG. 3, when AC power is input to the power supply unit, the reset time controller 420 which is an arm processor starts to operate. In addition, the power-on reset signal is converted from the high level to the low level, and the configuration signal is turned on to proceed with the gate array in the FPGA 410.

Then, when the gate array is completed and the Conf-Done signal is generated, the configuration detector 421 detects this signal and outputs the signal to the reset time controller 422. The reset time adjusting unit 422 then operates the internal timer. The internal timer stops the operation when the reset time set in software according to the FPGA 410 used in each logic unit elapses. When the timer stops operating, the reset time controller 422 converts the power-on reset signal from the low level to the high level and outputs the converted power to the FPGA 410. The FPGA 410 then starts to operate normally.

As described above, according to the present invention, the reset time can be set differently according to the FPGA by software using the arm processor. Since the configuration completion signal is detected and a power-on reset signal is output, the configuration data size of the FPGA The reset signal can be applied regardless of the change. This prevents burnout of the circuit due to reset time mismatch.

Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited thereto, and various other changes and modifications are possible.

As described above, according to the present invention, the reset signal may be changed regardless of the change in the configuration data size of the FPGA, thereby preventing the circuit from being burned out due to the reset time mismatch.

1 is an FPGA driving timing diagram according to the prior art.

2 is a detailed internal configuration diagram of a plasma display device according to an exemplary embodiment of the present invention.

3 is an FPGA driving timing diagram according to an embodiment of the present invention.

Claims (4)

A power supply unit supplying power; A driver to drive the plasma display panel using the voltage and current supplied from the power source; A logic unit including a memory in which data for driving the plasma display panel is stored, and a field programmable gate array (FPGA) which downloads data stored in the memory and outputs a driving waveform according to the data to the driver; And It includes a panel unit for displaying the output image data, The logic unit, Detecting a configuration completion signal output from the FPGA and outputting a signal for operating the FPGA to the FPGA after a predetermined time elapses. Plasma display device. The method of claim 1, The logic unit, A configuration detector for detecting the configuration completion signal from the FPGA; A reset time, which is a time required to initialize the FPGA, is stored, and an internal timer is operated during the preset reset time according to an output signal of the configuration detection unit, and the reset time has elapsed to operate the internal timer. Reset time control unit for outputting a reset signal for operating the FPGA to the FPGA when stopped Plasma display device further comprising. A power supply unit for supplying power, a driving unit for driving the plasma display panel by using the voltage and current supplied from the power supply unit, a memory in which data for driving the plasma display panel is stored, and data stored in the memory by downloading the data A method of driving a plasma display device comprising a logic unit including a field programmable gate array (FPGA) for outputting a driving waveform to the driving unit and a panel unit displaying the output image data, a) after the power is applied to the logic unit from the power supply unit, the FPGA performing configuration and outputting a configuration completion signal; And b) the logic unit detects the configuration completion signal and outputs a signal for operating the FPGA to the FPGA after a predetermined time elapses; Method of driving a plasma display device comprising a. The method of claim 3, The predetermined time is a time reset time required to initialize the FPGA, B), Operating, by the logic unit, an internal timer for a preset reset time according to an output signal of the configuration detection unit; And Outputting a reset signal for operating the FPGA to the FPGA when the reset timer elapses and the operation of the internal timer stops; Method of driving a plasma display device comprising a.