KR100563051B1 - Resetting apparatus of volatile integrated circuit in plasma display panel - Google Patents

Abstract

The present invention relates to a volatile integrated circuit initialization device of a plasma display panel. The volatile integrated circuit initialization apparatus of the plasma display panel according to the present invention generates an initialization signal of a volatile integrated circuit mounted on the plasma display panel driver in each of power-on, voltage fluctuations of power during operation, and power-off. A power supply voltage variation detection unit; A power signal delay unit; Initialization time adjusting unit; And an initialization signal output unit. The power supply voltage change detection unit detects a voltage change of the power supply and generates a voltage change signal. The power signal delay unit generates a delay power signal by delaying the power signal. The initialization time adjusting unit receives the voltage change signal and the delay power signal and generates an initialization time adjustment signal having a predetermined time width. The initialization signal output unit receives the voltage change signal and the initialization time adjustment signal to generate the initialization signal, and outputs the initialization signal to the initialization signal input terminal of the volatile integrated circuit. According to the present invention, the plasma display panel can be stably driven by initializing a volatile integrated circuit such as an FPGA in each of power-on, power-on voltage fluctuations, and power-off.

Description

Resetting apparatus of volatile integrated circuit in plasma display panel

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 is a cross-sectional view illustrating a configuration of a unit cell of the panel of FIG. 1.

3 is a block diagram illustrating a conventional driving device of the plasma display panel of FIG. 1.

4 is a waveform diagram schematically illustrating an example of voltage variation of a power source applied to the driving device of FIG. 3.

FIG. 5 is a waveform diagram schematically illustrating an example of a logic control signal and a driving signal in a third section of FIG. 4.

6 is a block diagram schematically illustrating a volatile integrated circuit initialization device of a plasma display panel according to an embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating the volatile integrated circuit initialization device of FIG. 6 in more detail.

FIG. 8 is a waveform diagram schematically illustrating an initialization signal by the volatile integrated circuit initialization device of FIG. 6.

9 is a waveform diagram at each terminal of the volatile integrated circuit initialization device according to the present invention when the power is turned on.

10 is a waveform diagram at each terminal of the volatile integrated circuit initialization device according to the present invention when the voltage suddenly changes.

11 is a waveform diagram at each terminal of the volatile integrated circuit initialization device according to the present invention when the power is turned off.

<Explanation of symbols for the main parts of the drawings>

31: power supply voltage detection unit, 32: power signal delay unit,

33: initialization time adjusting unit, 34: initialization signal output unit,

35: reset unit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a volatile integrated circuit initialization device of a plasma display panel. More particularly, the initialization time required for initialization of a volatile integrated circuit mounted on a driving device of a plasma display panel can be secured and the power supply can be changed during operation. The present invention relates to a volatile integrated circuit initialization device for a plasma display panel.

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 is a cross-sectional view illustrating a configuration of a unit cell of the panel of FIG. 1.

Referring to the drawings, between the front and rear glass substrates 10 and 13 of the conventional surface discharge plasma display panel 1, the address electrode lines A _R1 , A _G1 , ..., A _Gm , A _Bm ), Dielectric layers 11 and 15, Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), fluorescent layer 16, partition wall 17 ) And a magnesium monoxide (MgO) layer 12 as a protective layer.

The address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is entirely applied in front of the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . These partitions 17 function to partition the discharge area of each discharge cell and to prevent optical cross talk between each discharge cell. The fluorescent layer 16 is formed between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) are the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _Bm ) is formed in a predetermined pattern on the back of the front glass substrate 10 to be orthogonal to each other. Each intersection sets a corresponding discharge cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line and conductivity of a transparent conductive material such as indium tin oxide (ITO), etc. The metal electrode lines for increasing the coupling are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

As a driving method of the plasma display panel 1 having the structure described above, an address-display separation driving method which is mainly used is disclosed in US Pat.

3 is a block diagram illustrating a conventional driving device of the plasma display panel of FIG. 1.

A typical driving device 2 of the plasma display panel 1 includes an image processor 26, a logic controller 22, an address driver 23, an X driver 24, and a Y driver 25. The image processing unit 26 converts an external analog image signal into a digital signal, for example, an internal image signal, for example, 8-bit red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 22 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 26.

At this time, the driver such as the address driver 23, the X driver 24, and the Y driver 25 receives input from the drive control signals S _A , S _Y , and S _X , and generates respective drive signals. The generated driving signal is applied to the respective electrode lines.

That is, the address driver 23 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 22 to generate a display data signal, and generates the displayed display. The data signal is applied to the address electrode lines. The X driver 24 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the logic controller 22 and applies the X driving control signal S _X to the X electrode lines. The Y driver 25 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the logic controller 22 and applies the Y driving control signal S _Y to the Y electrode lines. In particular, an integrated circuit such as a field programmable gate array (FPGA) may be mounted in a driving device that performs the above functions. Such an integrated circuit is a volatile device and requires initialization for normal operation.

4 is a waveform diagram schematically illustrating an example of voltage variation of a power source applied to the driving device of FIG. 3. FIG. 5 is a waveform diagram schematically illustrating an example of a logic control signal and a driving signal in section III of FIG. 4.

Referring to the drawings, the voltage fluctuation of the power applied to the driving device of the plasma display panel may be changed when the power is turned on (first section I), or when the voltage of the power suddenly changes during normal operation (second). Section, II), and when the power is turned off (third section, III).

When the power is turned on (first section), the voltage Vcc of the power source is changed from the reference level (eg 0V) to the normal level (eg 3.3V), and is driven from the operating level (eg 2.9V). The device will start operating normally. In addition, when the voltage of the power supply suddenly fluctuates during the normal operation (second section), in particular, it is a section that falls below the operating level from the normal level and rises above the operating level to return to the normal level. In addition, when the power is turned off (third section), the power is changed from the normal level to the reference level.

In each of the first, second, and third sections, the integrated circuits used in the driving apparatus need to be initialized in order for the driving apparatus to operate normally. In particular, recently, Field Programmable Gate Array (FPGA) may be used for electronic equipment such as plasma display panels. As the internal circuit arrangement becomes complicated and the capacity increases, sufficient initialization time is required for normal operation. In addition, in case of sudden voltage fluctuations during operation as in the case of the second section, appropriate measures are necessary for the normal operation of the system.

In addition, as shown in FIG. 5, the power supply is turned off to cause a problem in the third section in which the voltage level drops to the reference level. That is, when the power supply falls below the operating level, the logic control signal does not generate a signal below the power supply level, but the drive signal level continues to fall as the voltage level of the power supply falls even below the power supply level. There is a problem that can cause an abnormal display on the panel or cause an abnormal operation on the system.

U. S. Patent No. 5,180, 926, Power-on reset architecture, discloses a circuit for generating an initialization signal for active elements of an integrated circuit at power-on. The above patent does not solve the problem as described above. The description of the details thereof will be omitted, and the contents thereof will be included in the present specification.

The present invention is to solve the above problems, it is possible to secure the initialization time required for the initialization of the volatile integrated circuit mounted on the driving device of the plasma display panel, the volatile integration of the plasma display panel that can cope with power fluctuations during operation An object of the present invention is to provide a circuit initialization device.

The volatile integrated circuit initiation apparatus of the plasma display panel according to the present invention for achieving the above object is a volatile device mounted on the plasma display panel driving apparatus in each case of power-on, voltage fluctuations in power, and power-off. Generating an initialization signal of the integrated circuit, the power supply voltage variation detecting unit; A power signal delay unit; Initialization time adjusting unit; And an initialization signal output unit.

The power supply voltage change detection unit detects a voltage change of the power supply and generates a voltage change signal. The power signal delay unit generates a delay power signal by delaying the power signal. The initialization time adjusting unit receives the voltage change signal and the delay power signal and generates an initialization time adjustment signal having a predetermined time width. The initialization signal output unit receives the voltage change signal and the initialization time adjustment signal to generate the initialization signal, and outputs the initialization signal to the initialization signal input terminal of the volatile integrated circuit.

The initialization time adjustment unit may include a time constant generation unit generating a time constant for adjusting the initialization time, an initialization time adjustment signal generation unit for generating an initialization time adjustment signal by receiving the time constant, and the voltage fluctuation signal and the delay power signal. And a signal input unit for receiving the logical product and inputting the result to the initialization time adjustment signal generation unit.

The time constant generator is interposed between the power supply and the ground in series with a resistor and a capacitor, and both ends of the capacitor are connected to the initialization time adjustment signal generator.

Preferably, the time constant is determined by the product of the resistance value of the resistor and the capacitance, and the time width of the initialization time adjustment signal is 0.7 times the time constant.

The power signal delay unit is interposed between the power supply and the ground in series with a resistor and a capacitor, and both ends of the capacitor are connected to the initialization time adjustment signal generator.

Preferably, the delay time width of the delay power signal is determined by the product of the resistance value of the resistor and the capacitance.

Preferably, the initialization signal output unit generates the initialization signal by performing an AND operation on the voltage change signal and the initialization time adjustment signal.

In addition, the volatile integrated circuit initialization apparatus of the plasma display panel according to the present invention preferably further includes a reset unit for generating a forced initialization signal.

According to another aspect of the present invention, there is provided a volatile integrated circuit initialization apparatus comprising: a power supply voltage variation detection unit for generating an initialization signal of a volatile integrated circuit in each case of power-on, power-on voltage change, and power-off; A power signal delay unit; Initialization time adjusting unit; And an initialization signal output unit.

The power supply voltage change detection unit detects a voltage change of the power supply and generates a voltage change signal. The power signal delay unit generates a delay power signal by delaying the power signal. The initialization time adjusting unit receives the voltage change signal and the delay power signal and generates an initialization time adjustment signal having a predetermined time width. The initialization signal output unit receives the voltage change signal and the initialization time adjustment signal to generate the initialization signal, and outputs the initialization signal to the initialization signal input terminal of the volatile integrated circuit.

According to the present invention, the plasma display panel can be stably driven by initializing a volatile integrated circuit such as an FPGA in each of power-on, power-on voltage fluctuations, and power-off.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram schematically illustrating a volatile integrated circuit initialization device of a plasma display panel according to an embodiment of the present invention. FIG. 7 is a circuit diagram illustrating the volatile integrated circuit initialization device of FIG. 6 in more detail. FIG. 8 is a waveform diagram schematically illustrating an initialization signal by the volatile integrated circuit initialization device of FIG. 6.

Referring to the drawings, the volatile integrated circuit initialization apparatus 3 of the plasma display panel according to the present invention is a volatile device mounted on the plasma display panel driving apparatus in each of power-on, voltage fluctuations in power, and power-off. Generating an initialization signal of the integrated circuit 41, the power supply voltage variation detecting unit 31; A power signal delay unit 32; An initialization time adjusting unit 33; And an initialization signal output section 34.

The power supply voltage change detector 31 detects a voltage change of the power supply and generates a voltage change signal. The power signal delay unit 32 delays the power signal to generate a delayed power signal. The initialization time adjustment unit 33 receives the voltage change signal and the delay power signal and generates an initialization time adjustment signal having a predetermined time width. The initialization signal output unit 34 receives the voltage change signal B1 and the initialization time adjustment signal B2 to generate an initialization signal B3, and converts the initialization signal into an initialization signal input terminal of the volatile integrated circuit 41. Output

In this case, a field programmable gate array (FPGA) is used as the volatile integrated circuit 41 mounted in the plasma display panel driving apparatus, and the driving apparatus according to the present invention requires a complicated internal circuit arrangement and a large capacity. Sufficient initialization time is required for this

 In particular, the volatile integrated circuit initialization apparatus 3 according to the present invention may be used in a logic controller 22 of FIG. 3, in which a logic controller processes an internal image signal input from an image processor. And a memory controller for controlling the frame memory.

An FPGA is a circuit designed to operate and design arbitrary logic circuits as intended by the user. When a design change is made during use, the FPGA can input a newly changed logic circuit into the FPGA device to operate as the changed logic circuit. It is an integrated circuit. Accordingly, the logic controller 22 of FIG. 3 may be configured to include an FPGA.

That is, the logic controller includes a clock buffer, a synchronization controller, a gamma correction unit, an error diffusion unit, a first-in first-out memory, a subfield generator, a subfield matrix unit, a matrix buffer unit, a memory control unit, and a frame- Memory, rearrangement unit, average signal level detection unit, power control unit, Y pyrom, I ² C serial communication interface, timing signal generator, and XY control unit, many of the components can be implemented in FPGA There will be.

The power supply voltage change detection unit 31 generates a voltage change signal by detecting a voltage change of the power supply. When the voltage of the power supply changes based on a predetermined level, the power supply voltage change detection unit 31 generates and outputs a voltage change signal having a predetermined level. That is, the power supply voltage fluctuation detector 31 clamps the output voltage to a reference level (for example, 0V) when the power supply voltage falls below a predetermined level, and sets the output voltage when the power supply voltage rises above a predetermined level. Output at a level (e.g., 3.3V) to detect voltage fluctuations in the power supply to generate a voltage fluctuation signal.

In the present embodiment, the power supply voltage fluctuation detecting element 311 is used to implement the power supply voltage fluctuation detecting unit as described above. A commercial integrated circuit may be used as the power supply voltage fluctuation detecting element, and a KIA70 ×× series may be used. At this time, the resistor R1 and the capacitor C1 are connected in series between the power supply terminal and the ground, and the connection portion of the power supply terminal, the resistor R1 and the capacitor C1 is connected to the power supply voltage fluctuation detecting element 311, respectively. Can be.

The power signal delay unit 32 generates a delayed power signal by delaying the power signal, and delays the power signal input to the initialization time adjustment unit 33 by a predetermined time width so that the initialization time adjustment unit can be normally operated. do. That is, the input power signal is input to the input terminal of the initialization time adjustment unit 33 after delaying the input power signal by a predetermined time width, and the input power signal is initialized after the stable operation voltage is applied to the initialization time adjustment unit 33. To be input to (33).

The power signal delay unit 32 has a resistor R2 and a capacitor C2 connected in series between the power source and the ground in order, and both ends of the capacitor C2 are connected to the initialization time adjusting unit 33. Connected. That is, the connection between the resistor R2 and one end of the capacitor C2 is connected to the initialization time adjusting unit 33, and the other end of the capacitor C2 is grounded and connected to the initialization time adjusting unit 33.

The power signal delay unit 32 is connected to a resistor and a capacitor in which a power source Vcc is connected in series, and when the power is first applied, current flows to the capacitor so that no current flows to the initialization time adjustment unit 33, and the capacitor is charged. As the current gradually flows to the initialization time adjustment unit 33, a voltage is gradually applied to the initialization time adjustment unit 33. Thus, the power signal Vcc input by the power signal delay unit 32 is delayed and applied to the initialization time adjustment unit.

At this time, it is preferable that the delay time width t _d of the delay power signal is determined by the product of the resistance value of the resistor R2 and the capacitance of the capacitor C2.

The initialization time adjustment unit 33 receives the voltage change signal and the delay power signal to generate an initialization time adjustment signal having a predetermined time width tp. The time constant generator 331 and the initialization time adjustment signal generator ( 332, and a signal input unit 333.

The time constant generator 331 generates a time constant for adjusting the initialization time tr. The initialization time adjustment signal generation unit 332 receives the time constant and generates an initialization time adjustment signal. The signal input unit 333 receives the voltage change signal A1 from the power supply voltage variation detection unit 31 and the delay power signal A2 from the power signal delay unit, and logically multiplies the voltage change signal and the delayed power signal A3. To the initialization time adjustment signal generator 332.

The time constant generator 331 includes a resistor R3 and a capacitor C3 connected in series between the power supply and the ground in order, and both ends of the capacitor C3 are connected to the initialization time adjustment signal generator 332. It is preferred to be connected. At this time, it is preferable that the time constant is determined by the product of the resistance value of the resistor R3 and the capacitance of the capacitor C3, and the time width of the initialization time adjustment signal is 0.7 times the time constant.

That is, by adjusting the resistance value of the resistance R3 of the time constant generator and the capacitance of the capacitor C3, the initialization time output from the initialization device according to the present invention can be adjusted. Therefore, it is possible to ensure the stable operation of the integrated circuit by successfully performing the initialization of the volatile integrated circuit, such as FPGA, which requires a sufficient initialization time.

To this end, a commercial integrated circuit may be used as the initialization time adjustment signal generator 332 for the volatile integrated circuit initialization apparatus according to the present invention. In this embodiment, a multi-vibrator 74HC221 may be used. .

The initialization signal output unit 34 receives the voltage change signal and the initialization time adjustment signal to generate an initialization signal, and outputs the initialization signal to the initialization signal input terminal of the volatile integrated circuit 41. In this case, the initialization signal output unit 34 may generate the initialization signal by performing a logical multiplication of the voltage change signal and the initialization time adjustment signal.

In addition, the volatile integrated circuit initialization device of the plasma display panel according to the present invention preferably further includes a reset unit 35 for generating a forced initialization signal. The reset unit 35 forcibly causes the volatile integrated circuit initialization device 3 to generate an initialization signal. An open / close switch may be used to generate an initialization signal in hardware when the switch is turned on. .

The volatile integrated circuit initialization apparatus according to the present invention may be applied to any case in addition to the plasma display panel if the volatile integrated circuit such as an FPGA is an electronic device.

9 is a waveform diagram at each terminal of the volatile integrated circuit initialization device according to the present invention when the power is turned on. 10 is a waveform diagram at each terminal of the volatile integrated circuit initialization device according to the present invention when the voltage suddenly changes. 11 is a waveform diagram at each terminal of the volatile integrated circuit initialization device according to the present invention when the power is turned off.

Referring to the drawings, in the volatile integrated circuit initialization apparatus according to the present invention, when the power is turned on (I of FIG. 8), the voltage of the power supply suddenly fluctuates during normal operation (II of FIG. 8), the power is turned off (III in FIG. 8), in each case, an initialization signal having a sufficient time width is generated for a volatile integrated circuit such as an FPGA which requires a long initialization time.

), 및 초기화신호 출력부(도 7의 34)의 출력단자(B3) 각각의 파형도를 도시하였다. When the power supply is on (I in FIG. 8), the voltage variation of the power supply (II in FIG. 8) during operation, and when the power is off (III in FIG. 8), the output terminal (333 of FIG. 7) A3), the input terminal B1 of the initialization signal output unit (34 in FIG. 7), and the output terminal (332 of FIG. 7) of the initialization time adjustment signal generation unit (332 in FIG. 7).

) And waveforms of the output terminal B3 of the initialization signal output section 34 (Fig. 7).

In this case, the volatile integrated circuit initialization apparatus according to the present invention generates and outputs an initialization signal output to an initialization terminal of a volatile integrated circuit such as an FPGA, and is applied to an integrated circuit initialized when the initialization signal is in an L state. . That is, the volatile integrated circuit initialization apparatus according to the present invention is configured to generate an L-level initialization output for initialization, and in the opposite case, the same principle proposed by the present invention may be applied.

Referring to FIG. 9, the signal at the output terminal A3 of the signal input unit 333 of FIG. 7 is output after the input voltage signal Vcc is delayed by a delay time t _d . The signal at the input terminal B1 of the initialization signal output section (34 in Fig. 7) is kept changed to the H state as the power supply voltage Vcc level becomes higher than the operating level.

)에서는 초기화시간 조정신호가 출력되는데, 초기화시간 조정신호는 전원 전압(Vcc) 레벨이 동작 레벨이상이 되면서 H상태로 변경되어 유지되다가 지연시간(t_d)후에 A3 단자의 신호의 레벨이 동작 레벨이상으로 올라가는 경우에 L 상태로 반전되고, 저항(R3)의 저항값과 콘덴서(C3)의 커패시턴스에 의해 정해지는 시정수에 따라 결정되는 시간폭(t_p)만큼 L 상태가 지속된 후에 다시 H 상태로 출력된다. 초기화신호 출력부(도 7의 34)의 출력단자(B3)에서의 신호는 B1 단자의 입력신호와

신호가 논리곱되어 초기화 신호의 시간 폭(tr)만큼 L 상태로 출력된다. Output terminal of the initialization time adjustment signal generator 332 of FIG.

), The initialization time adjustment signal is output.The initialization time adjustment signal is changed to H state while the power supply voltage (Vcc) level is over the operation level, and then the level of the signal of the A3 terminal becomes the operation level after the delay time (t _d ). When it rises above, it reverses to L state, and after H state continues for the time width t _p determined by the time constant determined by the resistance value of the resistor R3 and the capacitance of the capacitor C3, H is again performed. Output as status. The signal at the output terminal B3 of the initialization signal output section 34 in FIG. 7 is different from the input signal at the B1 terminal.

The signal is ANDed and output in the L state by the time width tr of the initialization signal.

Referring to FIG. 10, a section t _i that falls below the operating level from the normal level of the voltage level of the input power source Vcc occurs. Accordingly, the signal at the input terminal B1 of the initialization signal output unit 34 in FIG. 7 drops from the H state to the L state in the interval t _i , and at the output terminal A3 of the signal input unit 333 in FIG. 7. The signal of also falls from the H state to the L state in the t _i interval.

)에서의 신호는 A3 단자에서의 신호가 L 상태에서 H 상태로 변경되는 부분에서 H 상태로부터 L 상태로 변경되고, 저항(R3)의 저항값과 콘덴서(C3)의 커패시턴스에 의해 정해지는 시정수에 따라 결정되는 시간폭(t_p)만큼 L 상태가 지속된 후에 다시 H 상태로 출력된다. 초기화신호 출력부(도 7의 34)의 출력단자(B3)에서의 신호는 B1 단자의 입력신호와

신호가 논리곱되어 초기화 신호의 시간 폭(tr)만큼 L 상태로 출력된다. Output terminal of the initialization time adjustment signal generator 332 of FIG.

The signal at) is changed from the H state to the L state at the portion where the signal at the A3 terminal is changed from the L state to the H state, and is a time constant determined by the resistance value of the resistor R3 and the capacitance of the capacitor C3. After the L state continues for a time width t _p determined according to the output, the state is output again to the H state. The signal at the output terminal B3 of the initialization signal output section 34 in FIG. 7 is different from the input signal at the B1 terminal.

The signal is ANDed and output in the L state by the time width tr of the initialization signal.

Referring to FIG. 11, when the power supply is turned off, the voltage level of the power supply Vcc gradually drops from the normal level to the reference level. Accordingly, when the voltage level of the power supply Vcc falls below the operating level, the signal at the input terminal B1 of the initialization signal output section 34 in FIG. 7 and the output terminal of the signal input section 333 in FIG. The signal at (A3) falls from the H state to the L state.

)에서의 신호는 A3 단자에서의 신호가 L 레벨에서 H 레벨로 변경되는 경우에 H 레벨에서 L 레벨로 변경되는 것으로, 전원(Vcc)의 전압 레벨이 일정 레벨에 도달하기 전까지는 H 상태를 유지하다가, 일정 레벨에 도달된 후부터 점차로 감소한다. Output terminal of the initialization time adjustment signal generator 332 of FIG.

The signal at) is changed from H level to L level when the signal at A3 terminal is changed from L level to H level, and remains H state until the voltage level of power supply Vcc reaches a certain level. It gradually decreases after reaching a certain level.

신호가 논리곱되어 B1 단자에서의 신호와 동일한 신호를 유지한다. 따라서, 전원(Vcc)의 동작 레벨이하에서는 초기화 신호가 L로 유지되어, 집적회로의 초기화 후에 시스템이 종료된다. The signal at the output terminal B3 of the initialization signal output section 34 in FIG. 7 is different from the input signal at the B1 terminal.

The signal is ANDed to maintain the same signal as that at the B1 terminal. Therefore, below the operation level of the power supply Vcc, the initialization signal is kept at L, and the system is terminated after the initialization of the integrated circuit.

According to the volatile integrated circuit initialization apparatus of the plasma display panel according to the present invention, the plasma display panel can be stably driven by initializing a volatile integrated circuit such as an FPGA in each case of power-on, power-voltage change, and power-off. Can be.

In addition, since the time required for the initialization of the volatile integrated circuit that requires a sufficient initialization time can be secured, stable initialization is possible.

In addition, the volatile integrated circuit initialization apparatus according to the present invention may be applied to any case in addition to the plasma display panel if the volatile integrated circuit such as an FPGA is an electronic device.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, it is merely an example, and those skilled in the art may realize various modifications and equivalent other embodiments therefrom. I can understand. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

Claims (16)

By generating the initialization signal of the volatile integrated circuit in each case of power-on, voltage fluctuations of power during operation, and power-off, A power supply voltage change detector for detecting a voltage change of the power supply and generating a voltage change signal; A power signal delay unit for delaying a power signal of the power supply to generate a delayed power signal; An initialization time adjusting unit receiving the voltage change signal and the delay power signal and generating an initialization time adjusting signal having a time width determined by a time constant; And And an initialization signal output unit configured to receive the voltage change signal and the initialization time adjustment signal, generate the initialization signal, and output the initialization signal to an initialization signal input terminal of the volatile integrated circuit. The method of claim 1, The initialization time adjusting unit, A time constant generator for generating a time constant for adjusting the initialization time, an initialization time adjustment signal generator for generating an initialization time adjustment signal by receiving the time constant, and receiving and multiplying the voltage change signal and the delayed power signal by An initialization device for a volatile integrated circuit comprising a signal input unit for inputting an initialization time adjustment signal generation unit. The method of claim 2, And the time constant generator is interposed between the power supply and the ground in series with a resistor and a capacitor, and both ends of the capacitor are connected to the initialization time adjustment signal generator. The method of claim 3, And the time constant is determined by the product of the resistance value of the resistor and the capacitance of the capacitor, and the time width of the initialization time adjustment signal is 0.7 times the time constant. The method of claim 1, And the power signal delay unit is interposed between a power supply and a ground in series with a resistor and a capacitor, and both ends of the capacitor are connected to the initialization time adjustment unit. The method of claim 5, And a delay time width of the delay power signal is determined by a product of a resistance value of the resistor and a capacitance of the capacitor. The method of claim 1, The initialization signal output unit, And an initialization device of the volatile integrated circuit generating the initialization signal by performing a logical AND of the voltage change signal and the initialization time adjustment signal. The method of claim 1, And a reset unit for generating a forced initialization signal. In each case of power-on, voltage fluctuations of power during operation, and power-off, generating an initialization signal of a volatile integrated circuit mounted on the plasma display panel driver. A power supply voltage change detector for detecting a voltage change of the power supply and generating a voltage change signal; A power signal delay unit for delaying a power signal of the power supply to generate a delayed power signal; An initialization time adjusting unit receiving the voltage change signal and the delay power signal and generating an initialization time adjusting signal having a time width determined by a time constant; And Initializing the volatile integrated circuit of the plasma display panel having an initialization signal output unit for receiving the voltage change signal and the initialization time adjustment signal to generate the initialization signal, and outputs the initialization signal to the initialization signal input terminal of the volatile integrated circuit. Device. The method of claim 9, The initialization time adjusting unit, A time constant generator for generating a time constant for adjusting the initialization time, an initialization time adjustment signal generator for generating an initialization time adjustment signal by receiving the time constant, and receiving and multiplying the voltage change signal and the delayed power signal by A volatile integrated circuit initialization device of a plasma display panel including a signal input unit for inputting an initialization time adjustment signal generation unit. The method of claim 10, And the time constant generator is interposed between the power supply and the ground in series with a resistor and a capacitor, and both ends of the capacitor are connected to the initialization time adjustment signal generator. The method of claim 11, And the time constant is determined by the product of the resistance value of the resistor and the capacitance of the capacitor, and the time width of the initialization time adjustment signal is 0.7 times the time constant. The method of claim 9, And the power signal delay unit is interposed between the power supply and the ground in series with a resistor and a capacitor, and both ends of the capacitor are connected to the initialization time adjustment unit. The method of claim 13, And a delay time width of the delay power signal is determined by a product of a resistance value of the resistor and a capacitance of the capacitor. The method of claim 9, In the initialization signal output unit, And generating the initialization signal by multiplying the voltage change signal and the initialization time adjustment signal. The method of claim 9, And a reset unit for generating a forced initialization signal.

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