JPH08313589A - Method for diagnosing/inspection connection between lsi package and substrate - Google Patents

Abstract

PURPOSE: To easily and highly reliably diagnose/inspect the connection between an LSI package and substrate by making a plurality of copper foil pads connectable depending upon the wetting states of bumps and connecting a plurality of bonding pads to the copper foil pads, in a chain-like state. CONSTITUTION: A plurality of bonding pads (a) and (b) are provided in each buffer section 1 and 2 and a plurality of copper foil pads PAD1-3 are provided on an LSI package. At the time of performing diagnosis/inspections, the buffer sections 1 and 2 connect the pads (a) and (b) to selector circuits, etc. As a result, the pads PAD1-3 are connected in a chain-like state when the solder bumps have good solder wettability and the bumps are accurately formed on the copper foil pads PAD1-3, because the pad (a) of the buffer section 1 is connected to the pad (b) of the buffer section 2 on the copper foil pad PAD2. Therefore, the connection between an LSI package and substrate can be diagnosed/inspected easily by confirming the coincidence between an input signal SIG1 from the pad PAD1 or output signal SIG2 from a buffer and the output signal from the pad PAD3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to diagnosis / inspection of connection between an LSI package and a board, and more particularly to BGA (Ball Grid).
d Array) etc. related to the connection diagnosis / inspection between the surface mount type package and the board.

[0002]

2. Description of the Related Art A connection diagnosis / inspection method after mounting an LSI is to either electrically check or visually check. As a method of electrically confirming the connection of the LSI package, there is a method of inspecting using a boundary scan circuit called JTAG which is standardized by IEEE. Further, visually, there is a method of confirming the connection by an X-ray inspection.

[0003]

When inspecting the connecting portion between the LSI package and the substrate, it is not possible to perform visual inspection.
There is a method of visually inspecting with a line inspection machine, but this poses a cost problem.

Further, when the connection diagnosis / inspection is performed electrically, the wettability of the solder is good because the wettability of the solder is poor at the connection portion, and the solder ball melts properly, and the solder ball is properly melted. There is a drawback that you do not know if it is connected.

[0005]

An object of the present invention is to provide an LSI
(EN) Provided is a structure of an LSI package and a semiconductor integrated logic circuit capable of increasing the reliability of connection between the package and a printed circuit board when the package is mounted on the printed circuit board.

A semiconductor integrated logic circuit according to the present invention has a plurality of input / output buffers, and each of the plurality of input / output buffers has a plurality of bonding pads. The LSI package according to the present invention is provided with a selector circuit which provides a corresponding input / output or a selector circuit for selectively connecting the plurality of bonding pads.
Solder bumps (solder balls) with surface mount packages such as
And a plurality of copper foil pads (leads of the LSI) corresponding to the plurality of bonding pads of the semiconductor integrated logic circuit are provided, and further, the solder bumps are provided not on the LSI package side but on the substrate side. Characterize.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 shows the appearance of the LSI package of the present invention.

In FIG. 1, solder bumps (solder balls)
Is provided not on the LSI package side but on the substrate side.

FIG. 2 shows an embodiment of the copper foil pad of the present invention. In FIG. 2, the copper foil pad has two input / output buffers, and
The copper foil pads A and B correspond to this. Further, the copper foil pad is provided with solder paste and has a circular shape, and the solder paste evenly attracts the solder bumps (solder balls) on the substrate of FIG. 1 at the time of mounting. Even if it is misaligned, the self-alignment function is considered so that it can be returned to the center and mounted correctly. Therefore, the solder bumps evenly wet the outer copper foil pads B during mounting.

FIG. 3 shows an example of the basic circuit configuration of the input / output buffer section in the semiconductor integrated logic circuit of the present invention.

In FIG. 3, DATA1 is a signal line for exchanging data at the time of input / output. Also, EN
1 and EN2 are enable signal lines of each buffer. By inputting a low level, it becomes an enable state and data output can be performed, and by inputting a high level, it is disenabled and becomes a high impedance state. Become.

Therefore, when data is input from the outside to the inside of the LSI, a high level is input to EN1 and EN2. When data is output from the inside of the LSI to the outside, a high level is input to EN1 and a low level is input to EN2. Further, when the bonding pads a and b are connected at the time of connection diagnosis / inspection between the LSI package and the substrate, it can be realized by inputting a high level to EN2 and a low level to EN1.

FIG. 4 shows another example of the basic circuit configuration of the input / output buffer section in the semiconductor integrated logic circuit of the present invention.

In FIG. 4, the selector switches the operation as a normal bidirectional buffer and the operation for connecting the bonding pads a and b at the time of diagnosis / inspection of the connection between the LSI package and the substrate by the select signal SEL1. It was realized.

FIG. 5 shows an embodiment of the present invention.

In FIG. 5, the buffer unit 1 and the buffer unit 2 are LSIs as described in FIGS. 3 and 4.
During the connection diagnosis / inspection between the package and the substrate, the bonding pads a and b are connected by a selector circuit or the like.

Further, PAD1, PAD2, and PAD3
As described above with reference to FIG. 2, if the solder bumps have good wettability and are mounted correctly, in the PAD 2, a of the buffer unit 1 and b of the buffer unit 2 are connected.

With this connection, PAD1 to PAD
Up to 3 are connected in a chain shape, and when conventionally performing electrical connection diagnosis / inspection, the wettability of the solder is poor at the connection part and the solder wettability is good and the solder ball is What had the drawback of not knowing whether it was melted and connected properly was that the input data from PAD1: SIG1 or the output data from the buffer:
By confirming the match between the SIG2 and the output data from the PAD3, it is possible to easily diagnose / inspect the connectivity.

FIG. 6 shows the connectivity between the solder bumps and the copper foil pads.

In FIG. 6, (1) is an open state,
(2) is a state where they are just in contact, (3) is a state where the solder bumps have poor wettability, and (4) is a state where the solder bumps have good wettability. It indicates that

The copper foil pad, the buffer portion, and the bonding pad may be more or more in number, and the shape of the copper foil pad may not be circular. Needless to say, is not necessarily copper or solder.

[0023]

As described above, according to the present invention, a switching circuit is provided in the input / output buffer circuit section so that a plurality of bonding pads can be switched and connected, and when bumps (solder bumps, etc.) are wetted during LSI mounting, By connecting a plurality of pads and connecting a plurality of bonding pads and a plurality of copper foil pads (lead parts of LSI) in a chain shape, when the connection diagnosis / inspection is conventionally performed electrically, the connection parts are It is easy to trust what has the disadvantage that the solder wettability is bad and it is not just in contact, the solder wettability is good, and the solder ball melts and is properly connected. A high degree of connectivity diagnosis / inspection is possible.

[Brief description of drawings]

FIG. 1 is an external view of an LSI package of the present invention.

FIG. 2 is an example of the copper foil pad of the present invention.

FIG. 3 is an example of a basic circuit configuration of an input / output buffer section in the semiconductor integrated logic circuit of the present invention.

FIG. 4 is an example of a basic circuit configuration of an input / output buffer section in the semiconductor integrated logic circuit of the present invention.

FIG. 5 is a block diagram of an embodiment of the present invention.

FIG. 6 Solder bumps and copper foil pads (leads of LSI)
It is explanatory drawing which shows the quality of connectivity with.

[Explanation of symbols]

A, B ... Copper foil pad (lead of LSI), a, b ...
Bonding pad, EN1, EN2, EN3 ... Enable terminal of input / output buffer, DATA1, DATA2 ...
Input / output buffer data terminal, SEL1 ... Selector select terminal, PAD1, PAD2 ... Copper foil pad (LSI
, SIG1, SIG2 ... Input signals for connectivity diagnostic / test.

Claims (1)

[Claims] 1. A plurality of bonding pads respectively provided corresponding to a plurality of input / output buffers, and a plurality of copper foil pads (leads of LSI) on an LSI package. Then, a selector circuit which inputs / outputs a corresponding signal from the input / output buffer or selectively supplies a signal from another bonding pad is provided, and a plurality of copper foil pads on the LSI package ( LSI leads) are connected to each other so that the plurality of bonding pads and the plurality of copper foil pads (LSI leads) on the LSI package can be connected in a chain shape, and solder bumps can be formed on the substrate. And a method for diagnosing / inspecting a connection between an LSI package and a substrate, an LSI package structure, and a semiconductor package. Circuit.