JPH0831183A - Voltage type sense amplifier - Google Patents

Abstract

PURPOSE:To obtain a voltage type sense amplifier of 1 stage CMSA constitution and a voltage type sense amplifier of 2 stage CMSA constitution which can stably obtain sufficient amplification factor and output even when a low voltage source is used. CONSTITUTION:This device is provided with P type MOS transistors 11, 12 pulling up an input data line of a memory cell 13, current mirror type sense amplifiers 15a, 16a of 1 stage CMSA constitution amplifying data DATA, *DATA of the memory cell 13 transmitted from data lines BLA, *BLA, and MOS transistors 31, 32 constituting a negative feedback type MOS circuit raising a common source potential at a common source side of its driving stage. Further. this device is provided with current mirror type sense amplifiers 15b, 16b of 2nd stage amplifying DATAa, *DATAa of current mirror type sense amplifiers 15a, 16a, and a voltage type sense amplifier of 2 stage CMSA constitution is formed so that it is constituted with a complementary MOS circuit using P type MOS transistors 41, 42 at a load side of an output amplifying stage 40 and output signals *OUTa, OUTa are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current type sense amplifier for amplifying data in a memory cell transmitted via a data line using a current mirror type sense amplifier (hereinafter referred to as CMSA), and more particularly to a power supply. The present invention also relates to a voltage-source sense amplifier suitable even when a low-voltage power supply is used.

[0002]

2. Description of the Related Art When information is taken out from a data line from a memory cell such as a static RAM, a data output level is small, so that a sense amplifier amplifies the information to a predetermined level. In this case, a voltage-type sense amplifier is used as a sense amplifier that is resistant to noise and manufacturing process variations. FIG. 6 shows an example of a conventional voltage type sense amplifier. In FIG. 6, the bit line line pair BLA, * BLA is pulled up by P-type MOS transistors (hereinafter referred to as PMOS) 11 and 12 and supplied to the memory cell 13. Due to the capacitance existing between the bit line line pair BLA, * BLA (* indicates an inversion sign, the same applies below) and the bit line line pair (not shown) adjacent to the bit line line pair, a memory cell is provided in the adjacent bit line line pair. If there is a large level change due to writing or the like, the bit line line pair BLA, * BLA is also affected. When the power source has a high voltage (for example, 5V), the actual effect is small, but when the power source has a low voltage (for example, 3V), the effect cannot be ignored.

FIG. 7 and FIG. 8 show the influence of the level fluctuation of the adjacent bit line pair.
If an N-type MOS transistor (hereinafter referred to as NMOS) is used for pulling up the bit line pair, the potential drop is large. Therefore, in the case of a low voltage power supply, the potential BLBV of the adjacent bit line pair BLB, * BLB,
When * BLBV becomes low level, as shown in FIG. 7, a pair of bit line lines BLA, * supplied to the memory cell 13
The potentials BLAV and * BLAV of BLA are also lowered. As a result, the data node potential N in the memory cell 13
Since it becomes lower than V and * NV, the memory cell 13 may not be able to reliably and stably hold the data. On the other hand, when a PMOS is used for pulling up the bit line pair BLA, the potential drop is small. Therefore, even if the potential BLBV, * BLBV of the adjacent bit line pair BLB, * BLB becomes low potential. As shown in FIG. 8, the potentials BLAV, * BLAV of the bit line pair BLA, * BLA supplied to the memory cell 13 are only slightly lowered, and the data node potentials NV, * NV in the memory cell 13 are reduced. Is much higher than memory cell 1
3 can hold the data reliably and stably. Therefore, when a low voltage power supply is used, the bit line pair BLA, * BLA is pulled up by using PMOS.

Data D retrieved from memory cell 13
ATA and * DATA are decoded by the Y gate 14 and taken out on the data line pair DLA and * DLA to obtain C
Supplied to MSA 15 and 16. CMSA 15 and 1
Since 6 has the same structure, CM and CM
This will be described with reference to SA15. In CMSA15,
In the current mirror circuit forming the active load circuit, the gate of the PMOS 151, which connects the drain and the gate, has the PMO
It is configured by being connected to the gate of S152. NMOS 1
53 is a driving stage for driving the PMOS 151,
The OS 154 is a drive stage that drives the PMOS 152. Both sources of the NMOSs 153 and 154 are connected to a power source through a lead biasing NMOS 17,
A read signal READ is applied to the gate of 17.

An output * OUTa is generated as an output terminal of the CMSA 15 from the connection point of both drains of the PMOS 152 and the NMOS 154. Furthermore, at this connection point, PM
Both sources of OS155 and NMOS156 are connected,
Both drains of the PMOS 155 and the NMOS 156 are P
It is connected to the connection point between the MOS 151 and the NMOS 153.
CMS is used for the gates of the PMOS 155 and the NMOS 156.
The equalize signals * EQ and EQ of A15 are applied.
The above configuration is the CMSA 16 and the NMO for biasing the leads.
The same applies to S18, but the output of the CMSA 16 is OUTa. With this configuration, when reading,
When the read signal READ is applied to the gate of the NMOS 17, the NMOS 17 and 18 are turned on and the CMSA1
5 and 16 are activated. On the other hand, the data DATA and * DATA retrieved from the memory cell 13 are CMSA15.
In the CMSA 15, data * DATA is supplied to the gate of the NMOS 153.
The data DATA is supplied to the gate of the NMOS 154. On the other hand, the equalization signals EQ and * EQ of the CMSA 15
Is released (EQ is low level, * EQ is high level), the data DATA and * DATA of the memory cell 13 are supplied to the CMSA 15 (data spread), and output terminals (both drains of the PMOS 152 and the NMOS 154). The output * OUTa of the CMSA 15 is generated from the connection point).

2 and 3 describe the operating characteristics of the CMSA 15 and its signal waveforms, the contents thereof are also applied to the operation of the CMSA 16 and its operating characteristics. The drain-source voltage Vds vs. drain-source current Ids characteristic (operating characteristic) of the PMOS 151 and 152 of the CMSA 15 becomes the operating characteristic indicated by Ca, and N
The operating characteristics of the MOSs 153 and 154 are those indicated by Cb (note that the operating characteristics Ca ′ and Cb ′ will be described later in connection with Example A of the present invention).
Therefore, the operating points of the PMOS 151 and the NMOS 153 are P points, and the operating points of the PMOS 152 and the NMOS 154 are also P points. As is clear from the figure,
PMOS 151 and 152 operate in the saturation region, but N
The MOSs 153 and 154 operate in the linear region. MOS
Although the transistor has a large amplification factor in the saturation region, it cannot obtain a sufficient amplification factor in the linear region. Therefore, as shown by the dotted line in FIG. 3, the outputs * OUT of the CMSAs 15 and 16
The output of the sense amplifier becomes a low level as represented by the level difference between a and the output OUTa, and a sufficient amplification degree and output cannot be obtained (the output * OUTa ′ and OUT).
a 'will be described later in connection with Example A of the present invention).

As a voltage type sense amplifier which is an improvement of the above voltage source type sense amplifier of CMSA, CMSA2
There are voltage sense amplifiers in stages. This is improved by amplifying the data of the memory cell transmitted from the data line by using the two-stage CMSA so that the amplification degree is large and the output is also large. FIG. 9 shows an example of a conventional CMSA two-stage current source sense amplifier. In FIG. 9, the one-stage CM shown in FIG.
The same components as those in the SA current source sense amplifier will be described using the same reference numerals. The first-stage CMSA and read energizing gate NMOS are CMSA 15a and NMOS1.
7a, CMSA 16a, and NMOS 18a, and CMSA of the second stage and read energizing gate NMOS are CM
SA15b, NMOS17b and CMSA16b, N
A MOS 18b is used for distinction. 19 is PMOS and N
An equalizer circuit in which MOSs are connected in parallel.
Connected between the output terminals of 15a and 16a, both CMSA
The equalizing circuit provided inside (155, 156 of FIG. 6)
And 165, 166). Memory cell 1
The data fetched from No. 3 is the CMSA 15a on the first stage.
The operations up to the amplification by 16a and 16a are the same as those of the voltage source sense amplifier of the conventional CMSA one-stage configuration described in FIG. The outputs of the CMSAs 15a and 16a are indicated by data * DATAa and data DATAa. The output data is amplified by the CMSA 15b and the CMSA 16b in the second stage. The outputs of the CMSAs 15b and 16b are indicated by data * DATAb and data DATAb,
Furthermore, it is applied to the output amplifier 20 and amplified.

In the output amplifier 20, 21 and 22 are PMOSs, and read signals READ * (READ * is RE
It is a gate which is turned on by a complementary signal of AD). Two
3 and 25 are NMOSs that constitute an output drive stage,
Both NMOSs are connected in series, the drain of the NMOS 23 is connected to the drain of the PMOS 21, and the source of the NMOS 25 is connected to the power supply. Output data * DATAb from the CMSA 15b is supplied to the gate of the NMOS 23. The gate of the NMOS 25 has a CMSA 15b
The output data DATAa of the CMSA 16a for driving the. Data from the connection point of NMOS 23 and 25 *
NMOS2 that outputs DATAc and forms an output stage
7 gate. The output OUTb is output from the drain of the output stage NMOS 27. NMOS 2
An NMOS 29 is connected between the drain of No. 5 and the power supply, and an equalize signal EQ for controlling the start of operation of the output drive stage is applied to its gate.

On the other hand, 24 and 26 are NMOSs which constitute an output drive stage, and both NMOSs are connected in series, and N
The drain of the MOS 24 is connected to the drain of the PMOS 22, and the source of the NMOS 26 is connected to the power supply. NM
Output data DATAb from the CMSA 16b is supplied to the gate of the OS 24. The output data * DATAa of the CMSA 15a is supplied to the gate of the NMOS 26. Data DAT from the connection point of NMOS 24 and 26
Ac is output and supplied to the gate of the NMOS 28 forming the output stage. The output * OUTb is output from the drain of the output stage NMOS 28. An NMOS 30 is connected between the drain of the NMOS 26 and the power supply, and an equalize signal EQ for controlling the start of operation of the output drive stage is applied to its gate. Since the output drive stage of the output unit 20 uses the NMOSs 23 and 24 on the load side, there is a potential drop corresponding to the threshold values of the NMOSs 23 and 24 in addition to the potential drop due to the operating resistance of the gate PMOSs 21 and 22. Therefore, the levels of the output data * DATAc and DATAc decrease accordingly. However, the power source is 5V
In the case of a high voltage power supply such as, the potential drop is smaller than the power supply voltage, so the output data DATAc and *
The level of DATAc is high, and the output stage NMOSs 27 and 2
Since 8 could be driven sufficiently, there is no particular problem in practice.

However, when a low voltage power source such as 3V is used, the PMOSs 21 and 22 and the NM are
Output data * due to potential drop due to OS23 and 24
There is a possibility that the levels of DATAc and DATAc will decrease and the output stage cannot be driven sufficiently. FIG. 10 shows a two-stage C
4 shows the operating characteristics of a voltage type sense amplifier having an MSA configuration. The output data * DATAb and DATAb of the second stage CMSAs 15b and 16b have sufficient levels, but the output data DATAc and * DATA of the output drive stage are sufficient.
The level of c becomes a low level as shown in the figure due to the above-mentioned potential drop, the output stage NMOSs 27 and 28 cannot be sufficiently driven, and the outputs OUTb and * OUTb become a low level.

[0011]

In the conventional voltage-type sense amplifier having the CMSA one-stage structure, when the power supply voltage is a high voltage power supply, a sufficient amplification degree and output can be obtained from the memory cell to be read. However, in the case of a low voltage power supply, the operating point of the drive stage of the CMSA is in the linear region,
There is a disadvantage that it is not possible to stably obtain a sufficient amplification degree and output. Further, in the voltage-type sense amplifier of the two-stage CMSA configuration, when the power supply voltage is a high-voltage power supply, both the first-stage and second-stage CMSAs operate well, and a sufficient amplification factor and output from the memory cell to be read. Can be obtained. However, in the case of a low-voltage power supply, in addition to the above problem, since the voltage drop on the load side of the output drive stage in the output amplification section of the second stage CMSA is large, the drive output data becomes low level and the next stage However, there is a problem in that it is not possible to sufficiently drive the output stage connected to, and thus it is not possible to stably obtain a sufficient level of output data from the output stage.
The present invention solves the above-mentioned inconvenience, and can provide a sufficient amplification degree and stable output even when a low voltage power supply is used.
It is an object of the present invention to provide a voltage source sense amplifier having a one-stage configuration and a voltage source sense amplifier having a two-stage CMSA configuration.

[0012]

In order to solve the problems of the prior art and achieve the above-mentioned object, the CMS according to the present invention
The A1 stage configuration voltage type sense amplifier is a voltage type sense amplifier that amplifies data of a memory cell transmitted from a data line by using a CMSA, pulls up an input data line of the CMSA with a PMOS, and further, A circuit for raising the common source potential is provided on the common source side of the driving stage of the above. Here, the circuit for increasing the source potential of the CMSA may be formed of a negative feedback MOS circuit.

Further, the voltage-type sense amplifier of the CMSA two-stage structure according to the present invention is a first-stage CMSA in the voltage-type sense amplifier for amplifying the data of the memory cell transmitted from the data line by using the two-stage CMSA. The input data line of is pulled up by the PMOS and the first stage CM
A circuit for raising the common source potential is provided on the common source side of the SA drive stage, and an output amplification section for amplifying the output of the CMSA of the second stage is provided.
It is characterized by being constituted by an OS circuit. And the above 1
The circuit that raises the common source potential of the driving stage of the CMSA of the second stage can be configured by a negative feedback MOS circuit.

[0014]

Since the input data line of the CMSA is pulled up by the PMOS in the voltage source sense amplifier of the CMSA one-stage structure, even if the bit line line of the memory cell to be read under a low voltage power supply has a level fluctuation, the memory cell Data can be taken out stably from. Furthermore, CMSA
Since a circuit for increasing the common source potential is provided on the common source side of the driving stage of the CMSA, both the load side and the driving stage side MOS circuits of the CMSA operate with the saturation region as the operating point. . As a result, as compared with the conventional CMSA in which the MOS circuit in the driving stage operates in the linear region, the amplification degree of the CMSA is increased and a large output can be stably obtained. Therefore, when a high-voltage power supply is used as the power supply voltage, as well as when a low-voltage power supply is used, the amplification degree is large and the output is large as compared with the conventional voltage sense amplifier having the CMSA one-stage configuration. It can be obtained stably. Further, in this case, if the circuit for raising the common source potential of the driving stage is composed of a negative feedback MOS circuit, the CMSA has a simple circuit structure.
It is possible to raise the common source potential of the driving stage during the operation of.

Further, in the voltage-type sense amplifier having a two-stage structure of CMSA, the input data line of the first-stage CMSA is PM
Since a circuit for raising the common source potential is provided on the common source side of the driving stage of the CMSA of the first stage while being pulled up by the OS, as described above, the bit of the memory cell is under the low voltage power supply. Even if there is a level change in the line pair, stable data can be taken out, and CM
In the SA, both MOS circuits on the load side and the drive stage side operate with the saturation region as the operating point. As a result, even when a low voltage power supply is used, the first stage CMS
As the amplification degree of A increases, a large output can be stably obtained. Furthermore, since the output drive stage of the output amplifier for amplifying the output of the sense amplifier of the second CMSA is composed of the complementary PMOS circuit using the PMOS on the load side, even when the low voltage power source is used as the power source. , The potential drop of the load side stage is reduced and a sufficiently large drive output can be generated, and the next output stage can be sufficiently driven to obtain a large output. And the above 1
If the circuit for raising the common source potential of the CMSA driving stage of the second stage is configured by a negative feedback MOS circuit, it is possible to raise the common source potential of the driving stage during the operation of the CMSA with a simple circuit configuration.

[0016]

【Example】

(Embodiment A) An embodiment A of the voltage source sense amplifier of the CMSA one-stage structure according to the present invention will be described below with reference to FIGS. FIG. 1 shows an example of the configuration of the embodiment A, FIG. 2 is an explanatory diagram of its operation characteristic, and FIG. 3 is an explanatory diagram of its signal waveform. In FIG.
The components common to those of the conventional voltage source sense amplifier of the CMSA one-stage configuration described with reference to FIG. That is, the bit line line pair BLA, * B
LA is pulled up by the PMOSs 11 and 12 and supplied to the memory cell 13. Bit line pair B
When a PMOS is used for pulling up LA, the potential drop is small, so that the voltage supplied to the memory cell can have a sufficient margin. As a result, even if the potential of the adjacent bit line pair (not shown) becomes low due to writing or the like, as described above (see FIG. 8), the bit line pair BLA supplied to the memory cell 13 is The potentials of * BLA, BLAV, * BLAV drop only slightly, and the data node potentials NV, * NV in the memory cell 13 are reduced.
Since it is sufficiently higher than that, the memory cell 13 can securely and stably hold the data.

Data D retrieved from memory cell 13
ATA and * DATA are decoded by the Y gate 14 and taken out on the data line pair DLA and * DLA to obtain C
Supplied to MSA 15 and 16. CMSA 15 and 1
Since 6 has the same structure, the configuration and operation of both will be described below with the CMSA 15.
It is also applied to the MSA16. In the CMSA 15, the current mirror circuit, which is an active load circuit, is configured by connecting the gate of the PMOS 151, whose drain and gate are connected, to the gate of the PMOS 152. NM
The OS 153 is a driving stage for driving the PMOS 151,
The NMOS 154 is a driving stage of the PMOS 152. NM
Both sources of the OSs 153 and 154 are commonly connected. From the connection point of both drains of the PMOS 152 and the NMOS 154, output as the output terminal of the CMSA 15 * OU
Ta is generated. NMOS 17 is a read signal READ
It is a gate that is turned on by activating the CMSA 15. Furthermore, at this connection point, the PMOS 155 and the NMO are connected.
Both sources of S156 are connected, and PMOS 155 and N
Both drains of the MOS 156 are connected to the PMOS 151 and the NMO.
It is connected to the connection point of S153. PMOS 155 and 1
Equalize signals * EQ and EQ are applied to the gate of 56. The above CMSA 15 and lead energizing gate NM
The configuration related to the OS 17 is the same for the CMSA 16 and the read energizing gate NMOS 18, but the CMSA 1
The output of 6 is OUTa.

The above-described structure is common to the structure of the conventional voltage-type sense amplifier having the CMSA one-stage structure. Next, the structure of the characteristic part of the present invention will be described.
Reference numeral 31 is an NMOS that constitutes a negative feedback circuit, and is a CMSA.
A drain and a gate of the NMOS 31 are connected to a common source of the driving stage NMOSs 153 and 154 of 15, and the source thereof is connected to a drain of the read energizing gate NMOS 17. Similarly, 32 is an NMOS that constitutes the negative feedback circuit on the CMSA 16 side, and is a driving stage NMOS of the CMSA 16.
The drain and gate of the NMOS 32 are connected to the common source of 163 and 164, and the source is connected to the drain of the read energizing gate NMOS 18. In this configuration, at the time of reading, when the read signal READ is applied to the gates of the NMOSs 17 and 18, the NMOSs 17 and 18 are
Is turned on and CMSAs 15 and 16 are energized. On the other hand, the data DATA retrieved from the memory cell 13,
* Each DATA is supplied to CMSA 15 and 16. In CMSA15, data * DATA is NM
The data DATA supplied to the gate of OS153 is NM.
It is supplied to the gate of the OS 154. On the other hand, CMSA15
The equalizing signals EQ and * EQ of the memory cell 13 are released (EQ is low level, * EQ is high level), and the data D of the memory cell 13 is
When ATA and * DATA are supplied to CMSA15 (data spreads), CMSA1 is output from the output terminal (connection point of both drains of PMOS 152 and NMOS 154).
5 outputs * OUTa are generated.

On the other hand, the NMOS 31 constituting the negative feedback circuit
Is supplied with an operating current from the common source of the drive stage of the CMSA 15. The NMOS 31 causes a potential drop proportional to the magnitude of the operating current due to its negative feedback effect. Accordingly, the drive stage NMOSs 153 and 154 of the CMSA 15 are provided.
The common source potential of the voltage rises in proportion to the operating current. As a result, the operating point of the CMSA 15 shifts to the high voltage side. 2 and 3 explain the operating characteristics of the CMSA 15. Since the potential is increased by the negative feedback NMOS 31, the PMOS 151 and 15 of the CMSA 15 are
The drain-source voltage Vds vs. drain-source current Ids characteristic (operating characteristic) of No. 2 shifts from Ca to the operating characteristic represented by Ca ′, and the operating characteristics of the NMOSs 153 and 154 are the same operating represented by Cb to Cb ′. Transition to characteristics. Therefore, PMOS 151 and NMOS 153
The operating point of P is changed from P point to P ′ point, and the PMOS 152
Similarly, the operating points of the NMOS 154 and the NMOS 154 shift to the point P ′.

As is apparent from the figure, both the PMOS 151 and 152 and the NMOS 153 and 154 come to operate in the saturation region. MOS transistors are
Since the amplification degree is large in the saturation region, a sufficient amplification degree can be obtained as shown in FIG. The characteristic indicated by the solid line in FIG. 3 shows the operating characteristic of the embodiment A. The output * OUTa 'having a sufficiently large level difference is larger than the output * OUTa of the conventional CMSA shown by the dotted line.
It is output from the connection point of the MOS 154. CMSA mentioned above
15, lead energizing gate NMOS 17 and its negative feedback N
The operation content regarding the MOS 31 is the operation content of the CMSA 16, the read energizing gate NMOS 18, and the negative feedback NMOS 32 thereof. PMOS 161 and 162 constituting the current mirror circuit and its driving stage NMO
The operating points of S163 and 164 shift from the conventional point P to the point P ', and all of them operate using the saturation region as the operating point. From the connection point of the PMOS 162 and NMOS 164, the conventional CMSA shown by the dotted line is used. Output OUTa 'having a level difference sufficiently larger than that of the output OUTa.

As described above, CMSAs 15 and 1
Since the circuits for raising the common source potential, that is, the negative feedback circuits 31 and 32, are provided on the common source side of the driving stage of No. 6, the CMSAs 15 and 16 have both MOS circuits on the load side and the driving stage side. Both of them operate with the saturation region as the operating point, so that the amplification degree of the CMSA is increased and a large output can be stably obtained as compared with the conventional CMSA in which the MOS circuit of the driving stage operates in the linear region. The negative feedback circuit is the negative feedback N shown in FIG.
The structure is not limited to the MOS 31 and 32.
For example, by providing a load circuit in the drains and gate circuits of the negative feedback NMOSs 31 and 32, the potential rising characteristic thereof can be adjusted appropriately.

(Example B) Next, the CMSA according to the present invention
An embodiment B of the voltage type sense amplifier having a two-stage configuration will be described with reference to FIGS. FIG. 4 shows an example of the configuration of the embodiment B, and FIG. 5 is an operation explanatory diagram thereof. In FIG. 4, the same components as those of the voltage-type sense amplifier of the CMSA one-stage configuration described in FIG. The first-stage CMSA and read energizing gate NMOS are CMSA 15a and NMOS 17
a, CMSA 16a, NMOS 18a, and second
The CMSA of the second stage and the lead energizing gate NMOS are CMS
A15b, NMOS17b and CMSA16b, NM
The OS 18b is used for distinction. In Example B, C
Negative feedback NMOS 31 and 32 of MSA 15a and 16a
NMOSs 33 and 34 are provided on the drain side of the. The gate terminal of the NMOS 33 is connected to the drain of the driving stage NMOS 153 of the CMSA 15a.
The gate terminal of 4 is the driving stage NMOS 16 of the CMSA 16a.
3 drains.

The NMOS 33 is a MOS transistor for stabilizing the drain voltages of the MOS 151 and the MOS 153 even when the power supply voltage Vcc fluctuates. Similarly, the NMOS 34 is a MOS transistor for stabilizing the drain voltages of the MOSs 161 and 163 even when the power supply voltage Vcc fluctuates. Therefore, this NM
Even if the OSs 33 and 34 are present, the operations of the CMSAs 15a and 16a and the negative feedback NMOSs 31 and 32 are
This is similar to the case of Example A. The same applies to the gate NMOSs 35 and 36 provided on the common source side of the drive stages of the second-stage CMSAs 15b and 16b, and the operations of the CMSAs 15b and 16b are the same as those of the conventional CMSA 15 described with reference to FIG. And 16 are the same. In this configuration, the operation until the data taken out from the memory cell 13 is amplified by the first-stage CMSAs 15a and 16a is the same as that of the voltage source sense amplifier of the CMSA one-stage configuration according to the embodiment A described in FIG. Is the same.
The output of CMSA 15a and 16a is data * DATAa.
And data DATAa. The output data is amplified by the CMSA 15b and the CMSA 16b in the second stage. The output of this CMSA 15b and 16b is data * D
It is indicated by ATAb and data DATAb, and is further applied to the output amplifier 40 and amplified.

The output amplifying section 40 is a feature of the present invention. In the output amplifying section 40, 41 and 42 are PMOS, which are gates turned off by the read signal READ. Reference numerals 43 and 45 are complementary PMOS and NMOS constituting an output drive stage, both MOSs are connected in series, the source of the PMOS 43 is connected to the positive side of the power supply, and the source of the NMOS 45 is the negative side of the power supply. Connected to. The gates of the PMOS 43 and the NMOS 45 are commonly connected, the PMOS 41 is connected to the common gate, and the output data * D of the CMSA 15b at the second stage is connected.
ATAb is supplied. Data DATAc is output from the common drain connection point of the PMOS 43 and the NMOS 45, and is supplied to the gate of the NMOS 47 forming the output stage. Output from the drain of this output stage NMOS 47 *
OUTb is output. An NMOS 49 is connected between the drain of the NMOS 45 and the power supply, and an equalize signal EQ for controlling the operation start of the output drive stage is applied to the gate of the NMOS 49.

On the other hand, 44 and 46 are complementary PMOS and NMOS constituting an output drive stage, both MOSs are connected in series, the source of the PMOS 44 is connected to the positive side of the power source, and the source of the NMOS 46 is the power source. Connected to the negative electrode side of. The gates of the PMOS 44 and the NMOS 46 are commonly connected, the PMOS 42 is connected to the common gate, and the output data D of the CMSA 16b at the second stage is connected.
ATAb is supplied. Data * DATAc is output from the common drain connection point of the PMOS 44 and the NMOS 46, and is supplied to the gate of the NMOS 48 forming the output stage. The output OUTb is output from the drain of the output stage NMOS 48. An NMOS 50 is connected between the drain of the NMOS 46 and the power supply, and an equalize signal EQ for controlling the operation start of the output drive stage is applied to the gate of the NMOS 50. The output drive stage of this output section 40 is complementary,
Since PMOS 43 and 44 are used on the load side, P
Since the potential drop due to the MOSs 43 and 44 is small, the output data DATAc and data * DATAc can be amplified to near the power supply. FIG. 10 shows the operating characteristics of the output section 40. Since the potential drop by the PMOSs 43 and 44 is small, the complementary PMOS 4 constituting the output driving stage can be used even with a low voltage power supply such as 3V.
3, a sufficient voltage is supplied to the NMOS 45, the PMOS 44, and the NMOS 46, and the data * DATAc and the data DATAc output from both output driving stages can rise to near the power supply voltage as illustrated.

Therefore, the output stage NMOSs 47 and 48
Is high level output data DATAc and data * DA
Sufficiently driven by TAc, high levels of forces * OUTb and OUTb can be obtained as shown. As described above, in the voltage-type sense amplifier having the CMSA two-stage configuration, the input data line of the first-stage CMSA is PM
A circuit for pulling up by the OS and raising the common source potential of the common source side of the driving stage of the first stage CMSA is provided. Therefore, the CMSA is a MOS circuit on both the load side and the driving stage side. Both operate with the saturation region as the operating point, so that even when a low voltage power supply is used, the amplification degree of the first-stage CMSA is increased and a large output can be stably obtained. Furthermore, 2
Since the output drive stage of the output amplifier for amplifying the output of the sense amplifier of the CMSA of the second stage is configured by the complementary PMOS circuit using the PMOS on the load side, even when the low voltage power source is used as the power source, the load side is used. It became possible to generate a sufficiently large drive output by reducing the potential drop of, and it became possible to sufficiently drive the next output stage to obtain a large output. If the circuit for raising the common source potential of the CMSA driving stage of the first stage is configured by a negative feedback MOS circuit, the common source potential of the driving stage during the operation of the CMSA can be raised with a simple circuit configuration. it can.

[0027]

As described above, the CM according to the present invention
In the voltage sense amplifier of the SA1 stage configuration, the input data line of the CMSA is pulled up by the PMOS, so that even if there is a level change in the bit line line of the memory cell to be read under a low voltage power supply, data can be stably output from the memory cell. Can be taken out. Further, since a circuit for raising the common source potential of the CMSA is provided on the common source side of the drive stage, the CMSA operates with the saturation region as the operating point, and the MOS circuit of the drive stage operates in the linear region. Compared with the operating conventional CMSA, the amplification degree of the CMSA is increased and a large output can be stably obtained. Therefore, when a high-voltage power supply is used as the power supply voltage, as well as when a low-voltage power supply is used, the amplification degree is large and the output is large as compared with the conventional voltage sense amplifier having the CMSA one-stage configuration. It can be obtained stably. Further, in this case, if the circuit for raising the common source potential of the drive stage is configured by a negative feedback MOS circuit, it is possible to raise the common source potential of the drive stage during the operation of the CMSA with a simple circuit configuration. is there.

In the voltage source sense amplifier having the two-stage CMSA structure, the input data line of the first-stage CMSA is connected to the PMOS.
Since a circuit for raising the common source potential is provided on the common source side of the driving stage of the CMSA of the first stage, as described above, the bit of the memory cell is Stable data can be taken out even if the level of the line pair changes, and CMS
A operates with the saturation region as the operating point, and even when a low voltage power supply is used, the amplification degree of the first-stage CMSA increases and a large output can be stably obtained. Further, the output drive stage of the output amplification unit that amplifies the output of the second-stage CMSA sense amplifier is connected to the PMOS side on the load side.
Since it is composed of a complementary PMOS circuit that uses, the potential drop on the load side can be reduced and a sufficiently large drive output can be generated even when a low-voltage power supply is used as the power supply. It has become possible to obtain a large output by sufficiently driving. Then, the first stage CMS
If the circuit for raising the common source potential of the A drive stage is composed of a negative feedback type MOS circuit, the CMSA has a simple circuit configuration.
It is possible to raise the common source potential of the driving stage during the operation of.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment A of a voltage-type sense amplifier having a CMSA one-stage configuration according to the present invention.

FIG. 2 is an explanatory diagram of operating characteristics of a voltage type sense amplifier of Example A and a conventional CMSA one-stage configuration.

FIG. 3 is an explanatory diagram of each signal waveform during operation of the voltage-type sense amplifier of Example A and the conventional CMSA one-stage configuration.

FIG. 4 is a configuration diagram of an example B of a voltage source sense amplifier having a CMSA two-stage configuration according to the present invention.

FIG. 5 is an explanatory diagram of signal waveforms during operation of the example B.

FIG. 6 is a configuration diagram of a conventional voltage source sense amplifier having a CMSA one-stage configuration.

FIG. 7 is an explanatory diagram of operating characteristics of a pull-up circuit using NMOS.

FIG. 8 is an explanatory diagram of operating characteristics of a pull-up circuit using a PMOS.

FIG. 9 is a configuration diagram of an example B of a voltage source sense amplifier of a conventional CMSA two-stage configuration.

FIG. 10 is an explanatory diagram of signal waveforms during operation of a conventional voltage-type sense amplifier having a two-stage CMSA configuration.

[Explanation of symbols]

11, 12 Pull-up PMOS 13 Memory cell 14 Decoding Y gate 15, 15a, 15b Current mirror type sense amplifier (CMSA) 16, 16a, 16b Current mirror type sense amplifier (CMSA) 17, 18 Lead energizing NMOS 31 , 32 Negative feedback NMOS 20, 40 Output amplifier 43, 44 Complementary circuit PMOS 45, 46 Complementary circuit NMOS 47, 48 Output stage

Claims (4)

[Claims] 1. A voltage type sense amplifier for amplifying data of a memory cell transmitted from a data line by using a current mirror type sense amplifier, wherein an input data line of the current mirror type sense amplifier is P
A voltage-type sense amplifier, which is pulled up by a MOS transistor and further provided with a circuit for raising the common source potential on the common source side of the drive stage of the current mirror type sense amplifier. 2. A circuit for increasing a common source potential of a driving stage of a current mirror type sense amplifier is a negative feedback type MOS.
The voltage type sense amplifier according to claim 1, which is a circuit. 3. A voltage type sense amplifier for amplifying data of a memory cell transmitted from a data line by using a two-stage current mirror type sense amplifier, wherein the input data line of the first stage current mirror type sense amplifier is P While pulling up with a MOS transistor,
A circuit for increasing the common source potential is provided on the common source side of the drive stage of the first-stage current mirror type sense amplifier, and an output amplification section for amplifying the output of the second-stage current mirror type sense amplifier is provided on the load side. A voltage-type sense amplifier characterized by comprising a complementary MOS circuit using a P-type MOS transistor as described above. 4. The voltage type sense amplifier according to claim 3, wherein the circuit for increasing the common source potential of the driving stage of the first stage current mirror type sense amplifier is a negative feedback type MOS circuit.