JPH08307244A - Semiconductor device - Google Patents

Abstract

PURPOSE: To speed-up the operation of the system employing the semiconductor device by providing a cell including plural input elements validated selectively and respectively according to the logic condition of the circuit so as to selectively connect to each input element thereby reducing the parasitic capacitance. CONSTITUTION: Collectors of input transistors(TRs) Q1, Q2 are connected by a modify cell MC 21 and emitters of the TRs Q1, Q2 are connected by a modify cell MC 22 respectively and the result is registered respectively to a cell library of a gate array. Similarly, the connection path between collectors of TRs Q2, Q3 is registered as a modify cell MC 31 and the connection path between emitters of TRs Q2, Q3 is registered as a modify cell MC 32 respectively, and the connection path between collectors of TRs Q3, Q4 is registered as a modify cell MC 41 and the connection path between emitters of TRs Q3, Q4 is registered as a modify cell MC 42, respectively. The cells MC21-41 and MC 22-42 are arranged selectively in the process of the automatic layout design by a computer. Since the corresponding connection path is formed selectively, OR/ NOR gates with desired input number are formed selectively based on common 4-input OR/NOR gate cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique which is particularly effective when applied to a gate array or the like having a bipolar transistor as a basic element.

[0002]

2. Description of the Related Art There is a semiconductor device such as a gate array using a bipolar transistor (in this specification, a bipolar transistor may be simply referred to as a transistor) as a basic element. The gate array includes a plurality of logic gates having various logic functions, and these are combined to form a predetermined functional unit.

On the other hand, the layout design of gate arrays and the like is being automated by computers, and the types of logic gates that compose gate arrays and the like are limited by standardization, and then registered as cells in a cell library for layout design. To be done.

[0004]

In a gate array or the like having a bipolar transistor as a basic element, a logic gate cell such as an OR (or) gate or a NOR (nor) gate has a predetermined number of parallel couplings according to its logic condition. Input transistors are required. Therefore, considering the usage efficiency of the device, it is preferable to register a plurality of logic gate cells corresponding to each number of inputs in the cell library and selectively arrange them, but consider the labor and management of creating the library. In that case, it is effective to make the cells common and reduce the number of types. For this reason,
In a conventional gate array or the like, for example, a 4-input OR / NOR gate cell that includes four input transistors connected in parallel and can function as an OR gate and a NOR gate is registered, and these input transistors are selectively enabled. 1-input to 4-input OR gate or NOR
The gate is selectively configured. At this time, the collectors and emitters of the four input transistors are steadily connected regardless of their validity, but in the invalid input transistors, the corresponding modify cells are arranged so that The base and the emitter are selectively short-circuited. As a result, the disabled input transistors are forced into the cutoff state, which allows the logic gate cell to perform the desired logic function.

However, it has become clear by the present inventors that the following problems will occur in the conventional gate array and the like as the speed of the gate array and the like and the system including the same increases. That is, in the conventional gate array or the like, as described above, the collector and the emitter of the input transistor forming the logic gate cell are constantly connected regardless of their effectiveness, and the corresponding internal node has a plurality of connected nodes. A relatively large parasitic capacitance including the collector capacitance and the emitter capacitance of the input transistor and the wiring capacitance is fixedly coupled. As a result, the level change of each internal node becomes slower, the operation of the logic gate cell becomes slower, and the speeding up of the gate array and the system including it is restricted.

An object of the present invention is to speed up the operation of a logic gate cell in accordance with the number of inputs, and to speed up the operation of a system including the gate array, etc., which mounts the logic gate cell, and the like.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a gate array or the like provided with a logic gate cell including a plurality of input transistors that are provided in parallel and are selectively enabled according to the logic condition of the circuit, the connection path to the collector and the emitter of each input transistor is used as a modification cell. Register them in the library and selectively place these modifier cells when the corresponding input transistors are enabled.
Selective connection to the collector and emitter of the input transistor.

[0009]

According to the above-mentioned means, unnecessary input transistors can be selectively separated from the corresponding internal nodes of the logic gate cell to reduce parasitic capacitance such as collector capacitance and emitter capacitance coupled to these internal nodes. it can. As a result, the operation of the logic gate cell can be accelerated in accordance with the number of inputs, and the operation of the gate array or the like having the logic gate cell and the system including the same can be accelerated.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a 4-input OR to which the present invention is applied.
A circuit diagram of an embodiment for explaining the logical configuration of the NOR gate cell (logic gate cell) is shown. Also,
FIG. 2 shows a connection diagram of the first embodiment for explaining the layout image of the 4-input OR / NOR gate cell of FIG. 1, and FIGS. 3 and 4 show the second and third implementations thereof. Each example connection diagram is shown. Based on these figures, the logical configuration and operation of the 4-input OR / NOR gate cell of this embodiment, the layout method, and its features will be described. Although not particularly limited, the 4-input OR / NOR gate cell of this embodiment is mounted in a gate array having a bipolar transistor as a basic element together with a large number of similar logic gate cells not shown. Each of the circuit elements shown in FIGS. 1 to 4 is formed on one semiconductor substrate such as single crystal silicon by a well-known bipolar integrated circuit technique together with other circuit elements (not shown) forming a gate array. . In the circuit diagrams below, the illustrated transistors are all NPN bipolar transistors.

Referring to FIG. 1, the 4-input OR of this embodiment is
The NOR gate cell includes four input elements provided in parallel, that is, input transistors Q1 to Q4, and a transistor Q provided in these input transistors in a differential form.
Including 5 and. Of these, the commonly coupled collectors of the input transistors Q1 to Q4, that is, the internal node n1 is coupled to the ground potential GND via the resistor R1, and the collector of the transistor Q5 is coupled to the ground potential GND via the resistor R2. . Also, the transistors Q1 to Q4 and Q
5 co-coupled emitters or internal node n2
A power supply voltage VE is supplied via a current source composed of a transistor Q6 which receives a predetermined constant voltage VCS to its base and a resistor R3.
Bound to E. Further, the input transistors Q1 to Q4
Of the gate array are supplied with corresponding input signals I1 to I4 from a pre-stage circuit (not shown) of the gate array, and the base of the transistor Q5 is supplied with a predetermined reference voltage VBB from an internal voltage generating circuit (not shown) of the gate array. It The power supply voltage VEE is set to a negative potential such as -4V, although not particularly limited.

The potential at the collector of the transistor Q5 becomes the non-inverted output signal OT of the circuit after passing through the output emitter follower circuit composed of the transistor Q7 and the resistor R4, and the internal node n1 or the input transistors Q1 to Q4.
The potential at the commonly coupled collectors of the two becomes the inverted output signal OB of the circuit after passing through the output emitter follower circuit formed of the transistor Q8 and the resistor R5. The non-inverted output signal OT and the inverted output signal OB are supplied to a post-stage circuit (not shown) of the gate array. The resistors R4 and R that form the above two output emitter follower circuits.
A predetermined output power supply voltage VTT such as −2V is supplied to the other of the five.

As a result, the input transistors Q1 to Q4
Are turned off selectively when the corresponding input signals I1 to I4 are set to a low level lower than the reference voltage VBB, and the corresponding input signals I1 to I4 are changed to the reference voltage VBB.
When it is set to a higher level, it is selectively turned on. The transistor Q5 differentially coupled to these input transistors is the input transistors Q1 to Q1.
When all Q4 are turned off, they are selectively turned on, and when any of the input transistors Q1 to Q4 are turned on, they are selectively turned off.

When all the input transistors Q1 to Q4 are turned off and the transistor Q5 is turned on,
The collector potential of the transistor Q5 is set to a predetermined low level determined by the resistance value of the resistor R2 and the current value of the current source composed of the transistor Q6 and the resistor R3, and the 4-input O
The non-inverted output signal OT of the R / NOR gate cell is set to a predetermined low level that is lower than the low level of the collector potential of the transistor Q5 by the base-emitter voltage of the transistor Q7. At this time, the potential at the internal node n1, that is, the commonly coupled collectors of the input transistors Q1 to Q4 is set to a high level like the ground potential GND,
The inverted output signal OB of the 4-input OR / NOR gate cell is
The internal node n1 is set to the high level, that is, the high level lower than the ground potential GND by the base-emitter voltage of the transistor Q8.

On the other hand, when any of the input transistors Q1 to Q4 is turned on and the transistor Q5 is turned off, the collector potential of the transistor Q5 is set to a high level like the ground potential GND, and the 4-input OR. NO
The non-inverted output signal OT of the R gate cell is transferred to the transistor Q
The collector potential of 5 is set to a high level, that is, the ground potential GND, which is lower than the ground potential GND by the base-emitter voltage of the transistor Q7. At this time, the potential at the internal node n1, that is, the common-coupled collectors of the input transistors Q1 to Q4 is set to a predetermined low level determined by the resistance value of the resistor R1 and the current value of the current source, and 4-input O
The inverted output signal OB of the R / NOR gate cell is set to a predetermined low level lower than the low level at the internal node n1 by the base-emitter voltage of the transistor Q8.

As a result, the non-inverted output signal OT of the 4-input OR / NOR gate cell becomes an OR (logical sum) signal of the input signals I1 to I4 of OT = I1 + I2 + I3 + I4,
The inverted output signal OB is its inverted signal, that is, the input signal I1.
~ It becomes a NOR signal of I4.

In this embodiment, an automatic layout design system by a computer is adopted for the layout design of the gate array, and various logic gates of the gate array are cells represented by the 4-input OR / NOR gate cell of FIG. It is formed based on various standard common cells registered in the library. Further, the input transistors Q1 to Q4 forming the 4-input OR / NOR gate cell of FIG. 1 are selectively made effective according to the logical condition desired in the circuit,
The 4-input OR / NOR gate cell selectively functions as a 1-input to 4-input OR / NOR gate depending on the effective number of these input transistors. As a result, the number of types of logic gate cells to be registered in the cell library is reduced, and the management thereof is made efficient. In addition, 1-input OR ・ N
It goes without saying that the OR gate functions as a non-inverting or inverting buffer.

On the other hand, in the 4-input OR / NOR gate cell of this embodiment, as shown in FIG. 2, the input transistor Q1 is constantly enabled and the other input transistors Q1 and Q2 are turned on.
2 to Q4 are selectively made effective by selectively connecting their collector and the collector of the input transistor Q1 and their emitter and the emitter of the input transistor Q1, respectively. Of these, the connection paths between the collectors and the emitters of the input transistors Q1 and Q2 are registered as the modify cells MC21 and MC22 in the cell library of the gate array, respectively. Similarly, the connection paths between the collectors and the emitters of the input transistors Q2 and Q3 are registered as the modify cells MC31 and MC32, respectively, and
The connection paths between the collectors of 3 and Q4 and between the emitters are
The modification cells MC41 and MC42 are respectively registered. These modification cells MC21 to MC
41 and MC22 to MC42 are, for example, corresponding input terminals TI in the process of automatic layout design by a computer.
In response to the signal names defined in 1 to TI4, they are selectively arranged. Accordingly, since the corresponding connection path can be selectively formed, it is possible to selectively configure an OR / NOR gate having a desired number of inputs based on the common 4-input OR / NOR gate cell.

The modification cells MC21 to MC4
1 and MC22 to MC42 are both formed by the first metal wiring layer. The power supply voltage supply terminal TPW1 to which the upper terminals of the resistors R1 and R2 and the collectors of the transistors Q7 and Q8 are connected is connected to the supply point of the ground potential GND through a predetermined metal wiring layer and is connected to the resistor R3 or the resistor R4. Power supply voltage supply terminals TPW2 and TPW3 to which the lower terminals of R5 and R5 are connected are respectively connected to the supply points of the power supply voltage VEE or the output power supply voltage VTT through a predetermined metal wiring layer. Furthermore, the input terminals TI1 to T
I4 is input signals I1 to I4 via a predetermined metal wiring layer.
, And the non-inverting output terminal TOT and the inverting output terminal TOB are respectively coupled to the receiving points of the non-inverting output signal OT and the inverting output signal OB via a predetermined metal wiring layer. The reference voltage supply terminal TVBB and the constant voltage supply terminal TVCS are respectively coupled to the supply points of the reference voltage VBB or the constant voltage VCS via a predetermined metal wiring layer.

In the conventional 4-input OR / NOR gate cell, the collectors and emitters of the input transistors Q1 to Q4 are constantly connected regardless of their effectiveness. Also, its base is selectively coupled to its emitter by fixing it and disabling the corresponding modify cell, fixing it to the off state. Therefore, the internal node is always coupled with the parasitic capacitance including the collector capacitance and the emitter capacitance of the four input transistors Q1 to Q4, the wiring capacitance, and the like.
The operation of the logic gate composed of the input OR / NOR gate cell becomes slow. As a result, the operation of the gate array having the 4-input OR / NOR gate cell becomes slow, and there is a problem that the speedup of the system including the gate array is restricted.

However, in the case of this embodiment, the connection paths for the collectors and emitters of the input transistors Q2 to Q4 are modified cells MC21 to MC41 and MC2.
2 to MC42, and these modified cells are selectively arranged as needed, so that each OR / N
Only the collectors and emitters of the input transistors that are enabled are connected to the internal nodes n1 and n2 of the OR gate. In other words, the internal nodes n1 and n
No parasitic capacitance such as collector capacitance, emitter capacitance and wiring capacitance of the input transistor, which is invalidated, is coupled to 2. In particular, the 4-input OR / NOR gate cell has one input or three inputs having a small number of inputs. OR
When used as a NOR gate, the level change of signals at the internal nodes n1 and n2 is accelerated, and
The operation of the NOR gate is accelerated. As a result, the operation of the gate array having the 4-input OR / NOR gate cell is accelerated, and the operation of the system including the same is accelerated.

By the way, in the case of the embodiment of FIG. 2, the modification cells MC31, MC32 and MC41, MC4 are used.
2 is arranged by modifying cells MC21, MC22 or MC2 provided on the side of the internal nodes n1 and n2.
1, MC22 and MC31, MC32 have already been placed on the condition that they have already been placed, and such a placement order condition places a constraint on the operator in charge of the automatic placement design of the gate array. To deal with this, in the embodiment of FIG. 3, the connection paths between the collectors and the emitters of the input transistors Q1 and Q2 are registered as the modify cells MC21 and MC22, respectively, as in the embodiment of FIG. The modification cell MC31 is a connection path for collectively connecting the collectors or emitters of the transistors Q1, Q2 and Q3.
And MC32 respectively, and the connection paths for collectively connecting the collectors or emitters of the input transistors Q1, Q2, Q3 and Q4 are modified cells MC.
41 and MC42, respectively. These modification cells MC21 to MC41 and MC22
The MCs 42 can be arbitrarily arranged without paying attention to the arrangement order, and thus the constraint for the operator can be solved.

On the other hand, the value of the parasitic capacitance coupled to the internal nodes n1 and n2 of the 4-input OR / NOR gate cell is the internal node n1 to which the collectors of the input transistors Q1 to Q4 are commonly coupled and the internal to which the emitter is commonly coupled. Its value is different from that of the node n2. When the influence of the parasitic capacitance of the internal node n1 on the propagation delay time of the gate cell is expected to be relatively small, as shown in FIG. 4, the collector sides of the input transistors Q1 to Q4 are constantly connected and Only the connection path on the emitter side is modified cell M
A method of selectively forming C22 to MC42 can be adopted.

FIG. 5 is a connection diagram of an embodiment for explaining a layout image of a 4 × 4 input series gate cell to which the present invention is applied. Since this embodiment basically follows the embodiment of FIG. 3 or includes a portion similar to this, the description of the portion that can be inferred from FIG. 3 will be omitted.

In FIG. 5, the 4 × 4 input series gate cell of this embodiment includes four input transistors QA to QD connected in parallel and a transistor QJ differentially connected to these input transistors. Of these, the bases of the input transistors QA to QD, that is, the input terminal TIA
Input signals IA to ID (not shown) are respectively supplied to -TID, and a predetermined reference voltage VBB1 is supplied to the base of the transistor QJ, that is, the reference voltage supply terminal TVB1. The collector potential of the transistor QJ is output from the non-inverting output terminal TOT as the non-inverting output signal OT after passing through the output emitter follower circuit including the transistor QN and the resistor RF. Further, the potential at the internal node n3, that is, the common-coupled collectors of the input transistors QA to QD passes through the output emitter follower circuit including the transistor QO and the resistor RG, and then the inverted output signal OB.
Is output from the inverted output terminal TOB.

The 4 × 4 input series gate cell is further provided with a transistor QI whose collector is coupled to the internal node n4, that is to the commonly coupled emitters of transistors QA-QD and QJ, and to this transistor QI in a differential configuration. Transistor QK, and four input transistors QE to QH provided in parallel between internal node n5 and internal node n6, that is, the base of transistor QI. Of these, the internal node n5, that is, the commonly coupled collectors of the input transistors QE to QH are coupled to the power supply voltage supply terminal TPW1 via the resistor RB, and the internal node n6, that is, the input transistors QE to QH.
The commonly coupled emitters of H are connected to the power supply voltage supply terminal TP via the current source composed of the transistor QL and the resistor RD.
Bound to W2. The input signals IE to IH (not shown) are supplied to the bases of the input transistors QE to QH, that is, the input terminals TIE to TIH, respectively. The collector of the transistor QK is coupled to the collector of the transistor QJ in common, and its base, that is, the reference voltage supply terminal T
A predetermined reference voltage VBB2 is supplied to VB2. Between the commonly coupled emitters of the transistors QI and QK in the differential form and the power supply voltage supply terminal TPW2,
A current source composed of a transistor QM and a resistor RE is provided. The reference voltage VBB2 is lower than the reference voltage VBB1 by the base-emitter voltage of the transistor QI.

As a result, the input transistors QA to QD
Are selectively turned on when the corresponding input signals IA to ID are set to a high level higher than the reference voltage VBB1, and the input transistors QE to QH are transistors whose corresponding input signals IE to IH are higher than the reference voltage VBB2. When it is set to a high level higher than the base emitter voltage of QI, it is selectively turned on. Therefore, the non-inverting output terminal T of the 4 × 4 input series gate cell
The non-inverted output signal OT at the OT is the input signals IA-I.
Any one of D is set to the high level and the input signals IE to I
When any one of H is set to the high level, it is selectively set to the high level, and when all the input signals IE to IH are set to the low level, or when the input signals IA to ID are all set to the low level and the input signals IE to IH are set to the low level. When any one is set to high level, it is selectively set to low level. In addition, the inverted output terminal TO of the 4x4 input series gate cell
The inverted output signal OB in B is selectively set to the high level when the input signals IA to ID are all set to the low level or the input signals IE to IH are set to the low level, and one of the input signals IA to ID is set to the high level. And when any of the input signals IE to IH is set to the high level, it is selectively set to the low level.

In this embodiment, the input transistor Q
A and QE are constantly enabled and the input transistor Q
B-QD and QF-QH are corresponding modification cells MCB1 and MCB2, MCC1 and MCC2, MCD1 and MCD in the process of automatic layout design of the gate array.
2 or MCF1 and MCF2, MCG1 and MCG
2, MCH1 and MCH2 are selectively enabled. As a result, the internal nodes n3 to n6 are not coupled with parasitic capacitances such as collector capacitances, emitter capacitances, or wiring capacitances of the input transistors that are invalidated, and thus the configuration is based on the 4 × 4 input series gate cell. The operation of various logic gates to be performed is accelerated. According to the simulation by the inventors of the present application, the operation speed of the series gate is the same as that of the normal OR.
Compared to the NOR gate, the modification cells MCB2 and MCC are more susceptible to the parasitic capacitance coupled to the internal node n4, that is, the collector of the transistor QI.
2 and MCD2 are selectively arranged, and the speeding-up effect is extremely large.

The functions and effects obtained from the above embodiments are as follows. That is, (1) In a gate array or the like having a logic gate cell including a plurality of input transistors that are selectively enabled according to a logic condition of a circuit provided in a parallel form, a connection path to a collector and an emitter of each input transistor is modified. By registering these modified cells as cells in the cell library, selectively arranging these modified cells when the corresponding input transistors are enabled, and connecting the collector and emitter of the input transistors selectively, unnecessary input transistors Is selectively disconnected from the corresponding internal node of the logic gate cell, and the parasitic capacitance coupled to each internal node can be reduced. (2) According to the above item (1), the operation of the logic gate cell can be speeded up in accordance with the number of inputs. (3) According to the above item (2), it is possible to obtain an effect that the operation of a gate array including a logic gate cell and a system including the same can be accelerated.

The invention made by the present inventor has been specifically described above based on the embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 2, MC21 to MC41 and MC2
Any one of the 2 to MC 42 may be constantly in the connected state. Further, in FIG. 4, the input transistor Q1
Alternatively, the emitter-side connection path of Q4 to Q4 may be constantly connected, and the collector-side connection path may be selectively formed by the modify cell instead. In FIG. 5, the modification cells MCF1 to MCH1 and MCF2
The MCH2 and the resistor RB may not be provided. 1 to 5, each logic gate cell can have various logic functions, and the number of inputs, that is, the number of input transistors provided in parallel is arbitrary. In addition, the current source and output emitter follower circuit of each logic gate cell is configured by a plurality of transistors or resistors that are connected in parallel, and these transistors or resistors are selectively enabled by the corresponding modify cells to output the current source and output. The current class of the emitter follower circuit may be selectively switched. Furthermore, various embodiments can be adopted for the specific circuit configuration of each logic gate cell, the polarity and absolute value of the power supply voltage, the conductivity type of the transistor, and the like.

In the above description, the invention made by the present inventor was mainly applied to a gate array having a bipolar transistor as a basic element, which is the field of application of the invention, but the invention is not limited thereto. Instead, it can be applied to, for example, a gate array having various elements such as MOSFET (metal oxide semiconductor field effect transistor) as a basic element and various logic integrated circuit devices.
INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor device including at least a plurality of input elements which are provided in parallel and are selectively effective, and a device or system including the same.

[0032]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a gate array or the like provided with a logic gate cell including a plurality of input transistors that are provided in parallel and are selectively enabled according to the logic condition of the circuit, the connection path to the collector and the emitter of each input transistor is used as a modification cell. By registering these modification cells in the library and selectively arranging these modification cells when the corresponding input transistors are enabled, and connecting the collector and emitter of the input transistors selectively, unnecessary input transistors are made into logic gate cells. It is possible to reduce the parasitic capacitance such as collector capacitance and emitter capacitance coupled to these internal nodes by selectively disconnecting them from the corresponding internal nodes. As a result, the operation of the logic gate cell can be accelerated in accordance with the number of inputs, and the operation of the gate array or the like having the logic gate cell and the system including the same can be accelerated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment for explaining a logical configuration of a 4-input OR / NOR gate cell to which the invention is applied.

FIG. 2 is a connection diagram showing a first embodiment for explaining a layout image of the 4-input OR / NOR gate cell of FIG.

FIG. 3 is a connection diagram showing a second embodiment for explaining a layout image of the 4-input OR / NOR gate cell of FIG.

FIG. 4 is a connection diagram showing a third embodiment for explaining the layout image of the 4-input OR / NOR gate cell of FIG.

FIG. 5 is a connection diagram showing an embodiment for explaining a layout image of a 4 × 4 input series gate cell to which the present invention is applied.

[Explanation of symbols]

Q1 to Q8, QA to QO ... NPN bipolar transistor, R1 to R5, RA to RG ... Resistance, I1 to I4
... Input signal, OT ... Non-inverted output signal, OB ...
Inverted output signal, VCS ... constant voltage, VBB ... reference voltage, GND ... ground potential, VEE ... power supply voltage, VTT ... output power supply voltage. TI1 to TI4, TI
A to TIH ... input terminal, TOT ... non-inverting output terminal, TOB ... inverting output terminal, TVCS ... constant voltage supply terminal, TVBB, TVB1 to TVB2 ... reference voltage supply terminal, TPW1 to TPW3 ... Power supply voltage supply terminal, MC21 to MC41, MC22 to MC42, MCB
1-MCH1, MCB2-MCH2 ... Modify cells.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Yuko Ito 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Inventor Satoru Isomura 2326 Imai, Ome City, Tokyo Hitachi Device Development Center (72) Inventor Atsushi Shimizu 2326 Imai, Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Tetsuya Maruyama 2326, Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center

Claims (3)

[Claims] 1. A cell comprising a plurality of input elements, each of which is selectively enabled according to a logic condition of a circuit, and a connection to each input element is selectively provided on the condition that it is enabled. A semiconductor device characterized by being used. 2. The connection path to the input element is registered in the cell library as a modified cell, and the effective connection to the input element is selected by arranging a corresponding modified cell. The semiconductor device according to claim 1, wherein the semiconductor device is performed on a semiconductor device. 3. The semiconductor device is a gate array having a bipolar transistor as a basic element, and the cell is a logic gate cell including a plurality of input transistors arranged in parallel as the input element, and the modification cell. 3. The semiconductor device according to claim 1 or 2, wherein is for selectively connecting between collectors or between emitters of the input transistors.