JPH01127979A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To monitor an internal state of an ECL circuit by providing a transistor provided with a constant-current source, a transistor connected to a base of an output transistor, a unidirectional element and a test terminal. CONSTITUTION:As for a transistor Q5, a base is coupled to an emitter of an emitter follower output transistor Q3 in an ECL circuit, a power supply voltage V(-) is supplied to a collector, and a constant-current source I0 is provided on an emitter through a resistance R4. Also, as for a transistor Q7, a voltage across the resistance R4 is supplied to a base and an emitter, and its collector is coupled to a base of the transistor Q3 through a resistance R3. As for a unidirectional element, an anode side is coupled to a connecting point of the resistance R4 and the current source I0, and a cathode side is coupled to the base of the transistor Q5. A test use terminal VT is coupled to the connection of the resistance R4 and the current source I0. By this constitution, a monitor output signal is obtained, and by an operation of the unidirectional element and the transistor Q7, the internal state can be set arbitrarily to a high level or a low level.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular, to an ECL
The present invention relates to a technique that is effective for use in testing a semiconductor integrated circuit device including an emitter-coupled logic (emitter-coupled logic) circuit.

[Conventional technology]

In an ECL circuit, an emitter follower circuit may be used to monitor the internal logic operation of a semiconductor integrated circuit. Regarding the EC15 circuit,
For example, there is "Semiconductor Circuit Manual" published by Ohmsha on November 20, 1975, pages 236 to 238.

[Problem that the invention seeks to solve]

By providing an emitter follower circuit as described above at any location in the ECL circuit, the internal state of the ECL circuit can be monitored. However, since the internal state cannot be specified, creating input patterns for complex logic circuits becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semi-quartet integrated circuit device that is equipped with a test function that allows monitoring of the internal state in the ECLu path and designation of logic.

The above and other objects and novel features of the present invention will become apparent from the description of the Zero BAt (lr book) and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a transistor Q5 is provided whose base is coupled to the emitter of the emitter follower output transistor Q3 in the ECLu path, whose collector is supplied with an operating voltage, and whose emitter is connected to a constant current source via a resistor R4. The voltage across R4 is supplied to the base and emitter of a transistor Q7 whose collector is coupled to the base of the output transistor Q3 via the resistor R3, and the voltage across the transistor Q5 is supplied from the connection point between the resistor R4 and the constant current source. A unidirectional element that allows current to flow toward the base is provided, and a test terminal is connected to the connection between the resistor R4 and the constant current source.

[For production]

According to the above means, a monitor output signal is obtained by the transistor Q5 which substantially constitutes an emitter follower circuit, and when a high level or a low level is supplied to the test terminal, the unidirectional element and the transistor Q7 operate accordingly. The internal state can be specified arbitrarily.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

Transistors Q1 and G2 are placed in a differential configuration.

A constant current source 1o is provided at the common emitter of transistors Q1 and G2. The collectors of the transistors Q1 and G2 are provided with load resistors R1 and R2, respectively. Note that when logic is used, one or more transistors are provided in parallel with the transistor Q1,
An input signal is supplied to each base.

In this embodiment, the collector outputs of the transistors Ql and G2 are transmitted to the next stage logic gate circuits C1, G2, etc. via an emitter follower output circuit consisting of a transistor Q3 and a constant current source Io, and a transistor Q4 and a constant current source 1o. It is transmitted as input signals Do, DO. Note that a constant current source IO and an emitter follower output transistor Q3 . G
The constant current source provided in the emitter of 4 ■0 is shown with the same circuit symbol, but it does not mean that it flows the same constant current, but rather it is a constant current source in the boat fishing sense. It refers to Therefore, the above constant current source IOt current values may be different or may be the same.

In this embodiment, in order to enable monitoring of the output signal of the ECLu path in units as described above and setting its level,
The following circuit elements are added.

The emitter of the emitter follower output transistor Q3 is
Supplied to the base of transistor Q5.

The collector of this transistor Q5 is coupled to the power supply voltage Vcc, and its emitter is connected to a constant current source IO via a resistor R4. The voltage across the resistor R4 is supplied between the base and emitter of the transistor Q7. The collector of this transistor Q7 is coupled to the base of the output transistor Q3 via a resistor R3. A diode-shaped transistor Q6 is provided between the connection point between the resistor R4 and the constant current source Io and the base of the transistor Q5. The commonly connected base and collector of the transistor Q6 are connected as an anode to the connection point between the resistor R4 and the constant current source Io, and the emitter is connected as a cathode to the base of the transistor Q5. A test terminal VT is connected to the connection point between the resistor R4 and the constant current source io.

The terminal VT may be an external terminal of a semiconductor integrated circuit device, or may be a test pad used for blowing an integrated circuit on a semiconductor wafer.

The operation of this embodiment circuit will now be described.

When the terminal VT is used as a monitor terminal, the transistor Q5 operates as an emitter follower output transistor and outputs a signal corresponding to the output signal Do of the transistor Q3 from the terminal VT. Accordingly, for example, if the output signal DO of the transistor Q3 is at a high level, the terminal VT is set at a high level, and when it is at a low level, the terminal VT is set at a low level.

When the output signal DO is at a high level, if a high level is supplied from the terminal VT, the same high level is supplied between the base and emitter of the transistor Q5, so that the transistor Q5 is turned off and the output signal is output.

is left at a high level. In the above state, when the terminal VT is set to a low level, a relatively large current flows through the transistor Q5. This current increases the voltage drop across resistor R4, turning transistor Q7 on. Due to the on state of this transistor Q7, current flows through the load resistor R2 of the ECL via the resistor R3,
Transistor Q3 regardless of the input signal DI of the ECL circuit.
In order to lower the base potential of the transistor to a low level, its output signal DO changes from a high level as described above to a low level. At this time, the base potential of transistor Q3 is
This is determined by the voltage division between the resistors R2 and R3, and is set to a voltage such that the level of the output signal Do, which is changed to low level, does not cut off the transistor Q5.

When the output signal Do is at a low level, when a low level is supplied from the terminal VT, the same low level is supplied between the base and emitter of the transistor Q5, so that the transistor Q5 is turned off and the output signal DO remains at the low level.

In the above state, when the terminal VT is set to a high level, the transistors Q5 and Q7 are turned off as a result of being reverse biased between their bases and emitters. and,
The high level supplied from the terminal VT is transmitted to the output signal DO through the diode-type transistor Q6, making it a high level. At this time, the output transistor Q3 is also turned off because its base and emitter are reverse biased. Therefore, the current of the constant current source (20) provided at the emitter of the transistor Q3 flows from the terminal VT through the diode-type transistor Q6.

In this way, the terminal VT has the unit ECL as shown above.
In addition to being used as a circuit output monitor terminal, it can also be used to arbitrarily set the output signal Do. This makes it possible to directly supply an input signal for functional testing of the subsequent logic gate circuit 01, etc. that receives this output signal DO, thereby making it possible to shorten the testing time.

Although the above-mentioned test circuit is provided at the emitter output of the emitter follower output transistor Q3, etc., its output impedance is low and does not impair its high-speed operation. Also, transistor Q3
Since the resistor R3 will be connected to the base of the resistor R3, the speed will be slowed down by the parasitic capacitance. but,
The parasitic capacitance in this resistor R5 is compared with the substrate capacitance of the transistor Q2, the base-collector capacitance, and the base-emitter capacitance of the transistor Q3.
It will be small enough. Therefore, the resistor R5 as above
Even if the test circuit is added, the operating speed of the ECL circuit will not be substantially slowed down.As a result, even if the above test circuit is added, there will be almost no delay in the circuit operation on the ECL circuit side. It is no exaggeration to say that.

The effects obtained from the above examples are as follows. That is, (1) A transistor Q5 whose base is coupled to the emitter of an emitter follower output transistor Q3 in the ECL circuit, an operating voltage is supplied to its collector, and a constant current source is connected to its emitter via a resistor R4. The voltage across the resistor R4 is supplied to the base and emitter of a transistor Q7 whose collector is coupled to the base of the output transistor Q3 via the resistor R3, and from the connection point between the resistor R4 and the constant current source. A unidirectional element is provided that allows current to flow toward the base of the transistor Q5, and a test terminal is connected to the connection between the resistor R4 and the constant current source. In this configuration, a monitor output signal is obtained by the transistor Q5, which essentially constitutes an emitter follower circuit, and when a high level or low level G is supplied to the test terminal, the unidirectional element and the transistor Q7 operate accordingly. This provides the advantage that the internal state can be arbitrarily set to a high level or a low level.

(2) With (1) above, it becomes possible to monitor the signals of the ECL internal circuit and specify the logic level arbitrarily, making it easier to create test patterns for circuit function tests and shortening the testing time. The effect is that it becomes possible.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. For example, transistor Q
6 may be replaced with a diode. Furthermore, the semiconductor integrated circuit device may be for development purposes.
Further, the configuration of the constant current source IO may be a constant current circuit such as a transistor receiving a constant voltage, or a resistor having a relatively large resistance value. In place of , one provided on the emitter output side of transistor Q4, or
It may also be provided in both emitters of No. 4.

In FIG. 1, gate circuit G1. G2 includes, in addition to the ECL gate circuit, two sets of differential circuits that are switched by a signal in phase with the input signal DI and a signal in reverse phase, and whose outputs are cross-coupled, and the two sets of differential transistors. An analog multiplication circuit may be constructed by supplying the collector output of a differential transistor that receives another input signal to the emitter of the transistor.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, its base is coupled to the emitter of the emitter follower output transistor Q3 in the ECL circuit,
A transistor Q5 whose collector is supplied with an operating voltage and whose emitter is connected to a constant current source via a resistor R4.
is provided, and supplies the voltage across the resistor R4 to the base and emitter of a transistor Q7 whose collector is coupled to the base of the output transistor Q3 via the resistor R3, and connects the resistor R4 and the constant current source to the connection point. A unidirectional element is provided that causes current to flow from the transistor Q5 toward the base of the transistor Q5, and a test terminal is connected to the connection between the resistor R4 and the constant current source. In this configuration, a monitor output signal is obtained by the transistor Q5, which essentially constitutes an emitter follower circuit, and when a high level or a low level is supplied to the test terminal, the unidirectional element and the transistor Q7 operate accordingly. The internal state can be arbitrarily set to high or low level.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Claims (1)

[Claims] 1. The base of the emitter follower output transistor Q3 in the ECL circuit is coupled to the emitter, the collector is supplied with an operating voltage, and the emitter is provided with a constant current source via a resistor R4. a transistor Q7 whose base and emitter are supplied with the voltage across the resistor R4, and whose collector is coupled to the base of the output transistor Q3 via the resistor R3;
A test in which the anode side is coupled to the connection point between the resistor R4 and the constant current source, and the unidirectional element whose cathode side is coupled to the base of the transistor Q5, and the connection between the resistor R4 and the constant current source. 1. A semiconductor integrated circuit device comprising a terminal for 2. The semiconductor integrated circuit device according to claim 1, wherein the unidirectional element is a transistor connected in a diode configuration.