JPH08306817A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH08306817A
JPH08306817A JP10635995A JP10635995A JPH08306817A JP H08306817 A JPH08306817 A JP H08306817A JP 10635995 A JP10635995 A JP 10635995A JP 10635995 A JP10635995 A JP 10635995A JP H08306817 A JPH08306817 A JP H08306817A
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor device
hole
wiring pattern
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10635995A
Other languages
Japanese (ja)
Other versions
JP3553195B2 (en
Inventor
Tadashi Yamaguchi
忠士 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP10635995A priority Critical patent/JP3553195B2/en
Publication of JPH08306817A publication Critical patent/JPH08306817A/en
Application granted granted Critical
Publication of JP3553195B2 publication Critical patent/JP3553195B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: To facilitate machining of a thin type semiconductor device and reduce the cost. CONSTITUTION: A wiring pattern 11 of a semiconductor device is formed on the surface of a P.W.B(printed wiring board) 10, and a penetrating hole 12 and a penetrating hole for resin flow are formed on the center and the end part of the P.W.B 10. The penetrating hole 12 exposes a pad of a mounted semiconductor element 20 when viewed from the surface of the P.W.B 10. The semiconductor element 20 is fixed on the back of the P.W.B 10 so as to expose the pad which is connected with the wiring pattern 11 via a wire passing the penetrating hole 12. After the semiconductor element 20 is mounted, resin sealing is performed, and both surfaces of the semiconductor element 20 are sealed with resin 30 flowing in the penetrating hole for resin flow.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、薄型のICメモリカー
ドモジュール等の薄型半導体装置として用いられ、プリ
ント配線板(Printed Wiring Boad ;以下、P.W.B
という)に半導体素子を表面実装型で搭載した半導体装
置とその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used as a thin semiconductor device such as a thin IC memory card module, and is used in a printed wiring board (Printed Wiring Board;
The above) relates to a semiconductor device in which a semiconductor element is mounted by surface mounting and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来、このような分野の技術としては、
例えば、次のような文献に示されるものがあった。 文献;特開昭55−56647号公報 半導体集積回路のうちで腕時計やカメラやICカード等
に使用されるものには、厚さが0.5〜2mm程度の極め
て薄型のパッケージ構造が、要求されている。従来の半
導体装置は、リードフレームの所定位置に半導体素子を
搭載して、樹脂封止を行うか、または、上記文献に示す
ように、ガラスエポキシ等からなるP.W.Bに半導体
集積回路等の半導体素子を直接搭載し、その半導体素子
をP.W.B上の金属配線にワイヤで接続した後、エポ
キシ樹脂等で封止している。即ち、上記文献には、チッ
プ・オン・ボードのパッケージが示されている。P.
W.Bの表面には、外部に対する端子となるパターンが
形成されており、該パターンがそのP.W.Bの裏面に
形成されたボンディング用パターンにスルーホールを介
して接続されている。半導体素子はP.W.Bの裏面に
接着材を用いて固定され、その半導体素子の下面、つま
り、P.W.Bに接していない面に形成されたパッド
が、P.W.Bのボンディング用パターンにワイヤで接
続される。半導体素子のパッドが周囲のボンディング用
パターンに接続された後、該半導体素子が樹脂によって
封止成形され、半導体装置が完成する。
2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one shown in the following documents. Reference: Japanese Patent Laid-Open No. 55-56647. Among semiconductor integrated circuits used for wrist watches, cameras, IC cards, etc., an extremely thin package structure having a thickness of about 0.5 to 2 mm is required. ing. In the conventional semiconductor device, a semiconductor element is mounted at a predetermined position of a lead frame and resin sealing is performed, or as shown in the above-mentioned document, a P.P. W. A semiconductor element such as a semiconductor integrated circuit is directly mounted on the B.B. W. After connecting to the metal wiring on B with a wire, it is sealed with epoxy resin or the like. That is, a chip-on-board package is shown in the above document. P.
W. A pattern serving as a terminal to the outside is formed on the surface of B. W. It is connected to the bonding pattern formed on the back surface of B through a through hole. The semiconductor element is P.P. W. The back surface of the semiconductor element is fixed to the bottom surface of the semiconductor element by using an adhesive, and W. The pad formed on the surface not in contact with B.P. W. It is connected to the B bonding pattern by a wire. After the pad of the semiconductor element is connected to the surrounding bonding pattern, the semiconductor element is sealed and molded with resin to complete the semiconductor device.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
半導体装置では、次のような課題があった。リードフレ
ームを用いた半導体装置では、半導体装置全体の厚さと
面積が大きくなる。また、前記文献に示された方法によ
れば、半導体素子の搭載されるP.W.Bの表裏2面に
パターンを形成する必要があるので、銅箔を表裏に貼付
した構造の両面基板を用いなければならず、スルーホー
ルも所定数加工形成する必要があった。さらに、半導体
素子の搭載部分を薄型化をするためには、P.W.Bに
座ぐり加工を施す必要もあった。即ち、加工面或いはコ
スト面共に大きな課題があり、技術的に満足できるもの
が得られなかった。
However, the conventional semiconductor device has the following problems. In a semiconductor device using a lead frame, the thickness and area of the entire semiconductor device are large. Further, according to the method disclosed in the above-mentioned document, the P.I. W. Since it was necessary to form a pattern on the two front and back surfaces of B, it was necessary to use a double-sided board having a structure in which copper foil was attached to the front and back surfaces, and it was also necessary to process and form a predetermined number of through holes. Furthermore, in order to reduce the thickness of the semiconductor element mounting portion, P. W. It was also necessary to apply spot facing to B. That is, there are major problems in terms of processing and cost, and technically satisfactory products cannot be obtained.

【0004】[0004]

【課題を解決するための手段】第1〜第5の発明は、前
記課題を解決するために、コンタクト用の端子を有する
半導体素子を搭載したパッケージ構造からなる表面実装
型の半導体装置において、次のようなP.W.Bと半導
体素子と導電材と封止材料とを、備えている。P.W.
Bは、表面に配線パターンが形成されかつ貫通孔を有し
ている。半導体素子は、その貫通孔の位置に端子がくる
ようにP.W.Bの裏面に配置され、導電材が半導体素
子の端子と配線パターンの延在部とを接続する構成にな
っている。封止材料は、それら配線パターン延在部と貫
通孔と導電材と半導体素子を封止する構成としている。
第4及び第5の発明は、第1から第3の発明における配
線パターン上に固定され、その配線パターンを他の基板
に接続するための導電体を設けている。
In order to solve the above problems, the first to fifth inventions are directed to a surface mount type semiconductor device having a package structure in which a semiconductor element having a terminal for contact is mounted. P. W. B, a semiconductor element, a conductive material, and a sealing material are provided. P. W.
B has a wiring pattern formed on the surface and has a through hole. The semiconductor element is formed so that the terminal is located at the position of the through hole. W. It is arranged on the back surface of B and has a structure in which a conductive material connects the terminal of the semiconductor element and the extending portion of the wiring pattern. The sealing material is configured to seal the wiring pattern extending portion, the through hole, the conductive material, and the semiconductor element.
4th and 5th invention is provided on the wiring pattern in the 1st-3rd invention, and the conductor for connecting the wiring pattern to another board | substrate is provided.

【0005】第6〜第9の発明は、コンタクト用の端子
を有する半導体素子を搭載したパッケージ構造からなる
表面実装型の半導体装置の製造方法において、次のよう
な方法を講じている。即ち、表面に配線パターンが形成
されたP.W.Bに、後に半導体素子を固着するときに
該半導体素子の端子が露出するための貫通孔を形成し、
そのP.W.Bの裏面の、貫通孔から半導体素子の端子
が露出する位置に半導体素子を固着する。そして、その
端子と配線パターンの延在部とを導電材で接続し、配線
パターン延在部と貫通孔と導電材と半導体素子とを、封
止材料内に配置するようにしている。第9の発明は、第
6から第8の発明における配線パターン上に、その配線
パターンを他の基板と接続するための導電体を固定する
ようにしている。
The sixth to ninth inventions take the following method in a method of manufacturing a surface mount type semiconductor device having a package structure in which a semiconductor element having a contact terminal is mounted. That is, the P.P. W. B is formed with a through hole for exposing the terminals of the semiconductor element when the semiconductor element is fixed later.
The P. W. The semiconductor element is fixed to the back surface of B at a position where the terminal of the semiconductor element is exposed from the through hole. Then, the terminal and the extending portion of the wiring pattern are connected by a conductive material, and the wiring pattern extending portion, the through hole, the conductive material, and the semiconductor element are arranged in the sealing material. In a ninth aspect of the invention, a conductor for connecting the wiring pattern to another substrate is fixed on the wiring pattern of the sixth to eighth aspects of the invention.

【0006】[0006]

【作用】第1〜第5の発明によれば、以上のように半導
体装置を構成しているので、P.W.Bの表面には配線
パターンが形成されている。そのP.W.Bの裏面に配
置された半導体素子の端子は、貫通孔を通る導電材で該
P.W.Bの表面に形成された配線パターンの延在部と
接続される。即ち、半導体素子の外形を引き回すことな
しに、配線パターンと半導体素子の端子が導電材で接続
される。その配線パターンと導電材とを介して、半導体
素子における信号の送受信が行われることになる。それ
ら、配線パターン延在部と貫通孔と導電材と半導体素子
は、封止材料によって、保護される。第4及び第5の発
明によれば、配線パターン上の固定された導電体によっ
て、第1〜第3の発明における半導体装置が他の基板と
接続される。即ち、リードフレームを用いずに、半導体
素子が他の基板に接続される。
According to the first to fifth aspects of the invention, the semiconductor device is constructed as described above. W. A wiring pattern is formed on the surface of B. The P. W. The terminals of the semiconductor element arranged on the back surface of B are made of a conductive material passing through the through hole. W. It is connected to the extended portion of the wiring pattern formed on the surface of B. That is, the wiring pattern and the terminals of the semiconductor element are connected by the conductive material without drawing the outer shape of the semiconductor element. Signals are transmitted and received in the semiconductor element via the wiring pattern and the conductive material. The wiring pattern extension, the through hole, the conductive material, and the semiconductor element are protected by the sealing material. According to the fourth and fifth inventions, the semiconductor device according to the first to third inventions is connected to another substrate by the fixed conductor on the wiring pattern. That is, the semiconductor element is connected to another substrate without using the lead frame.

【0007】第6〜第9の発明によれば、半導体素子
は、表面に配線パターンの形成されたプリント配線板の
裏面に固着される。このとき、半導体素子の端子が、貫
通孔によって、P.W.Bの表面に露出する。その表面
に露出した端子と配線パターンの延在部が導電材で接続
される。その接続の後、配線パターン延在部と貫通孔と
導電材と半導体素子が、封止材料によって封止される。
即ち、第1〜第5の発明の半導体装置が製造される。第
9の発明によれば、第6〜第8の発明における配線パタ
ーン上に導電体が固定される。即ち、第4及び第5の発
明の半導体装置が製造される。
According to the sixth to ninth inventions, the semiconductor element is fixed to the back surface of the printed wiring board having the wiring pattern formed on the front surface. At this time, the terminal of the semiconductor element is connected to the P. W. Exposed on the surface of B. The terminal exposed on the surface and the extending portion of the wiring pattern are connected by a conductive material. After the connection, the wiring pattern extending portion, the through hole, the conductive material, and the semiconductor element are sealed with a sealing material.
That is, the semiconductor device of the first to fifth inventions is manufactured. According to the ninth invention, the conductor is fixed on the wiring pattern in the sixth to eighth inventions. That is, the semiconductor devices of the fourth and fifth inventions are manufactured.

【0008】[0008]

【実施例】第1の実施例 図1は、本発明の第1の実施例を示す半導体装置の断面
図である。この半導体装置には、片面基板のP.W.B
10が用いられ、そのP.W.B10の表面に配線パタ
ーン11が形成されている。P.W.B10の裏面に半
導体素子20が搭載されている。P.W.B10の中央
には貫通孔12が設けられ、半導体素子20の端子と配
線パターン11とが、貫通孔12を通るワイヤーで接続
されている。そして、半導体素子20の表面及び裏面と
貫通孔12とが、封止樹脂30で封止されている。図2
(1)〜(3)は、図1の半導体装置を構成するP.
W.Bと半導体素子と接着材を示す図である。同図
(1)はP.W.Bの上面図、同図(2)は半導体素子
の上面図、同図(3)が、そのP.W.Bに半導体素子
を固着する接着材を示している。P.W.B10は、ガ
ラスエポキシ等の基材を用いて構成され、該P.W.B
10の表面には8個の端子となる配線パターン11が形
成されている。また、P.W.B10の中央部には半導
体素子の端子の露出用貫通孔12が設けられ、さらに、
端部には後述する樹脂流通用の2つの貫通孔13が設け
られている。各パターン11が、貫通孔12の外周近辺
に対してそれぞれ延長形成されている。半導体素子20
の表面中央部には、ボンディング用の8個の端子である
パッド21が形成されている。また、半導体素子20を
P.W.B10に固定するための接着材22は薄いフィ
ルム状であり、該半導体素子20の上面の周囲をP.
W.Bに固着できるように、図2(3)のような枠形状
に形成されている。
First Embodiment FIG. 1 is a sectional view of a semiconductor device showing a first embodiment of the present invention. This semiconductor device includes a P.P. W. B
10 is used and its P. W. The wiring pattern 11 is formed on the surface of B10. P. W. The semiconductor element 20 is mounted on the back surface of B10. P. W. A through hole 12 is provided in the center of B10, and the terminal of the semiconductor element 20 and the wiring pattern 11 are connected by a wire passing through the through hole 12. The front surface and the back surface of the semiconductor element 20 and the through hole 12 are sealed with the sealing resin 30. Figure 2
(1) to (3) are P.s.
W. It is a figure which shows B, a semiconductor element, and an adhesive material. FIG. W. B is a top view of the semiconductor element, and FIG. W. An adhesive material for fixing the semiconductor element to B is shown. P. W. B10 is constituted by using a base material such as glass epoxy, and the P. W. B
Wiring patterns 11 to be eight terminals are formed on the surface of 10. In addition, P. W. A through hole 12 for exposing a terminal of a semiconductor element is provided in the central portion of B10, and further,
Two through holes 13 for resin circulation, which will be described later, are provided in the end portion. Each pattern 11 is formed so as to extend near the outer periphery of the through hole 12. Semiconductor device 20
Pads 21 which are eight terminals for bonding are formed in the central portion of the surface of the. In addition, the semiconductor element 20 is a P.O. W. The adhesive 22 for fixing to B10 is in the form of a thin film.
W. It is formed in a frame shape as shown in FIG. 2C so that it can be fixed to B.

【0009】次に、図を参照しつつ、図1の半導体装置
を製造する手順を説明する。図3(1),(2)は、図
2を用いた半導体装置の製造方法(その1)を示す図で
あり、同図(1)は上面図であり、同図(2)はその断
面図である。なお、図3において、図2と共通する要素
には、共通の符号が付されている。まず、半導体素子2
0を接着材22を用いてP.W.B10の裏面側に、固
着する。このとき、半導体素子20の表面の各パッド2
1は、P.W.B10の表面側から見て、貫通孔12を
通して露出するように配置され、図3(1)中の破線で
示されるように、半導体素子20の上部の周囲は枠形状
の接着材22でP.W.B10の裏面に固着される。続
いて、各パッド21は導電材であるワイヤー23で各パ
ターン11にそれぞれ接続される。即ち、P.W.B1
0の裏側の位置にある各パッド21は、図3(2)のよ
うに、貫通孔12の内側を通る8本のワイヤー23によ
って、P.W.B10の表面の各パターン11にそれぞ
れ接続される。
Next, a procedure for manufacturing the semiconductor device of FIG. 1 will be described with reference to the drawings. 3 (1) and 3 (2) are views showing a manufacturing method (1) of the semiconductor device using FIG. 2, FIG. 3 (1) is a top view, and FIG. It is a figure. Note that, in FIG. 3, elements common to those in FIG. 2 are denoted by common reference numerals. First, the semiconductor element 2
0 using the adhesive 22. W. It adheres to the back side of B10. At this time, each pad 2 on the surface of the semiconductor element 20
1 is the P. W. When viewed from the front surface side of B10, it is arranged so as to be exposed through the through hole 12, and as shown by the broken line in FIG. 3 (1), the periphery of the upper portion of the semiconductor element 20 is covered with a frame-shaped adhesive 22. W. It is fixed to the back surface of B10. Then, each pad 21 is connected to each pattern 11 by a wire 23 which is a conductive material. That is, P. W. B1
As shown in FIG. 3B, each pad 21 at the position on the back side of P. 0 is connected to the P.P. W. It is connected to each pattern 11 on the surface of B10.

【0010】図4(1)〜(3)は、図2を用いた半導
体装置の製造方法(その2)を示す図であり、同図
(1)は上面図であり、同図(2)はその断面図であ
り、同図(3)は背面図である。なお、図4において、
図2と共通する要素には、共通の符号が付されている。
各パッド21とP.W.B10表面のパターン11がそ
れぞれ接続された後、エポキシ樹脂等による封止成形が
行われる。封止成形成形によって、配線パターン11の
延在部と貫通孔12とワイヤ23と半導体素子20と
が、封止される。この封止成形の際、例えばP.W.B
10の表面側から射出された樹脂30が、貫通孔13を
通る。そのため、P.W.B10の裏面にも樹脂がまわ
り、図4のように、一度で半導体素子20が完全に被覆
される。即ち、P.W.B10の表面側では、貫通孔1
2,13及びワイヤ23,パッド21等が樹脂30で被
覆され、P.W.B10の裏面側では、半導体素子20
の外側がすべて樹脂30で被覆される。
4 (1) to 4 (3) are views showing a method of manufacturing a semiconductor device (part 2) using FIG. 2, FIG. 4 (1) is a top view, and FIG. 4 (2). Is a sectional view thereof, and FIG. 3C is a rear view thereof. In addition, in FIG.
Elements common to those in FIG. 2 are designated by common reference numerals.
Each pad 21 and P. W. After the patterns 11 on the surface of B10 are respectively connected, sealing molding is performed with an epoxy resin or the like. The extending portion of the wiring pattern 11, the through hole 12, the wire 23, and the semiconductor element 20 are sealed by the sealing molding. At the time of this sealing molding, for example, P. W. B
The resin 30 injected from the surface side of 10 passes through the through hole 13. Therefore, P. W. The resin also spreads on the back surface of B10, and the semiconductor element 20 is completely covered at once, as shown in FIG. That is, P. W. On the surface side of B10, the through hole 1
2, 13 and the wires 23, pads 21 and the like are covered with resin 30. W. On the back side of B10, the semiconductor element 20
Is entirely covered with the resin 30.

【0011】以上のように、この第1の実施例では、貫
通孔12を有したP.W.B10を用いて半導体装置を
構成し、貫通孔12を介してパッド21と配線パターン
11を接続しているので、P.W.B10が両面基板で
なく、片面基板でよくなっている。そのため、パターン
形成が容易となる上、スルーホールが不要となり、P.
W.B10の製造コストを低くすることができる。そし
て、半導体素子の機能増大に伴う素子サイズの拡大、あ
るいは半導体素子の形成技術の革新に伴うサイズの縮小
があっても追従性があり、多種の素子を共通のP.W.
B10の構造で対応させることができる。さらに、P.
W.B10自体も薄く高精度に形成することが可能であ
るため、必要以上に厚い基材の座ぐり加工をせずとも、
半導体装置全体の厚さを十分薄くすることができる。ま
た、P.W.B10の必要面積は、複数のパッド21の
形成されいる領域の面積と貫通孔12の外形でほぼ決ま
る。即ち、半導体装置20の外形から外側に向かってワ
イヤー23を出す必要がないので、例えば、パターン1
1の形成されているP.W.B10の面積を半導体素子
20の面積よりも小さくすることも可能であり、半導体
装置全体の面積が小さくなる。
As described above, in the first embodiment, the P.O. W. Since the semiconductor device is configured by using B10 and the pad 21 and the wiring pattern 11 are connected through the through hole 12, the P.B. W. B10 is improved with a single-sided substrate instead of a double-sided substrate. Therefore, the pattern formation is facilitated and the through hole is not required, and
W. The manufacturing cost of B10 can be reduced. Further, even if the element size is expanded with the increase in the function of the semiconductor element or the size is reduced with the innovation of the forming technology of the semiconductor element, there is a follow-up property, and various elements are shared by the common P.P. W.
The structure of B10 can be used. Furthermore, P.
W. Since B10 itself can be formed thinly and with high precision,
The thickness of the entire semiconductor device can be made sufficiently thin. In addition, P. W. The required area of B10 is substantially determined by the area of the region in which the plurality of pads 21 are formed and the outer shape of the through hole 12. That is, it is not necessary to extend the wire 23 from the outer shape of the semiconductor device 20 to the outside.
1 formed P.I. W. It is also possible to make the area of B10 smaller than the area of the semiconductor element 20, and the area of the entire semiconductor device becomes small.

【0012】第2の実施例 図5(1)〜(3)は、本発明の第2の実施例の半導体
装置を構成するP.W.Bと半導体素子と接着材を示す
図である。同図(1)はP.W.Bの上面図、同図
(2)は半導体素子の上面図、同図(3)が、そのP.
W.Bに半導体素子を固着する接着材を示している。図
5(1)に示されたP.W.B40は、ガラスエポキシ
等の基材を用いて構成され、該P.W.B40の表面に
は複数の端子となる配線パターン41が形成されてい
る。各パターン41は半導体装置の端子の一部を構成す
るものであり、貫通孔42の両側に、ほぼ均等に配列す
る形で形成されている。また、P.W.B40の中央部
には直線状に縦断する形で形成された長円の露出用貫通
孔42が設けられいる。それらパターン41と貫通孔4
2の間には、バスバー43が形成されている。バスバー
43は図示しない絶縁材のソルダーレジストにより、絶
縁被覆されている。P.W.B40に搭載される図5
(2)の半導体素子50の表面中央部には、ボンディン
グ用の複数のパッド51が1列に形成されている。この
構造は、近年大容量のメモリ系素子で主流になっている
ものであり、L.O.C(Lead On Chip)実装構造に準
じたパッド配列仕様である。半導体素子50をP.W.
B40に固着するための接着材52は、薄いフィルム状
であり、該半導体素子50の上部の周囲をP.W.B4
0に固着できるように、枠形状に形成されている。
Second Embodiment FIGS. 5 (1) to 5 (3) show a semiconductor device according to a second embodiment of the present invention. W. It is a figure which shows B, a semiconductor element, and an adhesive material. FIG. W. B is a top view of the semiconductor element, and FIG.
W. An adhesive material for fixing the semiconductor element to B is shown. As shown in FIG. W. B40 is composed of a base material such as glass epoxy, and the P. W. Wiring patterns 41 that serve as a plurality of terminals are formed on the surface of B40. Each pattern 41 constitutes a part of the terminal of the semiconductor device, and is formed on both sides of the through hole 42 so as to be arranged substantially evenly. In addition, P. W. An oblong exposure through hole 42 formed in a straight line is provided at the center of B40. Those patterns 41 and through holes 4
A bus bar 43 is formed between the two. The bus bar 43 is insulation-coated with a solder resist (not shown) made of an insulating material. P. W. Figure 5 mounted on B40
A plurality of pads 51 for bonding are formed in a row at the center of the surface of the semiconductor element 50 of (2). This structure has become mainstream in large capacity memory devices in recent years. O. It is a pad array specification conforming to the C (Lead On Chip) mounting structure. If the semiconductor element 50 is a P. W.
The adhesive 52 for fixing to the B40 is a thin film, and the periphery of the upper portion of the semiconductor element 50 is made of P. W. B4
It is formed in a frame shape so that it can be fixed to 0.

【0013】図6(1)〜(3)は、図5を用いた半導
体装置の製造方法を示す図であり、この図6を参照しつ
つ、P.W.B40に半導体素子50を搭載した半導体
装置を製造する手順を説明する。なお、図6において、
図5と共通する部分には共通の符号が付されている。ま
ず、半導体素子50を接着材52を用いてP.W.B4
0の裏側に固着する。このとき、半導体素子50表面の
各パッド51は、P.W.B40の表面側から見て、貫
通孔42を通して露出するように配置され、図6(1)
中の破線で示されるように、半導体素子50の上部の周
囲は枠形状の接着材52で、P.W.B10の裏面に固
着される。続いて、各パッド51はワイヤー53で、複
数のパターン41にそれぞれ接続される。即ち、図6
(1)のように、P.W.B40の裏側にある各パッド
51は、貫通孔42を通る複数のワイヤー53によっ
て、各パターン41にそれぞれ接続される。このとき、
バスバー越えボンディングが行われるが、バスバー43
はソルダーレジストで被覆されているので、ワイヤ53
の垂れ下がりによる短絡トラブル等が、防止されてい
る。
6 (1) to 6 (3) are views showing a method of manufacturing a semiconductor device using FIG. 5. Referring to FIG. W. A procedure for manufacturing a semiconductor device in which the semiconductor element 50 is mounted on B40 will be described. In addition, in FIG.
The same parts as those in FIG. 5 are designated by the same reference numerals. First, the semiconductor element 50 is bonded to the P. W. B4
Stick to the backside of 0. At this time, each pad 51 on the surface of the semiconductor element 50 is W. When viewed from the front surface side of B40, it is arranged so as to be exposed through the through hole 42.
As indicated by the broken line in the figure, the periphery of the upper portion of the semiconductor element 50 is a frame-shaped adhesive 52, which is formed of P. W. It is fixed to the back surface of B10. Subsequently, each pad 51 is connected to each of the plurality of patterns 41 by a wire 53. That is, FIG.
As in (1), P. W. Each pad 51 on the back side of B40 is connected to each pattern 41 by a plurality of wires 53 passing through the through holes 42. At this time,
Bonding over the bus bar is performed, but the bus bar 43
Is covered with solder resist, so the wire 53
Short-circuit troubles due to drooping are prevented.

【0014】次に、エポキシ樹脂60による封止成形が
行われる。樹脂の封止成形の際、P.W.B40の表面
側から射出された樹脂60によって、P.W.B10の
表面側では、貫通孔42、ワイヤ53、及びパッド52
等が、図6(2)のように樹脂60で被覆される。続い
て、図6(3)のように、端子としての機能を果たす球
状の導電体61を、ソルダーペースト等でパターン41
に仮固定する。これにより、半導体装置が完成する。導
電体61としては、例えばハンダが用いられる。図7
は、図6で製造された半導体装置の実装形態を示す図で
あり、図5と共通する要素には、共通する符号が付され
ている。完成した半導体装置において、球状の導電体6
1の仮固定された側が、他の基板70に対して対向して
置かれ、ソルダーペーストを用いたリフロー実装等の手
法で、該半導体装置が基板70に実装される。以上のよ
うに、本実施例では、貫通孔42を利用してパッド51
とパターン41を接続しているので、L.O.C(Lead
On Chip)実装構造に準じたパッド配列を有する半導体
装置を、リードフレームを用いて形成する場合に比べ、
遥かに小型で薄型の半導体装置とすることができる。こ
こで、ポリイミドコート等の手段を用いて表面被覆を完
全に施した半導体素子を用いれば、P.W.B40と同
等あるいはP.W.B40よりも大きなサイズの半導体
素子を実装することが可能である。即ち、チップサイ
ズ、またはアンダーチップサイズパッケージも可能とな
る。
Next, sealing molding with the epoxy resin 60 is performed. At the time of sealing molding of resin, P. W. The resin 60 injected from the front surface side of B40 causes P. W. On the front surface side of B10, the through hole 42, the wire 53, and the pad 52
Etc. are covered with resin 60 as shown in FIG. 6 (2). Then, as shown in FIG. 6C, a spherical conductor 61 that functions as a terminal is formed into a pattern 41 with solder paste or the like.
Temporarily fix to. Thereby, the semiconductor device is completed. As the conductor 61, for example, solder is used. Figure 7
FIG. 8 is a diagram showing a mounting mode of the semiconductor device manufactured in FIG. 6, and elements common to FIG. 5 are denoted by common reference numerals. In the completed semiconductor device, the spherical conductor 6
The temporarily fixed side of 1 is placed opposite to the other substrate 70, and the semiconductor device is mounted on the substrate 70 by a method such as reflow mounting using a solder paste. As described above, in this embodiment, the pad 51 is formed using the through hole 42.
Since the pattern 41 is connected to the L. O. C (Lead
On-chip) A semiconductor device having a pad array conforming to the mounting structure is compared to the case where a lead frame is used.
A far smaller and thinner semiconductor device can be obtained. If a semiconductor element whose surface is completely coated by means of polyimide coating or the like is used, P. W. Equivalent to B40 or P. W. It is possible to mount a semiconductor element having a size larger than B40. That is, a chip size or under chip size package is also possible.

【0015】また、バスバー43がソルダーレジストで
被覆されているので、バスバー越えボンディングの際の
短絡トラブルが防止される。一方、リードフレームを用
いた場合と比較して、P.W.B40におけるパターニ
ングの自由度が遥かに大きくなっている。つまり、リー
ドフレームを用いずに、バスバー43に対してそれぞれ
独立した複数の導電体61を用いて、基板70に半導体
装置が接続されるので、リードフレームの場合のよう
に、あえてバスバーをワイヤーボンィング点近傍に設定
する必要もなくなる。よって、例えば、パターン41の
外側を通してバスバー43を設定することも可能とな
る。したがって、ワイヤー53の配線ルートに対するル
ープコントロールに、注意を払う必要がなくなり、生産
面で有利となる。一方、パターン41上に、球状の導電
体61を仮固定しているので、近年、CPUやその周辺
の論理回路等の多ピンのLSIの新実装形態として注目
されているB.G.A(Ball Grid Array )と共に同一
基板70に混載されるとき、半田リフロー条件を合わせ
ることもできる。
Further, since the bus bar 43 is covered with the solder resist, the short-circuit trouble at the time of bonding over the bus bar can be prevented. On the other hand, as compared with the case where the lead frame is used, W. The degree of freedom of patterning at B40 is far greater. That is, since the semiconductor device is connected to the substrate 70 by using a plurality of conductors 61 that are independent of the bus bar 43 without using the lead frame, the bus bar is purposely wire-bonded as in the case of the lead frame. There is no need to set it near the swing point. Therefore, for example, the bus bar 43 can be set through the outside of the pattern 41. Therefore, it is not necessary to pay attention to the loop control for the wiring route of the wire 53, which is advantageous in terms of production. On the other hand, since the spherical conductor 61 is temporarily fixed on the pattern 41, B.B. has recently been attracting attention as a new mounting form of a multi-pin LSI such as a CPU or a logic circuit around it. G. When mixedly mounted on the same substrate 70 together with A (Ball Grid Array), the solder reflow conditions can be adjusted.

【0016】第3の実施例 図8は、本発明の第3の実施例を示す半導体装置の構造
図であり、図5と共通する要素には、共通の符号が付さ
れている。本実施例に用いられるP.W.B80は、第
2の実施例で用いたP.W.B40と同様の構成のP.
W.Bに、新たに封止樹脂60が流通する2つの貫通孔
81を設けたものであり、他のパターン41及び貫通孔
42はP.W.B40と同じ構成となっている。また、
P.W.B80に搭載される半導体素子50も、第2の
実施例と同様の構造である。図8の半導体装置を製造す
る場合も、第2の実施例と同様に、半導体素子50が
P.W.B80の裏面側の所定の位置に接着材52で固
定され、貫通孔42で表面に露出したパッド51とパタ
ーン41とが、該貫通孔42を通るワイヤー53で接続
される。パッド51とパターン41とが接続された後、
例えば、P.W.B80の表面側から樹脂60による樹
脂封止を行う。樹脂封止によって、半導体素子50の表
裏面は、図8のように完全に被覆される。つまり、樹脂
封止の際、貫通孔44は樹脂60を流通させる。よっ
て、貫通孔42によって半導体素子50のP.W.B8
0の表面から見て露出している部分及びワイヤー53は
樹脂60Aで被覆され、半導体素子50のP.W.B8
0の裏面から見て露出している部分は、樹脂60Bで被
覆される。以上のように、本実施例では、貫通孔44を
設けたP.W.B80で半導体装置を構成している。よ
って、半導体素子50の露出している部分を一度にすべ
て樹脂で被覆することができ、第2の実施例の効果を有
する半導体装置に、さらに、信頼性の高い耐湿性を持た
せることができる。
Third Embodiment FIG. 8 is a structural diagram of a semiconductor device showing a third embodiment of the present invention. Elements common to those in FIG. 5 are designated by common reference numerals. The P. W. B80 is the P. B. used in the second embodiment. W. P.B.
W. B, two through holes 81 through which the sealing resin 60 circulates are newly provided, and the other patterns 41 and the through holes 42 are formed by P.P. W. It has the same configuration as B40. Also,
P. W. The semiconductor element 50 mounted on the B80 also has the same structure as that of the second embodiment. Also in the case of manufacturing the semiconductor device shown in FIG. W. The pad 51 fixed to a predetermined position on the back surface side of the B80 with an adhesive 52 and exposed on the surface of the through hole 42 is connected to the pattern 41 by a wire 53 passing through the through hole 42. After the pad 51 and the pattern 41 are connected,
For example, P. W. Resin sealing with the resin 60 is performed from the front surface side of B80. The front and back surfaces of the semiconductor element 50 are completely covered by the resin sealing as shown in FIG. That is, at the time of resin sealing, the through hole 44 allows the resin 60 to flow. Therefore, the P.P. W. B8
The exposed portion of the semiconductor element 50 when viewed from the surface of the semiconductor element 50 and the wire 53 are covered with the resin 60A. W. B8
The exposed portion of 0 from the back surface is covered with resin 60B. As described above, in this embodiment, the P.I. W. B80 constitutes a semiconductor device. Therefore, the exposed portion of the semiconductor element 50 can be covered with the resin all at once, and the semiconductor device having the effect of the second embodiment can be provided with more reliable moisture resistance. .

【0017】第4の実施例 図9は、本発明の第4の実施例を示す半導体装置の構造
図であり、図5と共通する要素には共通の符号が付され
ている。本実施例の半導体装置は他の基板70に実装さ
れる際に、基板70の間に所定のクリアランスを設ける
突起62を、第2の実施例の半導体装置に設けている。
この半導体装置は、第2の実施例と同様のP.W.B4
0に半導体素子50を搭載している。複数の球状の導電
体61も第2の実施例と同様にパターン41上に仮固定
されている。半導体素子50のP.W.B40の表面に
露出した部分とワイヤー53は、図9のように樹脂60
で封止されている。この封止された樹脂60上には、該
樹脂60と同じエポキシ樹脂の突起62が設けられてい
る。この半導体装置の製造方法は第2の実施例と同様で
あり、突起62は樹脂封止の際に同時に形成される。図
10は、他の基板に実装された図9の半導体装置を示す
図である。半導体装置が他の基板70に実装された場
合、突起62が支えとなって、半導体装置と基板70の
間の距離が所望の値Hとなる。以上のように、本実施例
では突起62を設けているので、半導体装置の樹脂60
と基板70との間に所望のクリアランスを設定すること
ができる。そのため、実装寸法の精度が向上すると共
に、実装後のフラックス洗浄等を行う上で有効な構造と
することができる。
Fourth Embodiment FIG. 9 is a structural diagram of a semiconductor device showing a fourth embodiment of the present invention. Elements common to those in FIG. 5 are designated by common reference numerals. The semiconductor device of the present embodiment is provided with the projection 62 which provides a predetermined clearance between the substrates 70 when mounted on another substrate 70 in the semiconductor device of the second embodiment.
This semiconductor device has the same P.V. W. B4
The semiconductor element 50 is mounted on the memory cell 0. The plurality of spherical conductors 61 are also temporarily fixed on the pattern 41 as in the second embodiment. P. of the semiconductor element 50 W. The part exposed on the surface of B40 and the wire 53 are made of resin 60 as shown in FIG.
It is sealed with. On the sealed resin 60, a protrusion 62 made of the same epoxy resin as the resin 60 is provided. The method of manufacturing this semiconductor device is the same as that of the second embodiment, and the protrusions 62 are formed simultaneously at the time of resin sealing. FIG. 10 is a diagram showing the semiconductor device of FIG. 9 mounted on another substrate. When the semiconductor device is mounted on another substrate 70, the projection 62 supports the semiconductor device and the distance between the semiconductor device and the substrate 70 becomes a desired value H. As described above, since the protrusion 62 is provided in this embodiment, the resin 60 of the semiconductor device is provided.
A desired clearance can be set between the substrate 70 and the substrate 70. Therefore, the accuracy of the mounting dimensions is improved, and the structure is effective for cleaning the flux after mounting.

【0018】なお、本発明は、上記実施例に限定されず
種々の変形が可能である。その変形例としては、例えば
次のようなものがある。 (1) 上記実施例ではP.W.B10.40,80を
ガラスエポキシ、樹脂30,60をエポキシ樹脂で構成
しているが、これらの材質は絶縁性及び耐湿性に優れた
ものであればよく、他の材料で構成することも可能であ
る。 (2) 導電体61も、基板70に対して接続が可能で
あればよい。ハンダに限定されず、導電性と加工性に優
れた他の合金等も使用可能である。 (3) 第4の実施例では、第2の実施例の半導体装置
に対して突起62を設けた構造となっているが、第3の
実施例に突起を設けても、第4の実施例と同様の効果を
期待できる。
The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the above embodiment, P. W. B10.40 and 80 are made of glass epoxy, and resins 30 and 60 are made of epoxy resin. However, these materials should be excellent in insulation and moisture resistance, and can be made of other materials. Is. (2) The conductor 61 may also be connectable to the substrate 70. The alloy is not limited to the solder, and other alloys having excellent conductivity and workability can be used. (3) The fourth embodiment has a structure in which the projection 62 is provided on the semiconductor device of the second embodiment. However, even if the projection is provided in the third embodiment, the fourth embodiment You can expect the same effect as.

【0019】[0019]

【発明の効果】以上詳細に説明したように、第1から第
5の発明によれば、P.W.Bに貫通孔を設け、P.
W.Bの裏面に配置された半導体素子の端子は、貫通孔
を通る導電材で該P.W.Bの表面に形成された配線パ
ターンと接続された構成としている。よって、半導体素
子の外形を引き回すことなしに、配線パターンと半導体
素子の端子が導電材で接続される。そのためP.W.B
を両面基板で構成する必要がなくなり、座ぐり加工をせ
ずとも薄型の半導体装置となる。また、スルーホール加
工も必要がなくなる。さらに、半導体素子のサイズに関
係なく接続できるので、半導体装置全体を小さくするこ
とができ、かつ半導体素子のサイズ変化に追従可能な半
導体装置を形成することができる。即ち、半導体装置の
加工を容易にすると共にコストの低減が図れる。第4及
び第5の発明によれば、第1から第3の発明における配
線パターン上に他の基板と接続する導電体を設けている
ので、従来のリードフレームを用いたL.O.C構造よ
りも、小型かつ薄型の半導体装置が形成できると共に、
パターンの自由度が増して生産面で有利となる。また、
近年のCPUや論理回路等の実装形態のB.G.Aと、
同一の基板に実装可能な半導体装置を構成できる。
As described above in detail, according to the first to fifth inventions, the P.I. W. B is provided with a through hole, and P.
W. The terminals of the semiconductor element arranged on the back surface of B are made of a conductive material passing through the through hole. W. It is configured to be connected to the wiring pattern formed on the surface of B. Therefore, the wiring pattern and the terminals of the semiconductor element are connected by the conductive material without drawing the outer shape of the semiconductor element. Therefore, P. W. B
Since it is not necessary to configure the substrate with a double-sided substrate, a thin semiconductor device can be obtained without spot facing. In addition, there is no need for through hole processing. Furthermore, since the connection can be made regardless of the size of the semiconductor element, it is possible to reduce the size of the semiconductor device as a whole and to form a semiconductor device which can follow the size change of the semiconductor element. That is, the processing of the semiconductor device can be facilitated and the cost can be reduced. According to the fourth and fifth inventions, since the conductor for connecting to another substrate is provided on the wiring pattern in the first to third inventions, the L.L. O. A semiconductor device that is smaller and thinner than the C structure can be formed, and
The flexibility of the pattern increases, which is advantageous in terms of production. Also,
B. Implementation of recent CPUs, logic circuits, etc. G. A and
A semiconductor device that can be mounted on the same substrate can be configured.

【0020】第6〜第9の発明によれば、表面に配線パ
ターンが形成されたP.W.Bに貫通孔を形成し、P.
W.Bの裏面の、貫通孔から端子が露出する位置に半導
体素子を固着して端子と配線パターンの延在部とを導電
材で接続する。そして、配線パターン延在部と貫通孔と
導電材と半導体素子を、封止材料内に配置するようにし
ている。そのため、第1〜第5の発明の半導体装置を容
易に実現できる。よって、半導体装置全体を小さくする
ことができ、コストの低減を図れる。第9の発明によれ
ば、第6から第8の発明における配線パターン上に他の
基板と接続する導電体を固着するので、第4及び第5の
発明の半導体装置を実現できる。よって、L.O.C構
造よりも小型かつ薄型の半導体装置を形成できると共
に、パターンの自由度が増して生産面で有利となる。ま
た、近年のCPUや論理回路等の実装形態のB.G.A
と、同一の基板に実装可能な半導体装置を製造すること
ができる。
According to the sixth to ninth inventions, the P.P. W. A through hole is formed in B.
W. A semiconductor element is fixed on the back surface of B at a position where the terminal is exposed from the through hole, and the terminal and the extended portion of the wiring pattern are connected by a conductive material. Then, the wiring pattern extending portion, the through hole, the conductive material, and the semiconductor element are arranged in the sealing material. Therefore, the semiconductor device of the first to fifth inventions can be easily realized. Therefore, the entire semiconductor device can be downsized, and the cost can be reduced. According to the ninth invention, since the conductor for connecting to another substrate is fixed on the wiring pattern of the sixth to eighth inventions, the semiconductor device of the fourth and fifth inventions can be realized. Therefore, L. O. A semiconductor device that is smaller and thinner than the C structure can be formed, and the degree of freedom of patterns is increased, which is advantageous in terms of production. In addition, the B.I. G. A
With this, a semiconductor device that can be mounted on the same substrate can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す半導体装置の断面
図である。
FIG. 1 is a cross-sectional view of a semiconductor device showing a first embodiment of the present invention.

【図2】図1の半導体装置を構成するP.W.Bと半導
体素子と接着材を示す図である。
2 is a diagram illustrating a configuration of P.I. W. It is a figure which shows B, a semiconductor element, and an adhesive material.

【図3】図2を用いた半導体装置の製造方法(その1)
を示す図である。
FIG. 3 is a method of manufacturing a semiconductor device using FIG. 2 (No. 1).
FIG.

【図4】図2を用いた半導体装置の製造方法(その2)
を示す図である。
FIG. 4 is a method for manufacturing a semiconductor device using the method shown in FIG. 2 (No. 2).
FIG.

【図5】本発明の第2の実施例の半導体装置を構成する
P.W.Bと半導体素子と接着材を示す図である。
FIG. 5 is a diagram showing a structure of a P.V. W. It is a figure which shows B, a semiconductor element, and an adhesive material.

【図6】図5を用いた半導体装置の製造方法を示す図で
ある。
FIG. 6 is a diagram showing the method of manufacturing the semiconductor device using FIG. 5;

【図7】図6で製造された半導体装置の実装形態を示す
図である。
FIG. 7 is a diagram showing a mounting form of the semiconductor device manufactured in FIG. 6;

【図8】本発明の第3の実施例を示す半導体装置の構造
図である。
FIG. 8 is a structural diagram of a semiconductor device showing a third embodiment of the present invention.

【図9】本発明の第4の実施例を示す半導体装置の構造
図である。
FIG. 9 is a structural diagram of a semiconductor device showing a fourth embodiment of the present invention.

【図10】他の基板に実装された図9の半導体装置を示
す図である。
FIG. 10 is a diagram showing the semiconductor device of FIG. 9 mounted on another substrate.

【符号の説明】[Explanation of symbols]

10,40,80 P.W.B 11,41 配線パターン 12,42 貫通孔(露出用) 13,81 貫通孔(樹脂流通用) 20,50 半導体素子 21,51 パッド 22,52 接着材 23,53 ワイヤー 30,60,60A,60B 樹脂 62 突起 10, 40, 80 P.I. W. B 11,41 Wiring pattern 12,42 Through hole (for exposure) 13,81 Through hole (for resin distribution) 20,50 Semiconductor element 21,51 Pad 22,52 Adhesive 23,53 Wire 30,60,60A, 60B Resin 62 protrusion

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 コンタクト用の端子を有する半導体素子
を搭載したパッケージ構造からなる表面実装型の半導体
装置において、 表面に配線パターンが形成されかつ貫通孔を有したプリ
ント配線板と、 前記貫通孔の位置に前記端子がくるように前記プリント
配線板の裏面に配置された前記半導体素子と、 前記端子と前記配線パターンの延在部とを接続する導電
材と、 前記配線パターン延在部と前記貫通孔と前記導電材と前
記半導体素子とを封止する封止材料とを、 備えたことを特徴とする半導体装置。
1. A surface-mounted semiconductor device having a package structure in which a semiconductor element having a contact terminal is mounted, and a printed wiring board having a wiring pattern formed on its surface and having a through hole, and the through hole. The semiconductor element arranged on the back surface of the printed wiring board so that the terminal is located at a position, a conductive material connecting the terminal and the extended portion of the wiring pattern, the wiring pattern extended portion and the penetrating portion. A semiconductor device comprising: a hole, the conductive material, and a sealing material that seals the semiconductor element.
【請求項2】 前記プリント配線板は、前記貫通孔とは
異なる場所に形成された樹脂流通用貫通孔を有し、前記
配線パターン延在部と前記貫通孔と前記導電材と前記半
導体素子の表面及び裏面とは、樹脂で同時封止した構成
としたことを特徴とする請求項1記載の半導体装置。
2. The printed wiring board has a resin through hole formed at a location different from the through hole, and the wiring pattern extending portion, the through hole, the conductive material, and the semiconductor element are formed. The semiconductor device according to claim 1, wherein the front surface and the back surface are simultaneously sealed with a resin.
【請求項3】 前記プリント配線板は、前記半導体素子
に対するバスバーを表面に備え、前記バスバーの上部は
前記導電材と絶縁する絶縁材によって被覆した構造とし
たことを特徴とする請求項1または2記載の半導体装
置。
3. The printed wiring board is provided with a bus bar for the semiconductor element on a surface thereof, and an upper portion of the bus bar is covered with an insulating material which insulates from the conductive material. The semiconductor device described.
【請求項4】 前記配線パターン上に固定され、該配線
パターンを他の基板に接続するための導電体を設けたこ
とを特徴とする請求項1、2または3記載の半導体装
置。
4. The semiconductor device according to claim 1, further comprising a conductor fixed on the wiring pattern for connecting the wiring pattern to another substrate.
【請求項5】 前記半導体素子の端子と前記配線パター
ンの延在部と前記貫通孔と前記導電材とは、封止樹脂で
被覆した構成とし、該封止樹脂の上部には、前記他の基
板との間の距離を所定寸法に保つ突起を設けたことを特
徴とする請求項4記載の半導体装置。
5. The terminal of the semiconductor element, the extending portion of the wiring pattern, the through hole, and the conductive material are covered with a sealing resin, and an upper portion of the sealing resin is covered with the other material. The semiconductor device according to claim 4, further comprising a protrusion that maintains a distance between the substrate and the substrate at a predetermined size.
【請求項6】 コンタクト用の端子を有する半導体素子
を搭載したパッケージ構造からなる表面実装型の半導体
装置の製造方法において、 表面に配線パターンが形成されたプリント配線板に、後
に前記半導体素子を固着するときに該半導体素子の端子
が露出するための貫通孔を形成し、 前記プリント配線板の裏面の、前記貫通孔から前記端子
が露出する位置に前記半導体素子を固着し、 前記端子と前記配線パターンの延在部とを導電材で接続
し、 前記配線パターン延在部と前記貫通孔と前記導電材と前
記半導体素子とを封止材料内に配置するようにしたこと
を特徴とする半導体装置の製造方法。
6. A method of manufacturing a surface mount semiconductor device having a package structure in which a semiconductor element having a contact terminal is mounted, the semiconductor element being fixed to a printed wiring board having a wiring pattern formed on the surface thereof. Forming a through hole for exposing the terminal of the semiconductor element, and fixing the semiconductor element to a position on the back surface of the printed wiring board where the terminal is exposed from the through hole, the terminal and the wiring A semiconductor device, characterized in that the extending portion of the pattern is connected by a conductive material, and the wiring pattern extending portion, the through hole, the conductive material and the semiconductor element are arranged in a sealing material. Manufacturing method.
【請求項7】 前記プリント配線板には、前記貫通孔と
は異なる場所に樹脂流通用貫通孔を形成し、前記端子と
前記配線パターンの延在部とを導電材で接続した後、前
記配線パターン延在部と前記貫通孔と前記導電材と前記
半導体素子の表面及び裏面とを樹脂で同時に封止するこ
とを特徴とする請求項6記載の半導体装置の製造方法。
7. The printed wiring board is provided with resin through holes at locations different from the through holes, the terminals and the extending portions of the wiring pattern are connected by a conductive material, and then the wiring is provided. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the pattern extending portion, the through hole, the conductive material, and the front surface and the back surface of the semiconductor element are simultaneously sealed with resin.
【請求項8】 前記プリント配線板の表面に前記半導体
素子に対するバスバーを形成し、前記バスバーの上部に
は、前記導電材と該バスバーを絶縁するための絶縁被覆
を施すことを特徴とする請求項6または7記載の半導体
装置の製造方法。
8. A bus bar for the semiconductor element is formed on a surface of the printed wiring board, and an insulating coating for insulating the conductive material from the bus bar is provided on an upper portion of the bus bar. 6. The method for manufacturing a semiconductor device according to 6 or 7.
【請求項9】 前記配線パターン上に該配線パターンを
他の基板に接続するための導電体を固定することを特徴
とする請求項6、7または8記載の半導体装置の製造方
法。
9. The method of manufacturing a semiconductor device according to claim 6, wherein a conductor for connecting the wiring pattern to another substrate is fixed on the wiring pattern.
JP10635995A 1995-04-28 1995-04-28 Semiconductor device and manufacturing method thereof Expired - Lifetime JP3553195B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10635995A JP3553195B2 (en) 1995-04-28 1995-04-28 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10635995A JP3553195B2 (en) 1995-04-28 1995-04-28 Semiconductor device and manufacturing method thereof

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2004000538A Division JP3737093B2 (en) 2004-01-05 2004-01-05 Semiconductor device
JP2004102369A Division JP3728317B2 (en) 2004-03-31 2004-03-31 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
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ID=14431561

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333564B1 (en) 1998-06-22 2001-12-25 Fujitsu Limited Surface mount type semiconductor device and method of producing the same having an interposing layer electrically connecting the semiconductor chip with protrusion electrodes
US6780681B2 (en) 2001-12-27 2004-08-24 Shinko Electric Industries Co., Ltd. Process of manufacturing a semiconductor device
US6890796B1 (en) 1997-07-16 2005-05-10 Oki Electric Industry Co., Ltd. Method of manufacturing a semiconductor package having semiconductor decice mounted thereon and elongate opening through which electodes and patterns are connected
JP2005530358A (en) * 2002-06-19 2005-10-06 ワン,チェン,キーアン Packaging for microchip devices
JP2008078646A (en) * 2006-09-19 2008-04-03 Samsung Electro Mech Co Ltd Printed circuit board for package, and manufacturing method thereof
US7443041B2 (en) 2001-01-15 2008-10-28 United Test & Assembly Center Limited Packaging of a microchip device
US7663251B2 (en) 1997-07-16 2010-02-16 Oki Semiconductor Co., Ltd. Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
JP2012084908A (en) * 2011-12-15 2012-04-26 United Test And Assembly Center (S) Pte Ltd Packaging method for microchip device
KR101409839B1 (en) * 2007-05-23 2014-06-26 삼성전자주식회사 Semiconductor package

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7663251B2 (en) 1997-07-16 2010-02-16 Oki Semiconductor Co., Ltd. Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
US6890796B1 (en) 1997-07-16 2005-05-10 Oki Electric Industry Co., Ltd. Method of manufacturing a semiconductor package having semiconductor decice mounted thereon and elongate opening through which electodes and patterns are connected
US7129587B2 (en) 1997-07-16 2006-10-31 Oki Electric Industry Co., Ltd. Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
US7365439B2 (en) 1997-07-16 2008-04-29 Oki Electric Industry Co., Ltd. Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
US8018076B2 (en) 1997-07-16 2011-09-13 Oki Semiconductor Co., Ltd. Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
US6333564B1 (en) 1998-06-22 2001-12-25 Fujitsu Limited Surface mount type semiconductor device and method of producing the same having an interposing layer electrically connecting the semiconductor chip with protrusion electrodes
US7443041B2 (en) 2001-01-15 2008-10-28 United Test & Assembly Center Limited Packaging of a microchip device
US6780681B2 (en) 2001-12-27 2004-08-24 Shinko Electric Industries Co., Ltd. Process of manufacturing a semiconductor device
JP2005530358A (en) * 2002-06-19 2005-10-06 ワン,チェン,キーアン Packaging for microchip devices
US7504715B2 (en) 2002-06-19 2009-03-17 United Test & Assembly Center Limited Packaging of a microchip device
JP2008078646A (en) * 2006-09-19 2008-04-03 Samsung Electro Mech Co Ltd Printed circuit board for package, and manufacturing method thereof
KR101409839B1 (en) * 2007-05-23 2014-06-26 삼성전자주식회사 Semiconductor package
JP2012084908A (en) * 2011-12-15 2012-04-26 United Test And Assembly Center (S) Pte Ltd Packaging method for microchip device

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