JPH08306775A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE: To provide a technology for enhancing the device performance by reducing the interconnection crosstalk capacity. CONSTITUTION: A multilayer interconnection is constituted of a lower layer interconnection 4 and an upper layer interconnection 8 through an interlayer insulating film 10 comprising a laminate of a first insulating film 5, a third insulating film 7 and a space region 9 (formed by removing a second insulating film 6). Since the space region 9 is present at a part of the interlayer insulating film 10 and the permittivity of the air is low (about 1.0), the interconnection crosstalk capacity is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device for reducing inter-wiring crosstalk capacitance formed between wirings arranged via an interlayer insulating film. It relates to effective technology.

[0002]

2. Description of the Related Art Recent semiconductor devices typified by LSIs tend to have a higher degree of integration as more functions and smaller sizes are required. With such a high degree of integration, a plurality of wirings that are arranged adjacent to each other in a plane on the semiconductor substrate must be formed at a finer pitch. Furthermore, not only this but multilayer wiring in which the wiring is formed in multiple stages in the thickness direction of the substrate is adopted.

When a plurality of wirings are formed adjacent to each other with a fine pitch, or when a multilayer wiring is formed, between adjacent wirings or between a lower layer wiring and an upper layer wiring constituting the multilayer wiring. Must be insulated with an interlayer insulating film.

In this case, the material forming the interlayer insulating film is
In order to obtain excellent insulation properties or to prevent breakage when forming upper layer wiring, a structure in which a plurality of different materials are laminated instead of a single layer is often adopted. ing.

As an example, the interlayer insulating film is composed of three layers in which a first insulating film to a third insulating film are sequentially laminated. For example, plasma CV is used as the first insulating film.
D method (Chemical Vapor Deposition)
ion method) to form an oxide film (SiO ₂ film) to cover the lower wiring composed of a plurality of wirings, and the second insulating film is formed on the first insulating film by SOT (excellent flatness) by spin coating. A spin on glass) film is formed, and an oxide film is formed as a third insulating film on the second insulating film by a plasma CVD method.

A technique for laminating a plurality of insulating films on a semiconductor substrate as described above is disclosed in, for example, "V.
"LSI Process Equipment Handbook", June 1, 1990
Issued on 0th, p. 48.

[0007]

As the demand for fine wiring pitch increases with the high integration of LSIs, the crosstalk capacitance between wirings formed between wirings tends to increase. There is a problem of having a great influence.

That is, when the fine pitch of the wiring is further advanced, the inter-wiring capacitance formed by the wirings adjacent to each other via the interlayer insulating film is opposed to the lower wiring and the upper wiring which are opposed to each other via the interlayer insulating film. Since the inter-wiring crosstalk capacitance including the inter-wiring capacitance formed between the wirings tends to increase, crosstalk occurs between the wirings, which affects the operation of the LSI.

An object of the present invention is to provide a technique capable of reducing crosstalk capacitance between wirings and improving device performance.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A semiconductor device of the present invention is a semiconductor device in which an upper wiring is formed on a lower wiring formed on the surface of a semiconductor substrate with an interlayer insulating film interposed therebetween. A space region is formed in the part.

(2) The semiconductor device manufacturing method of the present invention is
A step of forming a lower layer wiring on the surface of the semiconductor substrate, a step of forming an interlayer insulating film so as to cover the lower layer wiring, a step of forming an upper layer wiring on the interlayer insulating film, and a part of the interlayer insulating film Is removed to form a spatial region.

(3) In another method of manufacturing a semiconductor device of the present invention, a step of forming a plurality of lower layer wirings adjacent to each other on the surface of a semiconductor substrate, and a first step of covering the lower layer wirings A step of forming an insulating film, a step of forming a second insulating film made of a softening material so as to be stacked on the first insulating film, and a step of forming a third insulating film on the second insulating film. The method includes a step of forming films so as to be stacked, a step of forming an upper wiring on the third insulating film, and a step of removing the second insulating film to form a space region.

[0015]

According to the above-mentioned means (1), the semiconductor device of the present invention is a semiconductor device in which the upper layer wiring is formed on the lower layer wiring formed on the surface of the semiconductor substrate via the interlayer insulating film. Since the space region is formed in a part of the interlayer insulating film, it is possible to reduce the crosstalk capacitance between wirings and improve the device performance.

According to the above-mentioned means (2), in the method of manufacturing a semiconductor device of the present invention, the step of forming the lower layer wiring on the surface of the semiconductor substrate and the step of forming the interlayer insulating film so as to cover the lower layer wiring. Since it includes a step, a step of forming an upper layer wiring on the interlayer insulating film, and a step of removing a part of the interlayer insulating film to form a space region, the crosstalk capacitance between wirings is reduced. It is possible to improve device performance.

According to the above-described means (3), another method of manufacturing a semiconductor device according to the present invention comprises a step of forming a plurality of lower layer wirings adjacent to each other on the surface of a semiconductor substrate,
Forming a first insulating film so as to cover the lower wiring, forming a second insulating film made of a softening material on the first insulating film, and forming a second insulating film. Forming a third insulating film so as to be laminated on the second insulating film; forming an upper wiring on the third insulating film; and removing the second insulating film to form a space region. Since the step of forming is included, it is possible to reduce the crosstalk capacitance between wirings and improve the device performance.

Hereinafter, the present invention will be described in detail with reference to the drawings along with embodiments.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0020]

1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. In the semiconductor device 1 of the present embodiment, a plurality of lower layer wirings 4 made of, for example, Al are adjacent to each other on the protective film 3 on the surface of the semiconductor substrate 2 made of, for example, a silicon single crystal substrate in which a desired element region is formed. It is formed so as to be arranged. Each lower layer wiring 4 is connected to a desired element region in the substrate 2, and is formed with a pitch of about 3 to 5 μm and a thickness of about 1 μm as an example.

The lower wiring 4 is formed by plasma CVD method, T
EOS method (Tetra Ethyl Ortho Sil
an oxide film (SiO) having a thickness of about 0.05 to 0.1 μm formed by, for example,
The first insulating film 5 composed of _two films) is covered with the first insulating film 5, and similarly, for example, a plasma CVD method,
By the TEOS method or the like, for example, the thickness is about 0.1 to 0.3.
A third insulating film 7 made of an oxide film having a thickness of μm is formed so as to be partially laminated, and an upper layer wiring 8 made of, for example, Al having a thickness of about 1 μm is formed on the third insulating film 7. Has been done.

As an example, the height between the first insulating film 5 and the third insulating film 7 and mainly between the lower wirings 4 is about 2 to 4 μm.
The space region 9 of is formed. The space region 9 is formed by removing the second insulating film after the second insulating film is formed on the first insulating film 5 in advance, as described later. The first insulating film 5, the third insulating film 7 and the space region 9 which are laminated on each other form an interlayer insulating film 10, and the lower layer wiring 4 and the upper layer wiring 8 form a multilayer wiring via the interlayer insulating film 10. It is configured. It should be noted that the relative thickness relationships of the respective wirings, insulating films, etc. shown in the figure are schematically shown for easy understanding of the description, and the actual relative thickness relationships are not reflected. The same applies to the following description.

Next, a method of manufacturing the semiconductor device 1 of this embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 2, a semiconductor substrate 2 made of, for example, a silicon single crystal substrate is prepared, a desired element region is formed by a well-known process, and then, for example, Al is formed on the surface protective film 3. Lower layer wiring 4 consisting of
As an example, the pitch is about 3 to 5 μm, and the thickness is about 1 μm.
Is formed adjacent to. The method of forming the lower wiring 4 is, for example, a CVD method, a PVD method (Pys) using a conductive film such as Al.
After being formed on the entire surface by the chemical vapor deposition method) or the like, it is patterned into a desired shape by the photolithography method.

Next, as shown in FIG. 3, the first insulating film 5 made of, for example, an oxide film having a thickness of about 0.05 to 0.1 μm is formed by, for example, a plasma CVD method, a TEOS method, or the like.
Are formed to cover the plurality of lower layer wirings 4. For the first insulating film 5, a material is selected that has excellent adhesion to the lower layer wiring 4 or the protective film 3 and does not adversely affect them.

Subsequently, as shown in FIG. 4, a thickness of about 3 is formed on the first insulating film 5 by, for example, a spin coating method.
A second insulating film 6 made of a photoresist having a thickness of ˜5 μm is formed. A material having softness and excellent flatness is selected for the second insulating film 6. That is, the second insulating film 6 is preferably made of a material that is easily softened so as to be easily removed when the space region is formed later by removing it, and a break does not occur when the upper layer wiring is formed later. A material that can be applied evenly is desirable. After application, this second
The photoresist which is the insulating film 6 is baked and solidified.

Next, as shown in FIG. 5, the second insulating film 6 is back-etched by a dry etching method such as a plasma etching method to position the first insulating film 5 on the lower wiring 4. Etching is performed so that the height is almost the same as.
Even at this point, the surface of the second insulating film 6 is kept flat. Although the second insulating films 6 appear to be separated in the illustrated cross-sectional structure, they are actually in a continuous relationship in the direction perpendicular to the paper surface.

Then, as shown in FIG. 6, a third oxide film having a thickness of, for example, about 0.1 to 0.3 μm is formed on the second insulating film 6 by, for example, the plasma CVD method or the TEOS method. The insulating film 7 is formed. The surface of the third insulating film 7 is similarly formed flat because the surface of the second insulating film 6 immediately below the third insulating film 7 is kept flat. This third
The insulating film 7 is selected from a material that is excellent in adhesiveness to the second insulating film 6 or an upper wiring formed later and does not adversely affect them.

Next, as shown in FIG. 7, for example, CVD
Method, PVD method (Physical Vapor Depo)
The upper wiring 8 made of, for example, Al and having a thickness of about 1 μm is formed on the third insulating film 7 by the method such as the position method). After the upper wiring 8 is formed on the entire surface in advance,
It is patterned into a desired shape by photolithography.

Then, as shown in FIG. 8, the second insulating film 6 formed between the first insulating film 5 and the third insulating film 7 and mainly between the lower wirings 4 is removed. As an example, a space region 9 having a height of about 2 to 4 μm is formed on this trace. The space area 9 is formed as follows.

For example, as shown in the partial perspective views of FIGS. 9 and 10, a photolithography method is applied to the position of the third insulating film 7 that bypasses the position where the upper layer wiring 8 is formed on the semiconductor substrate 2. A plurality of through holes 11 are formed. Next, a photoresist removing solution is injected from a part of these through holes 11 as shown by an arrow 12, and the pressure of this injection causes the second insulating film 6 to be removed from the through holes 11 of the other part as shown by an arrow 13. Eject and remove a photoresist. Thereby, the space area 9 is formed. This space area 9 is the second
Since the insulating film 6 is continuously formed as described above, it is continuously formed in a hollow shape. Then, a baking treatment is performed to remove the injected photoresist removing liquid.

As described above, the semiconductor device 1 shown in FIG.
Can be manufactured. The upper wiring 8 on the interlayer insulating film 10 may be protected by another insulating film, if necessary.

In this way, the lower layer wiring 5 and the upper layer wiring 8 are multilayered through the interlayer insulating film 10 constituted by the first insulating film 5, the third insulating film 7 and the space region 9 which are laminated on each other. According to the semiconductor device 1 of this embodiment in which the wiring is formed, the inter-wiring crosstalk capacitance can be reduced because the space region 9 exists in a part of the interlayer insulating film 10. That is, when the interlayer insulating film is composed mainly of an oxide film (SiO ₂ ) as in the conventional semiconductor device, the dielectric constant of the oxide film is approximately 3.9, whereas When a part of the interlayer insulating film 10 is composed of the space region 9 as in the semiconductor device of the example, the dielectric constant of air is approximately 1.0, and as a result, the inter-wiring crosstalk capacitance is reduced. Become so. This allows
Even if the fine pitch of the wiring is further advanced with the high integration of the LSI, the device performance will not be greatly affected.

According to this embodiment, the following effects can be obtained.

Interlayer insulating film 10 partially including a space region 9
Since the plurality of lower layer wirings 4 and the upper layer wirings 8 are arranged through the wirings, it is possible to reduce the inter-wiring crosstalk capacitance and improve the device performance.

As described above, the inventions made by the present inventor are
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, in the above-described embodiment, the method of removing the insulating film to form the space region has been described by taking the example of injecting the photoresist removing liquid into the through hole and discharging the insulating film. On the contrary, it is also possible to form the space region by sucking the insulating film from the through hole by a method such as vacuum suction.

Further, although an example of applying a photoresist as an insulating film in advance to form a space region has been described, the present invention is not limited to this, and other materials such as SOG can be used.

Furthermore, although an example of forming a two-layer wiring as the multilayer wiring has been described, the present invention can be similarly applied to the case of forming a multilayer wiring of three layers or more.

Furthermore, although an example of forming the interlayer insulating film in a three-layer structure has been described, the invention is not limited to this.

In the above description, the case where the invention made by the present inventor is mainly applied to the technology of the semiconductor device which is the field of application which is the background of the invention has been described, but the invention is not limited thereto. The present invention can be applied to the condition that the multilayer wiring is formed at least through the interlayer insulating film.

[0042]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

Since a plurality of lower layer wirings and upper layer wirings are arranged via the interlayer insulating film including a space area in a part, it is possible to reduce the crosstalk capacitance between wirings and improve the device performance. .

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step in the semiconductor device fabrication method of the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a partial perspective view showing another step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor substrate, 3 ... Protective film, 4 ... Lower wiring, 5 ... 1st insulating film, 6 ... 2nd insulating film (photoresist), 7 ... 3rd insulating film, 8 ... Upper layer wiring, 9 ... Space region, 10 ... Interlayer insulating film, 11 ... Through hole, 12 ... Direction of injecting photoresist removing liquid, 13 ... Direction of removing second insulating film.

Claims (7)

[Claims] 1. A semiconductor device in which an upper wiring is formed on a lower wiring formed on the surface of a semiconductor substrate via an interlayer insulating film, and a space region is formed in a part of the interlayer insulating film. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the lower layer wiring includes a plurality of wirings arranged adjacent to each other. 3. The semiconductor device according to claim 1, wherein the interlayer insulating film includes a plurality of stacked insulating films. 4. A step of forming a lower layer wiring on a surface of a semiconductor substrate, a step of forming an interlayer insulating film so as to cover the lower layer wiring, a step of forming an upper layer wiring on the interlayer insulating film, and the interlayer insulating film. A step of removing a part of the insulating film to form a spatial region, the method for manufacturing a semiconductor device. 5. A step of forming a plurality of lower layer wirings adjacent to each other on a surface of a semiconductor substrate, a step of forming a first insulating film so as to cover the lower layer wirings, and a first insulating layer. A step of forming a second insulating film made of a material having a softening property on the film so as to be stacked, a step of forming a third insulating film on the second insulating film, and 3. A method of manufacturing a semiconductor device, comprising: a step of forming an upper wiring on the insulating film 3; and a step of removing the second insulating film to form a space region. 6. The second insulating film is made of photoresist, and a photoresist removing solution is injected through a through hole formed in the third insulating film to remove the photoresist and form a spatial region. The method for manufacturing a semiconductor device according to claim 5, wherein 7. The method according to claim 5, wherein the third insulating film is formed after the second insulating film is formed and the second insulating film is back-etched. Manufacturing method of semiconductor device.