JPH08304513A - Failure diagnosis system - Google Patents

Abstract

PURPOSE: To speedily and accurately diagnose a failure by a means for defining stack fault, a means for simulating stuck-at fault, and a means for judging fault gate of suspect. CONSTITUTION: A means 11 for defining stuck-at fault inputs logic connection data 1 and refers to a fault gate 17 of suspect and defines 0 stuck-at fault or 1 stuck-at fault for the output of each fault gate of suspect. A means 12 for simulating stuck-at fault inputs a test pattern 2, performs fault simulation for the stuck-at fault defined by the means 11, and obtains a detection observation point. A means 13 for judging fault gate of suspect judges that an error may be produced when conditions that the stuck-at fault defined by the means 1 is detected at an observation point where a rest by a tester 100 results in an error and is not detected at an observation point where no error pattern results in an error and then outputs the gate to a fault gate 17 of suspect. When a failed part can be narrowed down, the gate 17 is displayed as a diagnosis result 16 by a diagnosis result display means 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure diagnosis system for a logic circuit, and more particularly to a failure diagnosis system for diagnosing a failure of a circuit determined to be defective as a result of a test using a tester.

[0002]

2. Description of the Related Art Conventionally, in this type of technique, the calculation time required for the fault simulation and the fault dictionary are required by sequentially comparing the fault simulation result based on the single stuck-at fault defined in the input / output of the gate with the test result by the tester. Several methods have been proposed to reduce the file size. For example, in Japanese Patent Laid-Open No. 4-266169,
A technique is described in which a fault to be simulated is defined stepwise and a diagnostic fault simulation is performed to reduce machine resources and improve the precision of fault diagnosis.
Further, Japanese Patent Laid-Open No. 4-195547 discloses a technique for reducing the processing time by collating the simulation result with the actual inspection result and narrowing down the simulation target list.

As another technique, there has been proposed a method of diagnosing a failure location by comparing a result of logic simulation assuming an arbitrary failure with a test result of a tester. For example, Japanese Patent Application Laid-Open No. 4-55776 describes a technique for identifying the cause of failure by comparing the expected value obtained by logic simulation with the measurement result obtained by a tester.

[0004]

In the above-mentioned prior art,
First, in the method of diagnosing a fault location by sequentially collating the fault simulation result based on the single stuck-at fault defined in the input / output of the gate and the test result by the tester,
There is a problem in that it is not possible to point out faulty points such as stuck-at faults and short circuit faults inside gates that are often found.

This is because the fault simulation is premised on a single stuck-at fault at the input / output of the gate. That is, it is determined whether or not a defined fault actually exists by checking whether the results of the fault simulation and the test results of the tester match, and the faults that do not match are excluded for each test pattern. With regard to stuck-at faults and short-circuit faults, the results of the fault simulation do not match the test results of the tester, and all the defined faults are excluded, and these faulty circuit parts cannot be pointed out.

Further, in the method of diagnosing a failure point by comparing the result of logic simulation assuming an arbitrary failure with the test result of the tester, the failure point can be identified by increasing the scale and complexity of the target circuit. There is a problem that it is very troublesome.

This requires the designer to first estimate the fault that is the cause based on the test results of the tester, and to estimate the suspected fault, it is necessary to be familiar with the circuit under test. This is because it is very difficult to estimate the failure location due to the increase in the scale and complexity of the target circuit. Also, if the result of the logic simulation assuming the estimated failure and the test result by the tester do not match due to an error in the estimation, it is necessary to repeat the estimation and the logic simulation many times.

An object of the present invention is to perform fault diagnosis at high speed,
It is also to improve the accuracy of diagnosis. More specifically, not only the stuck input / output stuck-at failure of the gate but also the stuck-at failure inside the gate and the short-circuited failure which are actually many can be narrowed down to improve the accuracy of the failure diagnosis. In addition, by providing a method for efficiently and automatically diagnosing failure points in a short time even for large-scale circuits,
It is an object of the present invention to provide a method by which even a person who is not familiar with a circuit under test can easily diagnose a failure location.

[0009]

In order to solve the above-mentioned problems, a failure diagnosis system of the present invention is a failure diagnosis system for a logic circuit for diagnosing a failure of the logic circuit based on a result of a test of a function level of the logic circuit. , A stuck-at fault defining means for defining 0 stuck-at faults and 1 stuck-at faults at the output of the suspected fault gate, and a test simulation used by the test pattern used in the test, and the stuck-at faults defined by the stuck-at fault defining means are detected. Stuck-at fault simulation means for determining at which observation point the fault is detected, and if a fault is detected by the stuck-at fault simulation means at the observation point at which an error has occurred by the test, it is determined that there is a possibility of an error cause. However, regarding the observation points that do not generate an error in the pattern If a fault is detected by the stuck-at fault simulation means and a suspected fault gate determining means determines that there is no possibility of error cause.

Another fault diagnosis system of the present invention is
In a failure diagnosis system of a logic circuit for diagnosing a failure of the logic circuit based on the result of the test of the function level of the logic circuit, an indefinite failure definition means for defining a failure in which the value at the time of failure is undefined at the output of the suspected failure gate, and , Perform a failure simulation using the test pattern used in the test,
An indefinite fault simulation means for determining to which observation point an indefinite value is output by the indefinite fault defined by the indefinite fault definition means, and all the errors by the indefinite fault simulation means with respect to the pattern in which an error occurs due to the test. When an indeterminate value is detected for the generated observation point, it is determined that there is a possibility of an error cause, and an observation point at which at least one error has been generated by the indefinite fault simulation means with respect to the pattern in which the error has occurred by the test. If a value that is not an indefinite value is detected, a suspected failure gate determination unit that determines that there is no possibility of an error cause is provided.

Another fault diagnosis system of the present invention is
In a logic circuit failure diagnosis system for diagnosing a failure of a logic circuit based on a result of a test of a function level of the logic circuit, a stuck-at fault defining means for defining 0 stuck-at fault and 1 stuck-at fault at an output of a suspected fault gate, Using the test pattern used in the test, the input value and the output value of the gate in the normal case and the input value and the output value of the gate in the case of the fault defined by the stuck-at fault defining means are obtained, and the suspected failure gate is obtained. A stuck-at fault simulation means for determining at which observation point a stuck-at fault defined in the output of is detected, and a failure is detected by the stuck-at fault simulation means for an observation point that does not generate an error by the test, The output value of the suspected failure gate is a normal case gage obtained by the stuck-at failure simulation means. The output value of the suspected failure gate is estimated by the stuck-at fault simulation means when the fault is detected by the stuck-at fault simulation means at the observation point where an error occurs in the test. A gate output value estimating means for estimating that the output value of the gate in the normal case is the opposite value, and an input value of the gate in the case where there is the failure obtained by the stuck-at fault simulation means and the Truth table creating means for creating a truth table of the suspected failure gate from the combination with the output value of the gate estimated by the gate output value estimating means, and removing a gate having a contradiction in the truth table from the suspected failure gate Have and.

Further, another failure diagnosis system of the present invention is
In a failure diagnosis system for a logic integrated circuit, which diagnoses a failure of a logic circuit based on a result of a test of a function level of the logic circuit, a suspected failure gate setting means for manually setting an initial value of a suspected failure gate in the logic circuit. And a stuck-at fault defining means for defining 0 stuck-at faults and 1 stuck-at faults at the output of the suspected fault gate, and a fault simulation using the test pattern used in the test, and stuck-at faults defined by the stuck-at fault defining means. A stuck-at fault simulation means for determining at which observation point is detected, and if a failure is detected by the stuck-at fault simulation means at the observation point at which an error has occurred by the test, it is possible that there is a possibility of an error cause. Judgment and observation that does not cause an error in the pattern that caused an error by the above test A suspected fault gate determining means determines that there is no possibility of errors caused when a failure is detected by the stuck-at fault simulation means with respect to,
The stuck-at fault defining means for defining 0 stuck-at faults and 1 stuck-at faults at the output of the suspected fault gate, and the input value and output value of the gate in the normal case using the test pattern used in the test and the stuck-at fault defining means. Stuck-at fault simulation means for determining at which observation point the stuck-at fault defined at the output of the suspected-fault gate is obtained by obtaining an input value and an output value of the gate when there is a defined fault, When a fault is detected by the stuck-at fault simulation means with respect to an observation point that does not generate an error by the test, the output value of the suspected fault gate is the output value of the gate in the normal case obtained by the stuck-at fault simulation means. It is estimated that they are the same, and the stuck-at fault simulation is performed for the observation point where an error has occurred in the test. Gate output value estimation for estimating that the output value of the suspected failure gate is the opposite value of the output value of the normal gate obtained by the stuck-at fault simulation means when a failure is detected by the operation means. Means, and a truth value table of the suspected failure gate from a combination of the input value of the gate when the fault is obtained by the stuck-at fault simulation means and the output value of the gate estimated by the gate output value estimation means. And a truth table creating means for creating a gate having a contradiction in the truth table and removing it from the suspected failure gate.

Another fault diagnosis system of the present invention is
In a failure diagnosis system for a logic integrated circuit, which diagnoses a failure of a logic circuit based on a result of a test of a function level of the logic circuit, a suspected failure gate setting means for manually setting an initial value of a suspected failure gate in the logic circuit. And an indefinite fault definition means for defining a fault in which the value at the time of failure is indefinite in the output of the suspected failure gate, and a fault simulation using the test pattern used in the test, and defined by the indefinite fault definition means. An indefinite fault simulation means for determining to which observation point an indefinite value is output due to an indefinite fault, and an indefinite value is detected for an observation point where all the errors have occurred by the indefinite fault simulation means with respect to the pattern in which an error has occurred due to the test. If the error is detected, it is judged that there is a possibility of error and the error is Suspected fault gate determination means for determining that there is no possibility of an error cause when a non-indeterminate value is detected for the observation points at which at least one error has occurred with respect to the generated pattern, and the suspected A stuck-at fault defining means for defining 0 stuck-at faults and 1 stuck-at faults at the output of the fault gate, and an input value and output value of the gate in a normal case using the test pattern used in the test, and the stuck-at fault defining means. A stuck-at fault simulation means for determining at which observation point the stuck-at fault defined in the output of the suspected-failed gate is obtained by obtaining an input value and an output value of the gate in the case where there is a selected fault; For the observation points that do not generate an error by the test, the stuck-at fault simulation means If it is issued, it is estimated that the output value of the suspected failure gate is the same as the output value of the gate in the normal case obtained by the stuck-at fault simulation means, and regarding the observation point at which an error occurred by the test. A gate for estimating that the output value of the suspected failure gate is a value opposite to the output value of the normal gate obtained by the stuck-at fault simulation means when a failure is detected by the stuck-at fault simulation means. The truth of the suspected failure gate from the combination of the output value estimation means and the gate input value when the fault is obtained by the stuck-at fault simulation means and the gate output value estimated by the gate output value estimation means. A truth table creating means for creating a value table and removing gates having inconsistencies in the truth table from the suspected failure gate Have and.

Another failure diagnosis system of the present invention is
In a failure diagnosis system for a logic circuit that diagnoses a failure of the logic circuit based on the result of the function level test of the logic circuit,
A circuit trace in which the circuit is traced from the observation point where an error is detected in the test result toward the input side of the circuit, and the gate in the range traced until reaching the input end of the logic circuit is the initial value of the suspected failure gate. Means, a stuck-at fault defining means for defining 0 stuck-at faults and 1 stuck-at faults at the output of the suspected failure gate, and a test simulation used in the test pattern used in the test, and the stuck-at faults defined by the stuck-at fault defining means. A stuck-at fault simulation means for determining at which observation point a fault is detected, and if a failure is detected by the stuck-at fault simulation means for an observation point at which an error has occurred by the test, it means that there is a possibility of an error cause. Is judged,
A suspected failure gate determination unit that determines that there is no possibility of an error cause when the stuck-at fault simulation unit detects a fault with respect to an observation point that does not cause an error in the pattern in which an error has occurred by the test, and a suspected fault The stuck-at fault defining means for defining 0 stuck-at faults and 1 stuck-at faults at the output of the gate, and the input value and output value of the gate in the normal case using the test pattern used in the test, and the stuck-at fault defining means. A stuck-at fault simulation means for determining at which observation point the stuck-at fault defined in the output of the suspected-failure gate is detected by obtaining an input value and an output value of the gate when there is a failure, and the test. A fault is detected by the stuck-at fault simulation means for an observation point that does not generate an error. In this case, it is estimated that the output value of the suspected fault gate is the same as the output value of the gate in the normal case obtained by the stuck-at fault simulation means, and the stuck-at degeneration is performed with respect to the observation point where an error occurs in the test. A gate output value for estimating that the output value of the suspected failure gate is the opposite of the output value of the gate in the normal case obtained by the stuck-at fault simulation means when a failure is detected by the failure simulation means. A truth table of the suspected failure gate based on a combination of an estimating unit and an input value of the gate when the fault is obtained by the stuck-at fault simulation unit and an output value of the gate estimated by the gate output value estimating unit. And a truth table creating means for removing a gate having a contradiction in the truth table from the suspected failure gate. To.

Another failure diagnosis system of the present invention is
In a failure diagnosis system for a logic circuit that diagnoses a failure of the logic circuit based on the result of the function level test of the logic circuit,
A circuit trace in which the circuit is traced from the observation point where an error is detected in the test result toward the input side of the circuit, and the gate in the range traced until reaching the input end of the logic circuit is the initial value of the suspected failure gate. Means, an indefinite fault definition means for defining a fault whose value at the time of failure is indefinite in the output of the suspected failure gate, and a fault simulation using the test pattern used in the test, and defined by the indefinite fault definition means. The indefinite fault simulation means for determining to which observation point an indefinite value is output due to the indefinite fault, and the indefinite values for the observation points in which all the errors have been generated by the indefinite fault simulation means with respect to the pattern in which an error has occurred due to the test. If it is detected, it is judged that there is a possibility that it is the cause of the error. A suspected failure gate determination means for determining that there is no possibility of error cause when at least one error-free observation point is detected by the indefinite failure simulation means with respect to the generated pattern. 0 for the output of the suspected failure gate
Stuck-at fault defining means for defining stuck-at fault and 1 stuck-at fault,
Using the test pattern used in the test, the input value and output value of the gate in the normal case and the input value and output value of the gate in the case of the fault defined by the stuck-at fault defining means are obtained, and the suspected fault A stuck-at fault simulation means for determining at which observation point the stuck-at fault defined in the output of the gate is detected, and a case where a failure is detected at the stuck-at fault simulation means for an observation point that does not generate an error by the test. It is estimated that the output value of the suspected failure gate is the same as the output value of the gate in the normal case obtained by the stuck-at fault simulation means, and the stuck-at fault simulation is performed on the observation point where an error occurs in the test. When a failure is detected by the means, the output value of the suspected failure gate is Gate output value estimating means for estimating that the output value of the gate in the normal case obtained by the stuck-at fault simulation means is the opposite value; A truth table for creating a truth table of the suspected failure gate from a combination of an input value and an output value of the gate estimated by the gate output value estimating means, and a truth for removing a gate having a contradiction in the truth table from the suspected failure gate. And a value table creating means.

[0016]

According to the first aspect of the present invention, not only does the fault simulation result of the stuck-at fault defined by the suspected fault gate determination means completely match the test result of the tester, but an error occurs due to a fault inside the gate. By leaving the gate that may be detected as the suspicious failure gate, not only the stuck input / output failure of the gate but also the failure inside the gate is diagnosed. Further, in the second aspect of the present invention, by deciding the suspected failure gate based on the result of failure simulation assuming a failure in which the output of the suspected failure gate becomes indefinite, an arbitrary failure in which the operation of the gate changes due to a failure inside the gate Diagnose. According to the third invention, the truth value table is created by estimating the output value of the suspected failure gate based on the result of the failure simulation, so that the truth table in the failure circuit can be applied to the failure in which the operation of the gate is changed by the failure inside the gate. To diagnose the failure.

According to the present invention, a failure simulation is performed for each test pattern without creating a failure dictionary in advance, and the suspected failure gate is narrowed down step by step by referring to the test result by the tester. Keep it low.

According to the present invention, all gates within the specified range of the circuit are set as the initial values of the suspected failure gate without the designer estimating the suspected failure location in advance, or an error is detected in the test result by the tester. The circuit is traced from the observed point to the input side, and the fault is diagnosed by using the gate in the traced range until reaching the input end of the logic integrated circuit as the initial value of the suspected fault gate, and Even a person who is not familiar with it can easily diagnose a failure.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the failure diagnosis system of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the fault diagnosis system according to the first embodiment of the present invention includes a stuck-at fault defining means 11 for defining a stuck-at-0 fault or a stuck-at-1 fault with respect to the output of the suspected fault gate 17. Stuck-at fault simulation means 12 for performing a failure simulation, suspected-fault gate determination means 13 for determining whether a gate in which a stuck-at fault is defined can cause an error, and diagnostic result display means 15 for displaying a diagnostic result 16. Is included.

The inspection result 3 stores error information obtained by comparing the output response of the circuit under test 101 given the test pattern 2 via the tester 100 and the expected output value of the test pattern 2. There is. First, the stuck-at fault definition means 11 inputs the logical connection data 1 of the circuit under test 101 and refers to the suspected fault gate 17 to define a stuck-at-0 fault or a stuck-at-1 fault at the output of each suspected fault gate. Here, the stuck-at-0 failure is a failure that fixedly becomes "0", and the stuck-at-1 failure is a failure that fixedly becomes "1". The definition performed by the stuck-at fault definition means 11 is tentative and is canceled according to the subsequent procedure.

Next, the stuck-at fault simulation means 12
Inputs the test pattern 2, and the stuck-at fault definition means 11
A stuck simulation is performed for the stuck-at faults defined by to find at which observation point each stuck-at fault is detected.

The suspected failure gate determination means 13 tests the stuck-at fault defined by the stuck-at fault definition means 11 to the tester 100.
If the condition that the error is detected at the observation point as a result of the test by and the detection is not performed at the observation point that is not an error in the error pattern is satisfied, the gate in which the stuck-at fault is defined may cause an error. Then, this gate is output to the suspected failure gate 17. Otherwise, if it is not detected at an observation point that results in an error in the test, or if it is detected at an observation point that is not an error in the error pattern, the gate in which the stuck-at fault is defined does not cause an error. Then, this gate is deleted from the suspected failure gate 17.

As the judgment 14 of the end of diagnosis, there is still an errored test pattern, and many gates remain as the suspected failure gate 17, and it is judged that the suspected failure location can be narrowed down. To return to the stuck-at fault definition means 11, the above process is repeated.
On the other hand, the error test pattern disappears or the suspected failure gate 17 has a sufficiently small number, for example, 1
If the failure points can be narrowed down to the points, the diagnosis result display means 15 allows the suspected failure gate 17 to display the diagnosis result 1
Display as 6.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to FIGS.

Referring to FIG. 2, an exclusive OR circuit (hereinafter referred to as an XOR circuit or an XO circuit) formed of a CMOS logic circuit.
In the circuit diagram of (R gate), the XOR circuit 20 is composed of PMOS transistors 21 to 25, NMOS transistors 26 to 30, and wiring between them. In FIG. 2, consider a case where a failure location 31 marked with an X is fixed to 0 due to a short circuit with the ground wiring or the like. Output Y when input A = 1 and input B = 1
Will be 0 if normal, but will be 1 due to a failure. For other inputs, the XOR circuit 20 outputs the same value as a normal circuit. Therefore, at the gate level, neither the 0 stuck-at fault nor the 1 stuck-at fault occurs at the gate input / output, and the gate behaves like an OR gate.

Referring to FIG. 3, in the example of the logic circuit including the XOR gate having an internal fault (hereinafter referred to as a fault gate) shown in FIG. 2, the logic circuit 40 has a normal XOR gate 4
1. A failure gate 42 whose logic has changed from an exclusive OR to a logical OR due to a failure, and a normal AND gate (hereinafter, AND gate).
43) and a normal OR gate (hereinafter,
It includes an OR gate) 44.

Referring to FIG. 4, there is shown a result of performing a test by applying the test pattern 2 to the logic circuit 40 of FIG. The test is conducted using five test patterns,
When the output F for the test pattern of pattern number "2" is "0" as an expected value in the case of a normal circuit, "1" is output in the fault circuit and an error occurs, and for the test pattern of pattern number "5". When the output E is "0" as the expected value in the case of the normal circuit, "1" is output in the faulty circuit, which is an error.

With reference to FIGS. 3 and 4, it is shown that the conventional failure diagnosis method for only the stuck-at fault of the input / output of the gate fails in narrowing down the failure point. Then, it is shown that the failure diagnosis method of the present invention enables narrowing down of failure points.

First, in the conventional fault diagnosis method for stuck-at faults, 0 stuck-at fault and 1 stuck-at fault are defined at the input and output of each gate. Next, failure simulation is performed using the test pattern, and only failures in which the defined failure detection status and the error result of the test result match are left as suspected failures. When the failure simulation is performed using the test pattern of the pattern number “1” of FIG. 4 in the circuit of FIG.
A total of 10 failures including 1 failure of the input / output of the R gate 41, 1 failure of the input / output of the failure gate 42, 1 failure of the output of the AND gate 43, and 1 failure of the input / output of the OR gate 44 are detected, and the test result is obtained. Since there are no errors in the above, these failures are excluded as inconsistencies. When a fault simulation is performed on the remaining stuck-at faults using the test pattern of the pattern number “2”, two 0 faults at the input of the XOR gate 42 are detected at the output F, and since there is an error at F, this 2 Only individual failures remain as suspected failures. When the failure simulation is performed with the test pattern of the pattern number “3”, the 0 failure at the first input of the failure gate 42 is detected at the output F, and when the failure simulation is performed with the test pattern of the pattern number “4”, the failure gate 42 2-input 0
A fault is detected at the output E, but since neither test pattern has an error, the two faults are deleted as a mismatch with the test result. As a result, all the stuck-at faults defined at the beginning are deleted, the suspected faults disappear, and the fault diagnosis fails.

Next, the operation of the fault diagnosis system of the present invention will be described. First, the XOR gate 41, the failure gate 42, A
Only the outputs of the ND gate 43 and the OR gate 44 define the stuck-at-0 fault and the stuck-at-1 fault. Next, a stuck-at fault simulation is performed using the test pattern. Since the test pattern with the pattern number “1” has no error, all the gates are left as they are as the suspected failure gate. In the test pattern of the pattern number "2", the AND gate 4
One failure of the output of 3 is detected at the output E, and one failure of the output of the other gate is detected at the output F. Output F with error
XOR gate 41, fault gate 42, and OR gate 4 having a fault detected by
4 remains as the suspected failure gate.

Next, a stuck-at-0 fault and a stuck-at-1 fault are defined again for the outputs of the remaining three gates, and the stuck-at fault simulation is performed by the following test pattern. In the test patterns of the pattern numbers “3” and “4”, there is no error, and therefore the suspected failure gate does not change. As a result of the stuck-at fault simulation using the test pattern of the pattern number “5”, one fault of the output of the fault gate 42 is detected at the output E, and XO
Output 0 of R gate 41 and OR gate 44 is output F
Detected in. As a result, only the fault gate 42 having a fault that is detected at the erroneous output E and not at the error-free output F remains as the suspected fault gate. In this way, it is possible to successfully narrow down the gates that actually have a failure.

In the first embodiment, as in the conventional method, 0 and 1 stuck-at faults are defined and a fault simulation is carried out. However, this is because the stuck-at fault only is diagnosed. Instead, it is performed to determine whether or not the fault signal propagates from the output of the suspected fault gate to the observation point where the error is observed. That is, the difference from the conventional method is that the suspicious failure gate is determined only by using the error pattern, the failure is defined only in the output of the suspicious failure gate and not in the input, and 0 failure and 1 failure each time. Both of these are defined.
The judgment of the suspected failure gate using only the error pattern is because the output value of the failure gate is not always fixed for failures other than the stuck-at failure, and the normal pattern may have the same output value as the normal circuit. This is because there is a risk that even a fault of a gate that actually has a fault may be deleted in the conventional method that deletes a pattern detected as a normal pattern as a mismatch. A fault is defined only for the output of the suspected fault gate when the output value of the fault gate is normal in the error pattern even if the actual fault location of the faulty gate is inside the gate or at the gate input. It should show a value different from the value of, and determine whether the failure signal propagates from the output of the failure gate to the observation point where the error is observed by determining whether the failure of the output of the gate is detected. This is because it can be determined.

As a result, the time required for the failure simulation can be greatly shortened as compared with the conventional method in which the failure is defined for all inputs and outputs of the gate and the failure simulation is performed. In the conventional diagnostic method, a fault that does not match the error pattern once and is deleted is never simulated again. On the other hand, the diagnostic method of the present invention provides both 0 and 1 faults in the output of the suspected failure gate. Depending on the type of failure inside the gate, the failure simulation is performed by defining "1" for a normal value "0" and "0" for a normal value "1". Because it can be considered. If a normal value "0" becomes "1" due to a failure in a certain error pattern, one failure of the output of the failure gate is detected and 0
No fault is detected. If another error pattern causes "0" with respect to the normal value "1" due to a failure, 0 failure of the output of the failure gate is detected and 1 failure is not detected. Therefore, by defining both 0-fault and 1-fault in the output of the suspected fault gate every time and performing the stuck-at fault simulation, the route from the fault gate to the observation point where the error is observed is activated by detecting either fault. It can be determined that it has become.

In this way, the normal diagnostic value cannot be narrowed down by the conventional diagnostic method, and the normal value "0" becomes "1" and the normal value "1" becomes "0". It is possible to narrow down even such a failure, and the accuracy of diagnosis can be improved.

Next, a second embodiment of the fault diagnosis system of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 5, the failure diagnosis system according to the second embodiment of the present invention includes an indefinite failure defining means 61, an indefinite failure simulation means 62, a suspected failure gate determining means 63, and a diagnosis result displaying means 65. Is included.

The logical connection data 1, the test pattern 2, the tester 100, the circuit under test 101, and the inspection result 3 are
This is similar to that described in the first embodiment.

First, the indefinite fault definition means 61 inputs the logical connection data 1 of the circuit under test 101, refers to the suspected fault gate 67, and outputs the output of each suspected fault gate whose fault value becomes indefinite. Is defined.

Next, the indefinite fault simulation means 62
Inputs the test pattern 2, and the indefinite fault definition means 61
A fault simulation is performed on the indefinite fault defined by ## EQU1 ## to find at which observation point the indefinite fault appears.

The suspicious failure gate determination means 63 uses the undefined failure defined by the undefined failure definition means 61 to determine the tester 1
When the indefiniteness occurs at all the observation points in which the error of each test pattern is an error as a result of the test by 00, it is determined that the gate in which the indefinite fault is defined may cause the error, and the suspected failure gate 67 Output. If no indefiniteness occurs at any other errored observation point, it is determined that the gate in which the indefinite fault is defined does not cause the error and is not output to the suspected failure gate 67.

In the diagnosis end judgment 64, the errored test pattern still remains, and many gates still remain as the suspected failure gate 67, and it is judged that the suspected failure location can be narrowed down. If it does, the process returns to the indefinite fault definition means 61 again and the above process is repeated. On the other hand, if the errored test pattern disappears, or if the number of suspected failure gates 67 is sufficiently small, for example, the failure points can be narrowed down to one, the suspected failure gate 67 is displayed by the diagnostic result display means 65. Is displayed as the diagnosis result 66.

Next, the operation of the second embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

First, an indefinite fault is defined at the outputs of the XOR gate 41, the fault gate 42, the AND gate 43, and the OR gate 44 in FIG. Next, failure simulation is performed using the test pattern. Since there is no error in the test pattern with the pattern number “1”, all gates remain as suspected failure gates. In the test pattern of the pattern number “2”, the output F having an error becomes indefinite due to the indefinite failure of the outputs of the XOR gate 41, the failure gate 42, and the OR gate 44, and therefore these gates remain as the suspected failure gates, and the output F becomes An undetermined AN
The D gate 43 is deleted from the suspected failure gate. In the test patterns of the pattern numbers “3” and “4”, since there is no error, the suspected failure gate does not change. In the last test pattern of the pattern number “5”, the failure gate 42
Since the output E having an error becomes indefinite due to the indefinite fault of the output of the above, and the output E does not become indefinite with the indefinite fault of the outputs of the other two gates, only the fault gate 42 remains as the suspected fault gate. In this way, it is possible to successfully narrow down the gate that actually has a failure.

In the second embodiment, unlike the conventional method, an indefinite fault is defined and a fault simulation is performed. If the fault gate operates abnormally and is observed as an error at the observation point of the circuit, the result of the fault simulation in which the output of the fault gate is indefinite should always give an indefinite output at the observation point where the error occurred. is there. If a fixed value of "0" or "1" is output at the observation point that resulted in an error as a result of the failure simulation, it was an error regardless of the value of the output of the gate that defined the indefinite failure. This means that the observation point is not affected, and it can be determined that the gate is not a fault gate. This holds even if the failure gate performs any operation other than fixed to 0 and fixed to 1. Therefore, unlike the conventional failure diagnosis method, it is possible to narrow down failures other than the stuck-at failure.

Next, a third embodiment of the fault diagnosis system of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 6, the fault diagnosis system according to the third embodiment of the present invention includes a stuck-at fault definition means 71, a stuck-at fault simulation means 72, a gate output value estimation means 73, a truth table creation means 74, It also includes diagnostic result display means 76.

The logical connection data 1, the test pattern 2, the tester 100, the circuit under test 101 and the inspection result 3 are the first
This is the same as that described in the embodiment.

First, the stuck-at fault definition means 71 inputs the logical connection data 1 of the circuit under test 101, and refers to the suspected fault gate 78 to define 0 stuck-at fault and 1 stuck-at fault at the output of each suspected fault gate. .

Next, the stuck-at fault simulation means 72.
Inputs the test pattern 2 and stuck-at fault definition means 71
A stuck simulation is performed for the stuck-at faults defined by to find at which observation point each stuck-at fault is detected. That is, the input value and the output value of the gate in the normal case using the test pattern 2 (hereinafter referred to as the normal value)
Furthermore, the input value and the output value of the gate when there is a fault defined by the stuck-at fault definition means 71 are determined. Then, it is determined at which observation point the stuck-at fault defined in the output of the suspected failure gate is detected.

The gate output value estimating means 73 estimates that the output value of the suspected failure gate in the test pattern is the same as the normal value when the stuck-at fault is detected in a test pattern which is not an error. Further, when the stuck-at fault is detected at the observation point where the error of the error pattern is detected, it is estimated that the output value of the suspected fault gate in the test pattern is a value opposite to the normal value. Normal value is "0"
If so, the estimated value is "1", and if the normal value is "0", the estimated value is "1". Further, when the stuck-at fault is simultaneously detected at the observation point where the error of the error pattern is an error and the observation point where the error of the same error pattern is not detected, it is estimated that the output value of the suspected failure gate in the test pattern is an indefinite value. . This means that the suspected failure gate is inconsistent with the true failure gate.

Next, the truth table creating means 74 is based on the normal value of the input value of the suspected failure gate in each test pattern and the output value of the suspected failure gate estimated by the gate output value estimating means 73. A truth table of the suspected failure gate is created. At this time, if the estimated output value of the suspected failure gate is an indefinite value, the suspected failure gate is deleted from the suspected failure gate 78 because the truth table has a contradiction. Also,
Even if the output value of the suspected fault gate estimated by the previous test pattern and the output estimated value of the suspected fault gate for the same input value estimated by another test pattern are different, it is considered that the truth table is inconsistent. The suspected failure gate is deleted from the suspected failure gate 78.

In the determination 75 of the end of diagnosis, the test pattern for which the failure simulation has not been performed still remains, and many gates still remain as the suspected failure gate 78, and it is possible to further narrow down the suspected failure location. If it is determined, the process returns to the stuck-at fault definition means 71 again, and the above process is repeated. On the other hand, if the processing is completed for all the test patterns or if the number of suspected failure gates 78 is sufficiently small, for example, the failure location can be narrowed down to one, the diagnostic result display means 76 causes the suspected failure gate 78 and the suspected failure gate truth. The value table 79 is displayed as the diagnosis result 77.

Next, the operation of the third embodiment of the present invention will be described in detail with reference to FIGS.

Referring to FIG. 7, there is shown an example of a logic circuit including an XOR gate having an internal fault of FIG. 2, and a logic circuit 80 has a fault gate 81 whose logic changes from an exclusive OR to a logical OR due to a fault and a normal gate. It consists of an AND gate 82.

Referring to FIG. 8, there is shown a result of performing a test by applying a test pattern to the logic circuit 80 of FIG. The test is performed by using eight test patterns. Only in the test pattern with the pattern number “8”, when the expected value of the normal circuit of the output Y becomes “0”, “1” is output in the faulty circuit and an error occurs. Has become.

First, the fault gate 81 in the logic circuit 80.
And a stuck-at-0 fault and a stuck-at-1 fault are defined at the output of the AND gate 82. Next, failure simulation is performed using the test pattern with the pattern number “1”. As a result,
A stuck-at-1 fault in the output of AND gate 82 is detected at output Y. Since there is no error in this pattern, the gate output value estimation means 73 estimates the output value of the AND gate 82 to be 0, which is the same as the normal value. The truth table creating means 74 uses A
The combination of the input value (0,0) of this pattern of the ND gate 82 and the estimated value 0 of the output value is output to the suspected failure gate truth table 79. It returns to the first stuck-at fault definition means 71 again.

Next, a fault simulation is performed using the test pattern of pattern number "2". As a result, the stuck-at-1 fault at the output of the fault gate 81 and the stuck-at-1 fault at the output of the AND gate 82 are detected at the output Y. Since there is no error in this pattern, the gate output value estimating means 7
3, the output value of the failure gate 81 and the AND gate 82
The output value of is estimated to be 0, which is the same as the normal value. The truth table creating means 74 outputs the estimated value 0 of the input value (0,0) and the output value of the failure gate 81 in this pattern, and the input value (0,1) and the output of the AND gate 82 in this pattern. The combination of the estimated values 0 is output to the suspected failure gate truth table 79. Both are consistent as the combination of the input value and the estimated value of the output value already output to the suspected failure gate truth value table 79, and thus both remain as the suspected failure gate.

Similarly, in the test pattern of the pattern number "3", the combination of the input value (1, 0) of the AND gate 82 and the estimated value 0 of the output value is output to the suspected failure gate truth value table 79, and the pattern number "3" is output. 4 ”test pattern, the combination of the input value (0, 1) of the failure gate 81 and the estimated value 1 of the output value, and the input value (1, 1) of the AND gate 82
And the estimated value 1 of the output value are output to the suspected failure gate truth value table 79. In the test pattern of the pattern number “5”, the output value is estimated to be 0 with respect to the input value (1,0) of the AND gate 82. This is the truth that is already output in the test pattern of the pattern number “3”. The suspicious failure gate truth value table 79 does not change because it matches the combination of the value tables.

Similarly, pattern numbers "6" and "7"
The combination of the input value and the estimated value of the output value of the AND gate 82 obtained by the test pattern of No. 1 matches the combination of the truth table obtained by the test patterns of the pattern numbers "4" and "1", respectively. Further, from the test pattern with the pattern number 6, the combination of the input value (1, 0) of the failure gate 81 and the estimated value 1 of the output value is added to the suspected failure gate truth value table 79.

Finally, in the test pattern of the pattern number "8", the stuck-at-1 fault of the output of the fault gate 81 and the stuck-at-1 fault of the output of the AND gate 82 are detected at the output Y, but the circuit under test has an error in this pattern. Therefore, the gate output value estimation means 73 estimates that the output values of the failure gate 81 and the AND gate 82 are “1” which is the opposite of the normal value. Since the combination of the input value (1, 1) of the failure gate 81 and the estimated value “1” of the output value does not contradict the truth table up to this point, it is added to the failure gate truth value table 79.

On the other hand, the input value (0,
The combination of 1) and the estimated value of the output value “1” is the input value (0, 1) obtained from the test pattern of the pattern number “2”.
Since this is inconsistent with the combination of the estimated value “0” of the output value,
The AND gate 82 is determined to be not the failure gate and is deleted from the suspected failure gate 78. Now that all the test patterns have been completed, the diagnostic result display means 76 displays the fault gate 81 and its truth table as the diagnostic result 77.

Referring to FIG. 9, in the example of the truth table displayed as the diagnosis result 77, the combination of the input value and the output value of the failure gate 81 finally diagnosed as the suspected failure gate is shown in a table format. It is displayed. As a result, the output value when the input value is originally (1, 1) should be "0", but becomes "1", and the exclusive OR gate operates as a logical sum. I understand. In this way, it is possible to narrow down the gates that actually have a failure, and at the same time, to estimate how the gate will operate due to the failure.

In the third embodiment, similarly to the first embodiment, the stuck-at fault is defined in the output of the suspected fault gate, the fault simulation is performed, and the fault location is narrowed down. The difference from the embodiment of FIG. 1 is that the result is narrowed down also by using the result of the failure simulation with a test pattern that is not an error. As a result, it may be possible to further narrow down the failures that cannot be narrowed down in the first embodiment.

For example, in the case of performing the failure diagnosis from the circuit of FIG. 7 and the result of FIG. 8, the failure diagnosis method according to the first embodiment determines only the test pattern of the pattern number “8” which is the error pattern. In this test pattern, one failure of the output of the failure gate 81 and one failure of the output of the AND gate 82 are detected in the output Y, so both are determined to be the suspected failure gate. As described above, in the third embodiment, there is an increase in the processing of processing all test patterns including a test pattern that is not an error and creating a truth table, but it is characterized by good narrowing accuracy.

Next, a fourth embodiment of the fault diagnosis system of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 10, in the failure diagnosis system according to the fourth embodiment of the present invention, suspected failure gate setting means 120, stuck-at failure definition means 11, stuck-at failure simulation means 12, suspected failure gate determination means 13 are shown. , Stuck-at fault definition means 71, stuck-at fault simulation means 72, gate output value estimation means 73, truth value table creation means 74, and
The diagnostic result display means 76 is included.

Stuck-at fault definition means 11, stuck-at fault simulation means 12, and suspected fault gate determination means 13
Is the same as each means in the first embodiment. Also,
Stuck-at fault definition means 71, stuck-at fault simulation means 72, gate output value estimation means 73, truth table creation means 7
4 and the diagnostic result display means 76 are the same as the respective means in the third embodiment. The logical connection data 1, the test pattern 2, the tester 100, the circuit under test 101, and the inspection result 3 are the same as those described in the first embodiment.

First, the gate within the range manually designated by the suspected failure gate setting means 120 is set as the initial value of the suspected failure gate 17. As a method of manually specifying, the entire circuit under test is specified as a range, the instruction decoding circuit or the arithmetic circuit is specified as a part that functionally separates the circuit inside the circuit under test, and the part other than the memory is in the circuit under test. Such as specifying a range other than the specific part of
The designer etc. can easily specify.

Next, using the suspected failure gate 17 set by the suspected failure gate setting means 120 as the initial value of the suspected failure gate, the stuck-at fault definition means 11, the stuck-at fault simulation means 12, and the suspected failure gate determination means 13 are set.
The first stage failure diagnosis is performed by. This procedure is similar to that described in the first embodiment 1. The suspected failure gate 17 obtained as a result is used as the initial value of the suspected failure gate 78 in the failure diagnosis of the second step, and the failure diagnosis of the second step is performed.

The procedure of the second stage failure diagnosis is the same as that described in the third embodiment. In the failure diagnosis according to the third embodiment, there is a possibility that the suspected failure gate can be narrowed down to a narrower range, although the processing amount is larger than that in the failure diagnosis according to the first embodiment. Therefore, first, the failure point is narrowed down by the diagnosis method of the first embodiment, and then the failure point is narrowed down by the same diagnosis method as the third embodiment, thereby reducing the entire processing time and It is possible to narrow down faulty parts with extremely high accuracy.

In the fourth embodiment, the first embodiment and the third embodiment are combined, but the same effect can be obtained by combining the second embodiment and the third embodiment. To be
In addition, in the first stage failure diagnosis, the suspected failure gate is 1
The second stage failure diagnosis may be omitted when the number is narrowed down.

Next, a fifth embodiment of the fault diagnosis system of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 11, the failure diagnosis system according to the fifth embodiment of the present invention includes the suspicious failure gate setting means 120 and the circuit tracing means 130 in the fourth embodiment.
It has been replaced with. Circuit trace means 13
0 refers to the inspection result 3 and follows the circuit from the observation point where an error is detected as a result of the test toward the input side of the circuit (hereinafter, this operation is referred to as trace). When tracing is performed until the input terminal of the circuit under test 101 is reached, the gate in the traced range is set as the initial value of the suspected failure gate 17. The subsequent procedure is the same as in the fourth embodiment.

In the fifth embodiment, the location where the actual failure exists must be on the input side of the observation point where the error is detected, and the range of the suspected failure gate should be limited beforehand by the trace of the circuit. You can In particular, when it is difficult for the designer to specify the functional suspect range, the processing time required for diagnosis is greatly reduced compared to performing fault diagnosis using all gates in the circuit under test as initial values of the suspected fault gate. The effect is that you can do it.

[0076]

As is apparent from the above description, according to the present invention, not only the stuck-at fault of the input / output of the gate but also the fault inside the gate can be diagnosed. And
As a result, the rate of succeeding in narrowing down the failure location is increased. This is because the actual failure rate is high inside the gate, not in the gate input / output or the wiring between the gates.

Further, according to the present invention, by simulating only the output failure of the suspected failure gate in the failure simulation for failure diagnosis, the number of failures to be simulated can be significantly reduced and the processing time required for failure diagnosis can be reduced. can do. Then, this facilitates failure diagnosis even for a large-scale circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a failure diagnosis system of the present invention.

FIG. 2 is a diagram showing an example of an exclusive OR circuit (fault gate) having a fault inside.

FIG. 3 is a diagram showing an example of a logic circuit including a failure gate.

FIG. 4 is a diagram showing an example of a result when a test is performed by applying a test pattern to a logic circuit.

FIG. 5 is a block diagram showing a second embodiment of the failure diagnosis system of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the failure diagnosis system of the present invention.

FIG. 7 is a diagram showing another example of a logic circuit including a failure gate.

FIG. 8 is a diagram showing another example of a result when a test is performed by giving a test pattern to a logic circuit.

FIG. 9 is an example of a truth table of a failure gate obtained as a result of failure diagnosis of a logic circuit.

FIG. 10 is a block diagram showing a fourth embodiment of the failure diagnosis system of the present invention.

FIG. 11 is a block diagram showing a fifth embodiment of the failure diagnosis system of the present invention.

[Explanation of symbols]

 1 logical connection data 2 test pattern 3 inspection result 11 stuck-at fault definition means 12 stuck-at fault simulation means 13 suspected failure gate determination means 14 diagnostic end determination 15 diagnostic result display means 16 diagnostic result 17 suspected failure gate 20 XOR circuits 21-25 PMOS transistors 26-30 NMOS transistor 31 Failure point 40 Logic circuit 41 XOR gate 42 Failure gate 43 AND gate 44 OR gate 51 Pattern number 52 Input value 53 Expected value 54 Output value 55 Error 56 Error observation point 61 Uncertain fault definition means 62 Uncertain fault simulation Means 63 Suspicious failure gate determination means 64 Diagnosis end determination 65 Diagnosis result display means 66 Diagnosis result 67 Suspected failure gate 71 Stuck-at failure definition means 72 Stuck-at failure simulation means 73 Game Output value estimation means 74 Truth table creation means 75 Diagnosis end judgment 76 Diagnosis result display means 77 Diagnosis result 78 Suspected failure gate 79 Suspected failure gate truth table 80 Logic circuit 81 Failure gate 82 AND gate 91 Pattern number 92 Input value 93 Expected Value 94 Output value 95 Error 100 Tester 101 Circuit under test 111 Input value of truth table 112 Output value of truth table 120 Suspected failure gate setting means 130 Circuit tracing means

Claims (7)

[Claims] 1. A stuck-at fault for defining 0 stuck-at faults and 1 stuck-at faults at an output of a suspected failure gate in a fault diagnosis system for a logic circuit that diagnoses a fault of the logic circuit based on a result of a test of a function level of the logic circuit. Defining means, a stuck-at fault simulation means for performing a fault simulation using the test pattern used in the test, and determining at which observation point the stuck-at fault defined by the stuck-at fault defining means is detected; When a fault is detected by the stuck-at fault simulation means with respect to an observation point where an error has occurred, it is determined that there is a possibility of an error cause, and the observation point that does not cause an error in the pattern in which the error occurs by the test is described above. An error occurs when a failure is detected by the stuck-at failure simulation means. A fault diagnosis system for a logic circuit, comprising: a suspicious fault gate determination means for determining that there is no possibility of a cause. 2. In a logic circuit failure diagnosis system for diagnosing a failure of a logic circuit based on a result of a test of a function level of the logic circuit, a failure whose value at the time of failure is undefined is defined in an output of a suspected failure gate. An indefinite fault definition means and an indefinite fault simulation means for performing a fault simulation using the test pattern used in the test, and determining to which observation point an indefinite value is output by the indefinite fault defined by the indefinite fault definition means. And, if an indeterminate value is detected for all observation points that have generated errors by the indefinite fault simulation means with respect to the pattern in which an error has occurred by the test, it is determined that there is a possibility of an error cause, and by the test, At least one of the indefinite fault simulation means for the pattern in which an error has occurred 2. A fault diagnosis system for a logic circuit, comprising: a suspicious fault gate determination unit that determines that there is no possibility of an error cause when an observation point that has caused an error is detected that is not an indefinite value. 3. A stuck-at fault in which a 0 stuck-at fault and a 1 stuck-at fault are defined at the output of a suspected fault gate in a fault diagnosis system for a logic circuit that diagnoses a fault in the logic circuit based on a result of a test of a function level of the logic circuit. Using the defining means and the test pattern used in the test, determine the input value and output value of the gate in the normal case and the input value and the output value of the gate in the case of the fault defined by the stuck-at fault defining means. A stuck-at fault simulation means for determining at which observation point a stuck-at fault defined in the output of the suspected failure gate is detected, and a failure detected by the stuck-at fault simulation means for an observation point at which no error occurs by the test. The output value of the suspected failure gate is obtained by the stuck-at failure simulation means. It is estimated that the output value of the gate in the normal case is the same, and when a failure is detected by the stuck-at failure simulation means at the observation point where an error occurs in the test, the output value of the suspected failure gate is A gate output value estimating means for estimating that the output value of the gate in the normal case obtained by the stuck-at fault simulation means is the opposite value, and a gate when there is the failure obtained by the stuck-at fault simulation means. A truth table for creating a truth table of the suspected failure gate from a combination of an input value and an output value of the gate estimated by the gate output value estimating means, and a truth for removing a gate having a contradiction in the truth table from the suspected failure gate. A fault diagnosis system for a logic circuit, comprising: a value table creating means. 4. A failure diagnosis system for a logic integrated circuit, which diagnoses a failure of a logic circuit based on a result of a test of a function level of the logic circuit, wherein an initial value of a suspicious failure gate in the logic circuit is manually set. Suspicious failure gate setting means, stuck-at fault defining means for defining 0 stuck-at faults and 1 stuck-at faults at the output of the suspected-failure gate, and fault simulation using the test pattern used in the test. A stuck-at fault simulation means for determining at which observation point a defined stuck-at fault is detected, and if a failure is detected by the stuck-at fault simulation means for an observation point at which an error has occurred by the test, an error cause is possible. There is an error in the pattern in which the When a fault is detected by the stuck-at fault simulation means for an observation point that does not occur, a suspected-fault gate determination means for determining that there is no possibility of an error cause, and a stuck-at-0 fault and a stuck-at-1 fault at the output of the suspected-fault gate. A stuck-at fault defining means that defines the input value and output value of the gate in the normal case using the test pattern used in the test, and an input value of the gate when there is a fault defined by the stuck-at fault defining means, and A stuck-at fault simulation means for determining an output value and determining at which observation point the stuck-at fault defined in the output of the suspected-fault gate is detected, and the stuck-at fault for an observation point that does not generate an error by the test. When a failure is detected by the simulation means, the output value of the suspected failure gate is the stuck-at failure. It is presumed that the output value of the gate in the normal case obtained by the simulation means is the same, and if a fault is detected by the stuck-at fault simulation means at the observation point at which an error has occurred in the test, the suspected fault is detected. Gate output value estimating means for estimating that the output value of the gate is the opposite value of the output value of the gate in the normal case obtained by the stuck-at fault simulation means, and the failure obtained by the stuck-at fault simulation means. If there is a gate input value and the output value of the gate estimated by the gate output value estimating means, a truth table of the suspected failure gate is created, and a gate having a contradiction in the truth table is suspected. A logic circuit fault diagnosis system comprising: a truth table creating means for removing from a fault gate. 5. In a failure diagnosis system for a logic integrated circuit, which diagnoses a failure of a logic circuit based on a result of a test of a function level of the logic circuit, an initial value of a suspected failure gate in the logic circuit is manually set. Suspicious failure gate setting means, undefined failure definition means for defining a failure in which the value at the time of failure is undefined in the output of the suspected failure gate, and failure simulation by using the test pattern used in the test, and the undefined failure definition An indefinite fault simulation means for determining to which observation point an indefinite value is output by an indefinite fault defined by means, and an observation point at which all the errors have been generated by the indefinite fault simulation means with respect to the pattern in which an error has occurred by the test. If an indefinite value is detected for, it is determined that there is a possibility of error and If a non-indeterminate value is detected for at least one observing point at which an error has occurred by the test with respect to the pattern in which an error has occurred in the test, it is determined that there is no possibility of an error cause. Means, a stuck-at fault defining means for defining 0 stuck-at faults and 1 stuck-at faults at the output of the suspected fault gate, input values and output values of the gate in the normal case using the test pattern used in the test, and the stuck-at fault A stuck-at fault simulation for determining an input value and an output value of a gate when there is a fault defined by the defining means and determining at which observation point the stuck-at fault defined at the output of the suspected fault gate is detected. Means and the stuck-at fault simulation for an observation point that does not generate an error by the test When a failure is detected by the means, it is estimated that the output value of the suspected failure gate is the same as the output value of the gate in the normal case obtained by the stuck-at failure simulation means, and an error is generated by the test. When a failure is detected by the stuck-at fault simulation means with respect to the observed point, the output value of the suspected failure gate is a value opposite to the output value of the gate at the normal time obtained by the stuck-at fault simulation means. And a gate output value estimating means for estimating the suspected combination based on a combination of the gate input value when the fault is obtained by the stuck-at fault simulation means and the gate output value estimated by the gate output value estimating means. Create a truth table for fault gates and remove gates with conflicting truth tables from suspected fault gates A fault diagnosis system for a logic circuit, comprising: 6. A failure diagnosis system for a logic circuit for diagnosing a failure of the logic circuit based on a result of a function level test of the logic circuit, wherein from an observation point where an error is detected in the test result toward an input side of the circuit. Circuit trace means for tracing a circuit and defining a gate within a range traced until reaching an input terminal of the logic circuit as an initial value of a suspicious failure gate, and defining a stuck-at-0 fault and a stuck-at-1 fault at the output of the suspicious failure gate A stuck-at fault definition means, a stuck-at fault simulation means for performing a fault simulation using the test pattern used in the test, and obtaining at which observation point the stuck-at fault defined by the stuck-at fault definition means is detected, A fault is detected by the stuck-at fault simulation means at an observation point where an error has occurred in the test. If a failure is detected by the stuck-at fault simulation means with respect to an observation point that does not generate an error in the pattern in which an error has occurred by the test, the cause of the error is determined. Suspicious failure gate determination means for determining that there is no possibility, stuck-at fault definition means for defining 0 stuck-at faults and 1 stuck-at faults at the output of the suspected-failed gate, and a normal case using the test pattern used in the above test Input value and output value of the gate and the input value and output value of the gate when there is a fault defined by the stuck-at fault defining means, and which stuck-at fault defined at the output of the suspected fault gate is observed. Regarding stuck-at fault simulation means for determining whether or not it is detected at a point, and an observation point that does not generate an error by the test When a failure is detected by the stuck-at fault simulation means, it is estimated that the output value of the suspected-fault gate is the same as the output value of the gate at the normal time obtained by the stuck-at fault simulation means, and the test is performed. When a fault is detected by the stuck-at fault simulation means with respect to the observation point at which an error has occurred, the output value of the suspected-fault gate is the opposite of the output value of the gate in the normal case obtained by the stuck-at fault simulation means. A gate output value estimating means for estimating that the value is a value, an input value of the gate when there is the failure obtained by the stuck-at fault simulation means, and an output value of the gate estimated by the gate output value estimating means A truth table of the suspected failure gate is created from the combination, and a game with inconsistency in the truth table is created. And a truth table creating means for removing a fault from a suspected failure gate. 7. A failure diagnosis system for a logic circuit for diagnosing a failure of the logic circuit based on a result of a function level test of the logic circuit, wherein from an observation point where an error is detected in the test result toward an input side of the circuit. Circuit trace means for tracing the circuit and setting the gate in the range traced until reaching the input terminal of the logic circuit as the initial value of the suspicious failure gate, and a failure in which the value at the time of the failure is indefinite in the output of the suspicious failure gate An indefinite fault defining means and a test pattern used in the test are used to perform a failure simulation, and an indefinite fault is obtained to determine to which observation point an indefinite value is output by the indefinite fault defined by the indefinite fault defining means. The simulation means and the indefinite fault simulation means for the pattern in which the error is generated by the test If an indefinite value is detected for the observation point where the error occurs, it is determined that there is a possibility of an error cause, and at least one error is detected by the indefinite fault simulation means with respect to the pattern in which the error is generated by the test. Defines a suspected failure gate determination means that determines that there is no possibility of an error cause when a non-indeterminate value is detected for the generated observation points, and 0 stuck-at fault and 1 stuck-at fault at the output of the suspected failure gate. A stuck-at fault definition means, and an input value and an output value of the gate in the normal case using the test pattern used in the test, and an input value and an output value of the gate when there is a fault defined by the stuck-at fault definition means. Degradation for determining at which observation point the stuck-at fault defined in the output of the suspected failure gate is detected Failure simulation means, when the fault is detected by the stuck-at fault simulation means with respect to the observation point that does not generate an error by the test, the output value of the suspected failure gate is in the normal case obtained by the stuck-at fault simulation means. The output value of the gate is estimated to be the same as the output value of the gate, and when a failure is detected by the stuck-at fault simulation means at the observation point where an error occurs in the test, the output value of the suspected-fault gate is set at the stuck-at fault simulation means. And a gate output value estimating means for estimating that the output value of the gate in the normal case is the opposite value, and an input value of the gate when there is the failure obtained by the stuck-at fault simulation means and the A combination with the gate output value estimated by the gate output value estimation means And a truth table creating means for creating a truth table of the suspected failure gate from the combination and removing a gate having a contradiction in the truth table from the suspected failure gate.