JPH08304484A - Phase-detecting apparatus - Google Patents

Abstract

PURPOSE: To detect a voltage of a power source or a phase of a current without being influenced by a distortion of the voltage of the power source, by integrating an angular velocity output from an adding means and outputting an integrated value as a detection phase. CONSTITUTION: An output unit 18 outputs a preset angular velocity ωSET. An adder 21 adds a compensation value Δω to the angular velocity ωSET, and outputs an angular velocity of a power source. Then, an integrator 34 integrates the input angular velocity ω of the power source and outputs a voltage of the power source or a phase θ the same as a phase ϕ of a current, i.e., a detection phase. A frequency of the power source is set for every area, and the angular velocity ωSET of the power source at the area is input to the adder 21. Since the compensation value Δω is added to the angular velocity ωSET, if the detection phase θ is ahead of the phase ϕ of the power source, the ωis decreased. As a result, the detection phase θ is delayed to be equal to the phase ϕ of the power source. On the contrary, if the detection phase θ is behind the phase ϕ, the ω is increased, whereby the detection phase θ is advanced to be equal to the phase ϕ of the power source.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase detector for detecting the phase of a voltage or current of an AC power supply (referred to as power supply phase).

[0002]

2. Description of the Related Art FIG. 8 shows a hardware block diagram of a phase detection apparatus previously filed by the present applicant. In FIG. 8, φ is the power supply phase, Su, Sv, and Sw are detection signals of the voltage or current of each phase of the three-phase power supply,

[0003]

[Equation 1] Is.

Reference numeral 4 is an oscillator, and 5 is a counter for counting the clock of the oscillator 4. The count value θ of the counter 5 is cleared to 0 when it becomes 2π or more. 6 is
Outputs cos θ and sin θ based on the count value θ 2
Phase oscillators, 7 and 8 are multipliers, 9 and 10 are amplifiers with a gain of 1 / √3, and 11 and 12 are adders. As is clear from FIG.

[0005]

[Equation 2]

[0006]

(Equation 3) Becomes So ideally,

[0007]

[Equation 4]

[0008]

(Equation 5) Becomes

In FIG. 8, reference numeral 13 is a comparator, which outputs a binary signal S ₁₃ of "1" when the signal S ₁₂ is larger than 0 V and "0" in other cases. 14 is a latch circuit, 2
The count value θ is latched in synchronization with the rising of the value signal S ₁₃ . Here, when the binary signal S ₁₃ rises, S ₁₂
Since = 0, from Equation 5,

[0010]

(Equation 6)

[0011] At this time, θ = φ. Therefore, every time the binary signal S ₁₃ rises, a value equal to the power supply phase φ can be taken into the latch circuit 14.

[0012]

FIG. 9 shows a phase detected by the latch circuit 14 of FIG. 8 (referred to as a detection phase) φ1.
Also, the waveform of the power supply phase φ is shown. When the voltage of the power source is distorted, the signal S ₁₂ is distorted, and therefore the rising timing of the binary signal S ₁₂ is deviated. Therefore, a large distortion occurs in the detection phase φ ₁ . If there is no distortion in the power supply voltage, the detection phase φ
₁ is updated when the binary signal S ₁₃ rises and becomes equal to the power supply phase φ. However, even in this case, the binary signal S ₁₃
After rising, the error (called a phase error) Δφ between the power supply phase φ and the detection phase φ ₁ gradually increases. In particular, immediately before the binary signal S ₁₃ rises, the error (called a phase error) Δφ between the power supply phase φ and the detection phase φ ₁ becomes maximum.

An active power filter (harmonic compensator, detailed configuration is described in, for example, Japanese Patent Application No. 6-37946) by the detection phase φ ₁ having such a stepwise waveform.
It is described in. ), It is not possible to compensate for higher harmonics. Not only that, the detected phase φ ₁ has a phase error Δφ and changes abruptly in a stepwise manner, so that the active filter is a source of harmonic generation.

If the frequency of the oscillator 4 can be increased and the frequency (detection frequency) fs for detecting the power supply phase can be sufficiently increased, the problem of harmonics can be solved. However, at present, the frequency of the oscillator 4 is about 64 MHz at maximum.
Further, the resolution of the power supply phase, which has a trade-off relationship with the detection frequency of the power supply phase, requires at least about 14 bits. Therefore, the frequency that can be detected is 4 kHz at maximum according to the following equation. With the conventional phase detector, it is difficult to further increase the detection frequency.

[0015]

(Equation 7)

On the other hand, an IGBT is widely used at present as a main circuit element of an active filter for electric power.
The switching frequency of this IGBT is 20 KHz in recent years.
Is rising up to. Therefore, in order to sufficiently reduce the harmonics, it is necessary to obtain the power supply phase at a frequency that is four times or more the switching frequency of 20 KHz. That is,

[0017]

(Equation 8)

Must be Therefore, an object of the present invention is to provide a phase detection device capable of detecting the phase of the voltage or current of the power supply (power supply phase) without being affected by the voltage distortion of the power supply. Another object of the present invention is to provide a phase detection device that can obtain a power source phase at a higher frequency than conventional ones.

[0019]

In order to achieve such an object, the invention as set forth in claim 1 is a phase detecting device for detecting the phase of a power source and outputting the detected phase, which is predetermined. An output unit that outputs an angular velocity, a unit that outputs a phase difference between the phase of the power supply and the detection phase, an addition unit that adds a value based on the phase difference to the angular velocity,
It is characterized by further comprising an integrating means for integrating the angular velocity output from the adding means to obtain an integrated value, and a means for outputting the integrated value as the detection phase.

According to a second aspect of the present invention, in the phase detecting apparatus according to the first aspect, the adding means increases the value based on the phase difference and the amplifying means that amplifies the value based on the phase difference. It has a phase difference integrating means for integrating and a means for adding a value based on the output of the amplifying means and the output of the phase difference integrating means to the angular velocity.

According to a third aspect of the present invention, in the phase detection device according to the first or second aspect, the integrating means outputs a pulse having a frequency proportional to the angular velocity output from the adding means, And a counting unit that outputs a count value obtained by counting the pulses as the integrated value.

According to a fourth aspect of the present invention, in the phase detection device according to the first or second aspect, the integrating means outputs a stored value as the integrated value, and a register.
Adding means for adding the angular velocity output from the adding means to the value stored in the register, and outputting the added value;
Means for storing the added value in the register.

[0023]

According to the first aspect of the present invention, the phase detecting apparatus adds a value based on the phase difference between the phase of the power source and the detected phase to a predetermined angular velocity, integrates the addition result, and outputs it as the detected phase. The phase detection device according to claim 2 amplifies a value based on the phase difference between the phase of the power supply and the detection phase, further integrates the value based on the phase difference, and outputs the amplified value and the integrated value. Add the value based on the predetermined angular velocity,
The addition result is integrated and output as the detected phase.

The phase detecting device according to the third aspect adds a value based on the phase difference between the phase of the power source and the detected phase to a predetermined angular velocity, and outputs a pulse having a frequency proportional to the value. The count value obtained by counting the pulses is output as the detection phase. The phase detection device according to claim 4 adds a value based on the phase difference between the phase of the power supply and the detected phase to a predetermined angular velocity, adds the value to the value stored in the register, and adds the value. The value is stored in the register again, and the stored value is output as the detection phase.

[0025]

【Example】

(Embodiment 1) FIG. 1 shows the hardware configuration of a phase detection apparatus according to Embodiment 1 of the present invention. In FIG.
Since the same configurations as those are denoted by the same reference numerals as those in FIG. 8,
These explanations are omitted. In FIG. 1, 18 is an output unit that outputs a predetermined angular velocity ω _SET .
Reference numeral 21 denotes an adder that adds the correction value Δω to the angular velocity ω _SET and outputs the angular velocity ω of the power supply. An integrator 23 integrates the input angular velocity ω of the power source to output the same phase θ as the phase (power source phase) φ of the voltage or current of the power source. The phase θ is called the detected phase. The frequency of the power supply depends on the region. Therefore, when the area in which the phase detector of the present invention is used is predetermined, the angular velocity of the power source in that area is input to the adder 21 as ω _SET in FIG.

FIG. 2 shows the characteristic of the signal S ₁₂ shown in FIG.
If the detection phase θ leads the power supply phase φ, (θ−
Since φ) becomes positive, the signal S ₁₂ = sin (θ−φ) becomes positive. On the contrary, when the detection phase θ is behind the power supply phase φ, the signal S ₁₂ = sin (θ−φ) becomes negative. The amplifier 20 amplifies the signal S ₁₂ . The magnitude of the gain of the amplifier 20 is set so that the detection phase θ does not get out of step with the power supply phase φ even when the power supply voltage is greatly distorted.
However, if the gain of the amplifier 20 is too large, the detection phase θ is likely to be affected by the distortion of the power supply voltage. Therefore, when the signal S ₁₂ = 1, the correction value Δω> 2π × 5H
Set the gain to be z.

By adding the correction value Δω to the angular velocity ω _SET, when the detection phase θ is ahead of the power supply phase φ, ω
Becomes smaller. Therefore, the detection phase θ is delayed and becomes equal to the power supply phase φ. On the contrary, the detected phase θ from the power phase φ
Is delayed, ω becomes large. Therefore, the detection phase θ advances and becomes equal to the power supply phase φ.

FIG. 3 shows a first configuration of the integrator 34 shown in FIG. The integrator 34 is composed of general-purpose digital circuit elements. In FIG. 3, 4 is an oscillator for generating the clock Sp. Reference numeral 41 is a rate multi, which outputs a pulse train having a frequency proportional to the input ω. That is, the pulse train frequency = kω (k is a proportional constant). For example Texas Instruments (registered trademark)
Company's SN7497 can be used as the rate multi 41.

Reference numeral 42 denotes a counter, which is a rate multi 41.
The pulse train output from is counted. This makes ω
Can be integrated. It is assumed that the bit length of the maximum value counted by the counter 42 is the count length Nc and the bit length of the detection phase θ is Nd (Nd ≦ Nc). Upper Nd of Nc
Detection phase θ when outputting bits as detection phase θ
The frequency fs at which is calculated is

[0030]

[Equation 9]

It becomes That is, fs can be set by the proportional constant k of the rate multi and the count length Nc.

FIG. 4 shows a second configuration of the integrator 34 shown in FIG. In FIG. 4, 51 is a frequency divider that divides the clock Sp to generate a latch signal LA, and 53 is a latch signal LA.
This is a register for fetching input data by. 52
Is the angular velocity ω in the detected phase θ output from the register 53.
Is an adder for adding and inputting again to the register 53.

The frequency fs at which the detection phase θ is calculated is equal to the frequency of the latch signal LA. Therefore, the angular velocity ω is set to the magnitude of the power supply phase that advances during one cycle of the latch signal LA. By setting the frequency of the latch signal LA, that is, fs to be high, the detection signal θ can be detected at a high frequency.

FIG. 5 shows waveforms of the power supply voltage Su, the power supply phase φ, and the detection phase θ. By detecting the detection signal θ at a high frequency, the difference between the power supply phase φ and the detection phase θ can be reduced as compared with the conventional phase detector shown in FIG. Since the conventional phase detector detects the power supply phase at the moment based on the power supply voltage at a certain moment and the output voltage of the two-phase oscillator, it is easily affected by the momentary distortion of the power supply voltage. On the other hand, the phase detector of the present invention corrects the steady angular velocity ω based on the power supply voltage at a certain moment and the output voltage of the two-phase oscillator. Since the corrected angular velocity ω is integrated to detect the power supply phase θ, the distortion of the power supply voltage at a certain moment does not immediately affect the phase. Therefore, the influence of the distortion of the power supply voltage can be reduced.

(Second Embodiment) FIG. 6 shows a hardware configuration of a second embodiment of the present invention. When the angular velocity of the power supply is one of the known angular velocities, the average value or the intermediate value of the known angular velocities is input to the adder 21 as ω _SET . For example,
When the phase detector of the present invention is used anywhere in Japan, the angular velocity of the power source is 2π × 50 Hz or 2π × 6.
Since it is 0 Hz, 55 of their average value or intermediate value
Input Hz to ω _SET to the adder 21. In this case, a steady difference occurs between the set angular velocity ω _SET and the angular velocity ω of the power supply. Therefore, in order to compensate for this difference, an integrator 23 that integrates Δω is provided in parallel with the amplifier 20.

When the detection phase θ is ahead of the power supply phase φ, Δω becomes positive, so the integrated value ω ′ by the integrator 23.
Grows larger. On the contrary, when the detection phase θ is behind the power supply phase φ, Δω becomes negative, and thus the integrated value ω ′ becomes small. Therefore, the integrated value ω ′ becomes equal to the difference between the angular velocity ω of the power source and the preset angular velocity ω _SET . By adding this integrated value ω ′ to the set angular velocity ω _SET by the adder 21, the angular velocity ω of the power supply can be obtained. Further, since the integrated value ω ′ is stable when the power supply phase φ and the detection phase θ match, the detection phase θ becomes equal to the power supply phase φ.
In this way, the power supply phase φ can be detected.

Note that the integrator 23 does not necessarily have to be provided at the subsequent stage of the amplifier 20 as long as it is capable of compensating for the steady difference between the set angular velocity ω _SET and the angular velocity ω of the power supply.
For example, the amplifier 20 and the integrator 23 may be provided in parallel, the respective outputs may be added, and further input to the adder 21. ,

(Embodiment 3) In Embodiment 1 or 2, the three-phase alternating currents Su, Sv, Sw are given by sine as in the following equation.

[0039]

[Equation 10]

On the other hand, in the third embodiment, the three-phase alternating current S
u, Sv and Sw are given by the cosine as in the following equation.

[Equation 11]

When each of the phases of the equation 10 is advanced by π / 2,

(Equation 12)

[Mathematical formula-see original document] and agrees with the equation 11. Therefore, if the phase of the two-phase oscillator 6 is also advanced by π / 2, the two-phase oscillator 6
The output of

[0043]

(Equation 13) Becomes At this time, the signal S ₁₂ is

[0044]

[Equation 14]

And is in agreement with Equation 5. Therefore, the power supply phase φ can be detected by latching the counter output θ at the rising edge of the binary signal S ₁₂ as in the first or second embodiment. As described above, even when the three-phase alternating currents Su, Sv, and Sw are given by cosine, the phase of the two-phase oscillator 6 is advanced by π / 2,
The phase detection device described in the first or second embodiment can be used. FIG. 7 shows a hardware configuration of the phase detector in which the two-phase oscillator 6 is changed when the AC power defined by the cosine is supplied to the phase detection device described in the first embodiment.

(Others) In the case where the angular velocity ω of the voltage or current of the power source is one of a plurality of predetermined angular velocities, for example, when the phase detector is used only in Japan, 2 in the configuration shown in FIG.
One of the known angular velocities selected by switch operation,
It may be entered as the set angular velocity ω _SET . in this case,
Compared with the configuration of FIG. 6, the integrator 23 can be omitted.

[0047]

As is apparent from the above description, according to the present invention, a value based on the phase difference between the phase of the power source and the detected phase is added to the predetermined angular velocity, and the addition result is integrated. Since it is output as the detection phase, the distortion of the power supply voltage is unlikely to affect the detection phase. Moreover, since the integrated value of the phase difference affects the detection phase, the influence of instantaneous voltage distortion of the power supply on the detection phase is reduced.

Further, a value based on the phase difference between the phase of the power source and the detected phase is amplified by an amplifier and integrated by an integrator,
It is also possible to add a value based on the amplified or integrated value to a predetermined angular velocity, integrate the addition result, and output it as a detection phase. In this case, the effect of distortion of the power supply voltage can be further reduced by reducing the gain of the amplifier. By making the gain sufficiently small, it is possible to ignore the influence of the phase distortion of the power supply voltage and detect only the phase of the basic component of the power supply voltage.

Further, when the frequency of the oscillator 4 of the present invention is the same as that of the conventional clock signal Sp, the phase error Δφ becomes small. Therefore, the frequency of the oscillator 4 can be reduced. Therefore, it is possible to use a slow-moving element, facilitate countermeasures against radiation noise, and reduce the cost of the phase detection device.

Furthermore, the detection frequency of the power supply phase is calculated by the integrator 3
The frequency of the clock of 4 can be increased. Therefore, the phase error of the detected phase can be made extremely small. Further, the phase detection frequency can be increased to 20 kHz or more, which is four times the IGBT switching frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of a phase detection device of the present invention in a first embodiment.

FIG. 2 is an explanatory diagram showing a waveform of a signal S ₁₂ .

FIG. 3 is a block diagram showing a first configuration of an integrator 34.

FIG. 4 is a block diagram showing a second configuration of the integrator 34.

FIG. 5 is an explanatory diagram illustrating waveforms of a power supply phase φ and a detection phase θ of the phase detection device of the present invention.

FIG. 6 is a block diagram showing a hardware configuration of a phase detection device of the present invention in a second embodiment.

FIG. 7 is a block diagram showing a hardware configuration of a phase detection device of the present invention in a third embodiment.

FIG. 8 is a block diagram showing a hardware configuration of a conventional phase detection device.

FIG. 9 is an explanatory diagram showing waveforms of a power supply phase φ and a detection phase θ in a hardware configuration of a conventional phase detection device.

[Explanation of symbols]

 4 oscillator 5 counter 6 two-phase oscillator 7, 8 multiplier 9, 10 amplifier 11, 12 adder 13 comparator 14 latch circuit 18 output unit 20 amplifier 21 adder 23, 34 integrator 41 rate multi 42 counter 51 frequency divider 52 adder 53 register

Claims (4)

[Claims] 1. A phase detection device for detecting a phase of a power supply and outputting a detection phase, the output unit outputting a predetermined angular velocity, and outputting a phase difference between the phase of the power supply and the detection phase. Means, an adding means for adding a value based on the phase difference to the angular velocity, an integrating means for integrating the angular velocity output from the adding means to obtain an integrated value, and outputting the integrated value as the detected phase. A phase detection device comprising: 2. The adding means includes: an amplifying means for amplifying a value based on the phase difference; a phase difference integrating means for integrating a value based on the phase difference; an output of the amplifying means and the phase difference integrating means. The phase detection device according to claim 1, further comprising a unit that adds a value based on the output of the unit to the angular velocity. 3. The integrating means includes means for outputting a pulse having a frequency proportional to the angular velocity output from the adding means, and counting means for outputting a count value obtained by counting the pulse as the integrated value. The phase detection device according to claim 1 or 2, characterized in that. 4. The integrating means adds the angular velocity output from the adding means to the register that outputs the stored value as the integrated value, and outputs the added value to the value stored in the register. 3. The phase detection device according to claim 1, further comprising: an addition unit configured to perform the addition, and a unit configured to store the added value in the register.