JPH08298343A - End surface emitting led array and it manufacture - Google Patents

Abstract

PURPOSE: To provide an end surface emitting type LED array and its manufacturing method wherein light emitting end surfaces are sufficiently isolated and high density constitution is possible. CONSTITUTION: An N-type semiconductor substrate 11, P-type GaAsP regions 13 formed on the semiconductor substrate 11 at specified intervals, contact parts 20 formed on the P-type GaAsP regions 13 by etching an insulating film 19, P side electrodes 15 connected with the contact parts 20, end surfaces 13a of the P-type GaAsP regions 13 which surfaces are formed on the opposite side of the P side electrodes 15, and an end surface 11a of the semiconductor substrate which surface is continuous to the end surfaces 13a are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an edge emitting LED array used in an LED printer head which is a light source of an electrophotographic printer, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an LED array has been used as a light source for an electrophotographic printer, for example. LE
One type of D array is called an edge emitting LED array. The structure and manufacturing method of the LED array are disclosed, for example, in (1) Japanese Patent Application Laid-Open No. 5-31955. According to the prior art, when a light emitting end face is formed on a semiconductor wafer having a double hetero structure, it is described that it is performed by a dry etching method using a chlorine-based gas.

[0003]

However, in the case of the conventional LED array, there is a problem that it is difficult to achieve a high density of, for example, 600 dpi or more. For example, in the case of the LED array disclosed in the above-mentioned prior art, the light emitting end face is separated by the separation groove, but the width of this groove hinders high density.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an edge emitting LED array capable of eliminating the above-mentioned conventional problems, sufficiently separating the light emitting edge and achieving high density, and a method of manufacturing the same. To do.

[0005]

In order to achieve the above object, the present invention provides (1) an edge-emitting type L which is separated by dicing from a semiconductor wafer having a plurality of PN junction light emitting elements formed thereon.
In the ED array, a first conductivity type semiconductor base, and second conductivity type regions formed on the semiconductor base at predetermined intervals
A contact portion formed by etching an insulating film on the second conductivity type region, an electrode connected to the contact portion, and an end face of the second conductivity type region formed on the side opposite to the electrode, The subsequent end face of the semiconductor base is provided.

(2) In a method of manufacturing an edge-emitting LED array formed by dicing a semiconductor wafer having a plurality of PN junction light emitting elements formed thereon, a step of forming a first conductive type semiconductor base, and After the diffusion prevention film is etched and selectively diffused on the semiconductor underlayer, the diffusion prevention film is etched to increase the contact area with the P-side electrode, and insulation for insulating the semiconductor underlayer and the P-side electrode After the film is formed, a step of simultaneously forming a contact hole and a mask for forming a light emitting end surface, and a step of removing the mask for forming the light emitting end surface by a lift-off method during etching for forming the light emitting end surface are performed.

[0007]

[Action]

(1) According to the edge emitting LED array according to the first aspect, it is possible to obtain an edge emitting LED array in which the light emitting end surfaces are sufficiently separated and the density can be increased. (2) According to the manufacturing method of the edge-emitting LED array according to the second aspect, the unnecessary diffusion preventing film is removed by etching after the impurities are diffused in the portion not covered with the diffusion preventing film. Therefore, for example, in a high-density LED array of 600 dpi or more, even if the diffusion region becomes fine, P
Since the side diffusion region can be used for connection with the side electrode, the contact resistance is not increased due to the reduction of the contact area.

Since the contact hole and the light emitting end face formation mask are formed at the same time in the insulating film etching step, the accuracy of mask alignment is significantly improved as compared with the case where the contact hole formation and the light emitting end face formation are performed separately. Thus, it is possible to manufacture an LED array with little variation in the bonding area. In the light emitting end face forming etching step, the light emitting end face forming mask is removed by the lift-off method. Therefore, side etching during the light emitting end face forming etching allows the LED array to be manufactured without the mask remaining in the eaves shape. .

[0009]

Embodiments of the present invention will be described in detail below with reference to the drawings. It should be noted that each of the drawings schematically shows the dimensions, shapes, and arrangement relationships of the respective constituent components to the extent that these inventions can be understood. Further, in each drawing, the same constituent components are indicated by the same reference numerals.

FIG. 1 shows an edge emitting type L showing an embodiment of the present invention.
It is a figure which shows the structure of ED array, FIG.1 (A) is a top view of the edge emitting LED array, FIG.1 (B) is FIG.
The side view seen from the P direction of (A), FIG. 2 is the CC sectional view taken on the line in FIG. 1 (B). 1 and 2, 1
0 is an edge emitting LED array showing an embodiment of the present invention, 1
Reference numeral 1 is an N-type (first conductivity type) semiconductor base. In detail,
N-type gallium arsenide (GaAs) substrate and this N-type G
The N-type semiconductor underlayer 11 is composed of N-type gallium / arsenic / phosphorus (GaAsP) epitaxially grown on the aAs substrate.

Further, 13 is a P formed on the N-type semiconductor underlayer 11 at a predetermined interval (an interval corresponding to the LED arrangement pitch).
Type (second conductivity type) GaAsP region. This P-type Ga
The junction between the AsP region 13 and GaAsP of the N-type semiconductor base 11 becomes a light emitting region. Further, 15 is a P-side electrode,
An insulating film 19 electrically insulates the P-side electrode 15 and the N-type semiconductor base 11 from each other. Reference numeral 17 indicates an N-side electrode, and 23 indicates a light emitting end face.

As described above, the N-type semiconductor base 11 and the P-type GaAsP formed on the semiconductor base 11 at a predetermined interval.
Region 13 and insulating film 1 on P-type GaAsP region 13
Contact part 20 formed by etching 9
And the P-side electrode 15 connected to the contact portion 20.
Then, the end face 13a of the P-type GaAsP region 13 formed on the side opposite to the P-side electrode 15 and the end face 11a of the semiconductor underlayer 11 subsequent thereto are provided.

Next, an edge emitting type L showing an embodiment of the present invention will be described.
A method of manufacturing the ED array will be described. FIG. 3 is a sectional view (No. 1) of a manufacturing process of an edge emitting LED array showing an embodiment of the present invention, and FIG. 4 is a manufacturing process sectional view (No. 2) of an edge emitting LED array showing an embodiment of the present invention. is there.

(1) First, as shown in FIG.
N-type GaAs substrate and N-type GaAsP layer epitaxially grown on this N-type GaAs substrate
The diffusion prevention film 21 is formed on the mold semiconductor base 11 by a known film forming method such as a vapor deposition method, a sputtering method or a CVD method, a photolithography technique, and an etching technique.

The diffusion prevention film 21 can be made of, for example, a film selected from an alumina film, a nitride film, and a silicon oxide film. The film thickness can be set to 50 to 200 nm, for example. The diffusion control film 25 is formed on the N-type semiconductor base 11 on which the diffusion prevention film 21 is formed by a known film forming method. The diffusion control film 25 is, for example, an alumina film, a nitride film, a silicon oxide film, PSG (Phospho-Si).
It can be made of a film selected from the licate glass). The film thickness is, for example, 10 to 20 nm.

(2) Next, as shown in FIG.
A P-type GaAsP region 13 is formed by diffusing, for example, zinc (Zn) as a P-type impurity by a vapor phase diffusion method through a diffusion control film 25 in a portion of the type semiconductor underlayer 11 not covered with the diffusion prevention film 21. To do. (3) Next, as shown in FIG. 3C, the diffusion control film 25 and the diffusion prevention film 21 shown in FIG. 3B are removed.
The P-side electrode may be left without being necessarily etched in the lower part of the planned site.

Next, an insulating film 19 for insulating the N-type semiconductor base 11 and the P-side electrode formed later is formed on this substrate by a known film forming method. This insulating film 1
9 can be composed of a film selected from, for example, an alumina film, a nitride film, or a silicon oxide film. The film thickness is
For example, it is 50 to 100 nm. Next, this insulating film 1
9 is processed into a predetermined shape by a known lithographic technique and etching technique to form a contact hole 1 in the insulating film 19.
9-1 is formed. At the same time, the mask 19a for the light emitting end face,
19b is formed by etching.

(4) Next, as shown in FIG.
The P-side electrode 15 connected to the type GaAsP region 13 is formed by a well-known film forming method and fine processing technique, and N
An N-side electrode 17 is formed on the back surface of the mold semiconductor base 11. The N-side electrode 17 may be formed after polishing the back surface of the N-type semiconductor underlayer 11 to improve the characteristics. Where P
The material forming the side electrode 15 is a P-type GaAsP region 13
There is no particular limitation as long as it is a material capable of making ohmic contact with. For example, aluminum is the P-side electrode 15
Can be used as a constituent material. Further, the constituent material of the N-side electrode 17 is not particularly limited as long as it is a material capable of making ohmic contact with the N-type semiconductor base 11. For example, gold alloy can be used as a constituent material of the N-side electrode 17.

(5) Next, a predetermined recess is formed in the substrate. Here, a predetermined concave portion is formed in a portion between the adjacent LED arrays, that is, a portion corresponding to a dicing planned area on the light emitting end face side of the adjacent LED arrays. For this reason, first, as shown in FIG. 4A, an etching mask 27, for example, a resist pattern, which covers a region other than the region where the recess is to be formed, which is not covered with the insulating film, is formed on the substrate.

(6) Next, as shown in FIG.
The substrate on which the etching mask 27 has been formed is etched to form the recess 29. This etching, for example,
The etching is performed with a phosphoric acid-based or citric acid-based etching solution.
For example, a 50 wt% citric acid aqueous solution [C ₃ H ₄ (O
[H) (COOH) ₃ · H ₂ O] and hydrogen peroxide solution are mixed at a predetermined mixing ratio and can be used as a citric acid-based etchant.

In this way, the P-type GaAsP region 13 is formed.
End surface 13a and the end surface 11a of the N-type semiconductor underlayer 11 subsequent thereto are formed. Next, when the resist is peeled off, the etching mask made of the insulating film is peeled off by lift-off at the same time, and the eaves are not left. As described above, the semiconductor wafer in the state shown in FIG.
Multiple arrays will be created.

(7) Next, predetermined dicing is performed. That is, as shown in FIG. 4C, the semiconductor wafer on which a plurality of LED arrays have been formed is diced from the bottom surface of the recess 29 with a cutting width w2 narrower than the width w1 at the bottom surface.
As described above, (A) since the unnecessary diffusion preventing film 21 is removed by etching after diffusing the impurities in the portion not covered with the diffusion preventing film 21, for example, the high density LED on 600 dpi. In the array, a P-type G that is a diffusion region
Even if the aAsP region 13 becomes finer, the side diffusion region can be used for the connection with the P-side electrode 15, so that the contact resistance is not increased by the reduction of the contact area.

(B) In the step of etching the insulating film 19, the contact hole 19-1 and the mask 19 on the light emitting end face.
Since a and 19b are formed at the same time, the accuracy of mask alignment is significantly improved and an LED array with less variation in the bonding area can be manufactured, as compared with the case where the contact hole formation and the light emitting end face formation are performed separately. it can. (C) In the etching process for forming the light emitting end face, the masks 19a and 19b on the light emitting end face are removed by the lift-off method.
Arrays can be made.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0025]

As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the invention described in claim 1, it is possible to obtain an edge-emitting LED array capable of sufficiently separating the light-emitting edge surface and enabling high density. Especially 600 dpi
Even with the above high density, it is possible to design with a margin in mask alignment accuracy. In addition, P is higher than the conventional design value.
The N-junction area can be designed small.

As a result, the current density flowing through the PN junction is increased, and a brighter LED than before can be manufactured. (2) According to the second aspect of the present invention, the unnecessary diffusion prevention film is removed by etching after the impurities are diffused in the portion not covered with the diffusion prevention film. In a high-density LED array, even if the diffusion area becomes fine, P
Since the side diffusion region can be used for connection with the side electrode, the contact resistance is not increased due to the reduction of the contact area.

Since the contact hole and the light emitting end face formation mask are formed at the same time in the insulating film etching step, the accuracy of mask alignment is significantly improved as compared with the case where the contact hole formation and the light emitting end face formation are performed separately. Thus, it is possible to manufacture an LED array with little variation in the bonding area. In the light emitting end face forming etching step, the mask for forming the light emitting end face is removed by the lift-off method. Therefore, side etching during the light emitting end face forming etching does not leave the mask in the shape of an eaves-shaped LED array.

Further, in order to carry out this step, no specially expensive device, jig or the like is required, and the manufacturing can be carried out at low cost.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of an edge-emitting LED array showing an embodiment of the present invention.

FIG. 2 is a sectional view taken along line CC in FIG.

FIG. 3 is a sectional view (No. 1) of a manufacturing process of an edge-emitting LED array showing an example of the present invention.

FIG. 4 is a manufacturing process sectional view (2) of an edge-emitting LED array showing an example of the present invention.

[Explanation of symbols]

 10 Edge-Emitting LED Array 11 N-Type (First Conduction Type) Semiconductor Base 11a N-type End Face of Semiconductor Base 13 P-type (Second Conduction Type) GaAsP Region 13a P-type GaAsP Region End Face 15 P-side Electrode 17 N-side Electrode 19 Insulating film 19-1 Contact holes 19a, 19b Mask of light emitting end face 20 Contact part 21 Diffusion prevention film 23 Light emitting end face 25 Diffusion control film 27 Etching mask 29 Recess

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masumi Koizumi 1-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. An edge emitting LED array, which is separated by dicing from a semiconductor wafer having a plurality of light emitting elements having PN junctions, wherein (a) a first conductive type semiconductor base and (b) the semiconductor base. Second conductivity type regions formed at predetermined intervals, and (c) contact portions formed on the second conductivity type regions by etching an insulating film,
An edge-emitting LED having (d) an electrode connected to the contact portion, (e) an end face of the second conductivity type region formed on the opposite side of the electrode, and an end face of the semiconductor base that follows the end face. array. 2. A method of manufacturing an edge-emitting LED array, which is separated by dicing from a semiconductor wafer on which a plurality of light emitting elements having PN junctions are formed, the method comprising: (a) forming a semiconductor substrate of a first conductivity type; (B) a step of etching the diffusion barrier film on the semiconductor underlayer to selectively diffuse the same, and then etching the diffusion barrier film to increase the contact area with the P-side electrode; and (c) the semiconductor underlayer and the P side. A step of forming a contact hole and a mask for forming a light emitting end surface at the same time after forming an insulating film for insulating the electrode;
(D) A step of removing the mask for forming the light emitting end surface by a lift-off method at the time of etching for forming the light emitting end surface.