JPH08293582A - Semiconductor device - Google Patents

Abstract

PURPOSE: To enable an SC circuit to be formed as approximate in characteristics as previously designed by a method wherein a parasitic capacitance formed between capacitors used in a switched capacitor circuit (SC circuit) is eliminated. CONSTITUTION: A unit capacitor is formed on each grid of a grounding wire 3 formed in grids. Each capacitor is composed of the unit capacitors connected in series with Al wirings. That is, on the left side of a figure an upper electrode 11 and a lower electrode 12 are connected to Al wirings 13 and 14 respectively, a capacitor is formed of the one unit capacitor, and on the right side of a figure, upper electrodes 21a and 21b are connected to an Al wiring 23, lower electrodes 22a and 22b are connected to an Al wiring 24, and a capacitor is composed of the two unit capacitors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a switched capacitor circuit (hereinafter, referred to as an SC circuit).

[0002]

2. Description of the Related Art An SC circuit comprises a switch that opens and closes periodically, a plurality of capacitors and an operational amplifier. The transfer function of the SC circuit is determined by the capacitance ratio of the capacitor, as described later. The area is the parameter that can be controlled most accurately in the semiconductor device manufacturing process. Even if there is, the variation of the area ratio can be suppressed low, so that it is possible to configure as a circuit having a high precision constant, and a circuit for configuring a filter, an impedance element, etc. in an analog integrated circuit. Has been awarded as.

FIG. 3 shows an example of the SC circuit. Switches SW ₁ and the switch SW ₂ is adapted to switch to the terminal 1 and the terminal 2 to terminal 0 as a stator. Usually, these switches are constituted by MOS type field effect transistors.

[0004] inverting input of the operational amplifier OA, and the terminal 1 of the upper electrode and the switch SW ₁ of the capacitor C ₁ is connected, the positive-phase input of the operational amplifier OA is connected to ground. The lower electrode of the capacitor C ₁ is connected to the output terminal Vo and the output of the operational amplifier OA. Terminal 2 of the switch SW ₁ is grounded. The upper electrode of the capacitor C ₂ is a switch S
The lower electrode is connected to the terminal 0 of W ₁ and the lower electrode is connected to the terminal 0 of the switch SW ₂ . The terminal 1 of the switch SW ₂ is grounded, and the terminal 2 is connected to the input terminal Vi.

The SC circuit shown in FIG. 3 constitutes a filter, and its transfer function is given by the following equation (1), where the capacitances of the capacitors C ₁ and C ₂ are C ₁ and C ₂ , respectively. H (z) = (C ₂ / C ₁ ) × {Z ^−1/2 / (1−Z ⁻¹ )} (1) As is clear from the equation (1), the frequency characteristic (cutoff frequency) of the SC circuit ) Is determined by the capacitance value ratio of each capacitor. In order to increase the accuracy of the capacitance value, the SC circuit generally employs a method of arranging a plurality of capacitors having the same unit area and shape in the layout of the capacitance unit.

FIG. 4 (a) is a plan view showing a conventional structure of the SC circuit capacitance portion, and FIG. 4 (b) is a sectional view taken along line BB thereof. As shown in FIG. 1, a plurality of lower electrodes are formed in an island shape on a silicon oxide film 2 formed on a semiconductor substrate 1, and a lower electrode is formed on the lower electrode with an interlayer insulating film 4 interposed therebetween. An upper electrode that is one size smaller than that is arranged. Except for an opening for contacting each electrode, the whole is covered with a cover film 5. All the lower electrodes are formed in the same area, and all the upper electrodes are formed in the same area. Therefore, the unit capacitors composed of a set of lower electrode and upper electrode have the same unit capacitance C ₀ .

[0007] In the left half of the figure, the upper electrode 11 and lower electrode 12 are connected via a contact 15 and 16 to the Al wiring 13 and 14 respectively, to form a capacitor C ₁ of the capacitor C _0. In the right half of the figure, the upper electrode 21a, 21b and the lower electrode 22a, 22b, the contact 25a of the Al wiring 23 and 24, respectively, 25b and the contact 26a, is connected via 26b, capacitor C ₂ of the capacitor 2C ₀ Is formed.

The upper and lower electrodes of the capacitors C ₁ and C ₂ are Al wirings 13, 14, 23 and 24, respectively.
Are connected to desired circuits via. Since the capacitors C ₁ and C ₂ are arranged close to each other,
Parasitic capacitance is generated between the lower electrodes of the capacitors C ₁ and C ₂ and affects the frequency characteristics of the SC circuit. In addition, parasitic capacitance occurs between wiring layers, which also affects the frequency characteristics of the SC circuit.

In the SC circuit shown in FIG. 3, the parasitic capacitance Cp generated between the lower electrode of the capacitor C _{1 and} the lower electrode of the capacitor C _{2 is} the lower electrode of the capacitors C ₁ and C ₂ as indicated by the broken line. Connected in between. The transfer function of the SC circuit when the parasitic capacitance Cp occurs as shown in FIG. 3 is given by the following equation (2). H ′ (z) = {(C ₂ −Cp) / (C ₁ + Cp)} × {Z ^−1/2 / (1−Z ⁻¹ )} (2)

On the other hand, a parasitic capacitance generated between wiring layers drawn from the capacitor is connected in parallel to the capacitor C ₁ or C ₂ . As a countermeasure for the parasitic capacitance generated between the wirings, there is one proposed in Japanese Patent Application Laid-Open No. 3-238823. This will be described with reference to FIG.

FIG. 5 is a cross-sectional view showing this conventional example, which shows a state at a portion corresponding to a cross section taken along line CC of FIG. 4 (a). An interlayer insulating film 33 is formed on the silicon oxide film 32 provided on the semiconductor substrate 31 to be inserted between the lower electrode and the upper electrode of the capacitor. A wiring 34 connected to the lower electrode and a wiring 35 connected to the upper electrode are formed on the interlayer insulating film 33, and a low-impedance wiring 36 is formed between the two wirings. The surfaces of the interlayer insulating film 33 and the wirings 34 to 36 are covered with the cover film 37.

[0012]

In the conventional semiconductor device shown in FIG. 4, since the lower electrodes of the unit capacitors are arranged close to each other, a parasitic capacitance is generated between the unit capacitors. Parasitic capacitance is generated between the capacitors formed in parallel connection.
As the transfer function of the circuit is expressed by the above equation (2),
The characteristics deviate from the design values given by equation (1).

In the conventional example shown in FIG. 5, the problem of a decrease in the accuracy of the capacitance ratio due to the parasitic capacitance generated between the wiring layers is improved, but there is no effect on the parasitic capacitance generated between the capacitances. In general, the interlayer insulating film serves as the dielectric film of the capacitor and is therefore made of a material having a high relative dielectric constant.
Therefore, a large parasitic capacitance is generated between the capacitors, and the effect is larger than the effect of the parasitic capacitance generated between the wiring layers.

The present invention has been made in view of this point, and an object of the present invention is to cut off capacitive coupling generated between capacitors, improve the specific capacitance accuracy of an SC circuit, and obtain a design value of a transfer function of the SC circuit. The goal is to minimize the deviation.

[0015]

To achieve the above object, according to the present invention, a plurality of capacitors formed on a semiconductor substrate by two conductive layers sandwiching an interlayer insulating film are provided. In a semiconductor device having at least one capacitor, the connection state of which is regularly changed by a switching element, a wiring layer connected to the low impedance line and formed in the same layer as the lower electrode of the capacitor is formed between the capacitors. A semiconductor device,
Will be provided.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1A is a plan view showing a configuration of a capacitor unit according to one embodiment of the present invention, and FIG.
FIG. 3 is a sectional view taken along line AA of FIG. In FIG. 1, portions similar to those of the conventional example shown in FIG. 4 are designated by the same reference numerals, and thus duplicated description will be omitted. In comparison with the example, the unit capacitor is surrounded by the ground wiring 3 in the same wiring layer as the lower electrode. That is, the ground wiring 3 is formed in a lattice shape, and a unit capacitor is formed in a grid portion of the ground wiring 3. Then, the required number of unit capacitors are connected in parallel by the Al wirings 13 and 14 to the Al wirings 23 and 24.

By inserting the ground wiring between the lower layer electrodes, the capacitive coupling generated between the lower layer electrodes of the unit capacitors is canceled, and each lower layer electrode has a parasitic capacitance with the ground wiring. Therefore, the combined capacitor formed by connecting the unit capacitors in parallel does not have a parasitic capacitance between the capacitors, but has a parasitic capacitance with the ground wiring.

FIG. 2 is a circuit diagram of an SC circuit having the capacitor shown in FIG. As shown in the figure, the capacitors C ₁ and C ₂ have parasitic capacitances Cp ₁ and Cp ₂ between the lower electrode and the ground, respectively. Thus, references (eg "Switched Capacitor Circuit" p.48 published by Hyundai Engineering Co.)
As described above, the parasitic capacitance of the ground potential does not affect the frequency characteristics.

For example, in the conventional example shown in FIG. 3, when the capacitances of the capacitors C ₁ and C ₂ are C ₁ = C ₂ = 0.5 pF and the parasitic capacitance Cp is Cp = 0.01 pF,
Assuming that the cutoff frequency when the parasitic capacitance Cp does not occur is 1, the cutoff frequency when the parasitic capacitance Cp occurs is 0.96, which is a deviation of 4% from the design value. According to the present invention,
By eliminating this deviation, it is possible to configure a circuit as designed.

The preferred embodiment has been described above.
The present invention is not limited to this, and various changes can be made within the scope described in the claims. For example, in the embodiment, the ground wiring is laid between all the unit capacitors, but when one composite capacitor is composed of a plurality of unit capacitors, the ground wiring may not be provided in the same composite capacitor. . Further, the wiring arranged between the capacitors is not limited to the ground wiring, but may be a wiring connected to another low impedance line such as a power supply wiring. Further, in combination with the present invention and the above-mentioned second conventional example, a ground wiring and the like in the same layer can be arranged between Al wirings drawn out of the capacitor.

[0021]

As described above, according to the present invention, a plurality of unit capacitors each having a two-layer structure with an interlayer insulating film interposed therebetween are connected to a low impedance line and connected to the same layer as the lower electrode. Since the layers are arranged, the parasitic capacitance generated between the unit capacitors can be reduced to the parasitic capacitance of the ground potential. Therefore, according to the present invention, it is possible to reduce the deviation of the circuit characteristic of the SC circuit from the design value.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view showing a configuration of a capacitor unit according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of one embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of a conventional example.

4A and 4B are a plan view and a cross-sectional view illustrating a configuration of a capacitor unit in a conventional example.

FIG. 5 is a cross-sectional view showing a state of a wiring drawn from a capacitor in another conventional example.

[Explanation of symbols]

1, 31 Semiconductor substrate 2, 32 Silicon oxide film 3 Ground wiring 4, 33 Interlayer insulating film 5, 37 Cover film 11, 21a, 21b Upper electrode 12, 22a, 22b Lower electrode 13, 14, 23, 24 Al wiring 15, 16, 25a, 25b, 26a, 26b Contact 34, 35 Wiring 36 Low impedance wiring C ₁ , C ₂ Capacitor (or capacitance thereof) Cp, Cp ₁ , Cp ₂ Parasitic capacitance OA Operational amplifier SW ₁ , SW ₂ switch Vi Input terminal Vo output terminal

Claims (4)

[Claims] 1. A semiconductor device comprising a plurality of capacitors formed on a semiconductor substrate and formed by two conductive layers sandwiching an interlayer insulating film, and at least one capacitor is periodically connected by a switching element. In a semiconductor device to be changed, a wiring layer connected to a low impedance line and having the same layer as a lower electrode of the capacitor is formed between the capacitors. 2. The semiconductor device according to claim 1, wherein at least one capacitor is constituted by a parallel connection of unit capacitors having a unit capacitance. 3. The semiconductor device according to claim 1, wherein said low impedance line is a ground line. 4. The same wiring layer connected to a low impedance line is formed between a wiring layer drawn from a lower electrode and a wiring layer drawn from an upper electrode of the same capacitor. 2. The semiconductor device according to claim 1, wherein