JPH08287241A - Data processor - Google Patents

Abstract

PURPOSE: To provide the data processor which can download control data to respective pipeline elements in a pipeline by using a simple hardware interface. CONSTITUTION: This data processor is provided with the pipeline constituted by connecting the pipeline elements 21-24 in downloading order through control signal lines 30-34 in series and downloading hardware 36 which has a signal input/output part 361 connected to the signal input side of the head element 24 of the pipeline and the signal output side of the tail element 21 and downloads control data to the respective pipeline elements through a common data bus 12. Each element when supplied with an acknowledgement signal at its signal input side at the time of downloading enters a download ready state to input downloaded control data addressed to itself and supplies an acknowledgement signal to the signal input side of the next-stage pipeline element on the completion of the input and when the hardware 36 inputs an acknowledgement signal finally, the downloading to the pipeline is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for performing pipeline processing by connecting a plurality of processors each having a processing function (hereinafter referred to as a function block) in series, and more particularly, to each processor (hereinafter, referred to as a pipe). (Referred to as a line element) has a memory for storing control data regarding a built-in function block.

[0002]

2. Description of the Related Art When high-speed processing of a large amount of data is desired such as image processing, it is effective to apply pipeline processing.

Conventionally, when developing a pipeline processing device, the pipeline elements forming the pipeline are directly configured as function blocks in hardware designed for each case, or the corresponding function blocks and their operation are performed. It is configured by downloading the operation information of the function block to the memory by using the pipeline element including the memory that determines the. The number of pipeline stages is also designed for each device according to the processing content.

FIGS. 4A and 4B are views showing first and second configuration examples of a conventional pipeline processing apparatus. 5A and 5B are diagrams showing third and fourth configuration examples of the conventional pipeline processing apparatus.

In FIG. 4A, dedicated function blocks F1 are connected in series in four stages to form a pipeline. In this pipeline, each pipeline element P1
Is composed of a function block F1 directly configured by hardware, the function of the pipeline is fixed.

In this configuration, all the pipeline elements and the number of pipeline stages must be newly designed according to the processing purpose of the pipeline, and there is a problem that the development cost rises.

In FIG. 4 (b), the pipeline element P2 has a general purpose function block F2 and a volatile memory M1 for controlling it, and has a download hardware D1 for each element P2.

With this configuration, it is easy to change the processing contents of each pipeline element P2 and it is easy to increase or decrease the number of stages of the pipeline, but each stage has a download hardware D1. It becomes an expensive system. Further, there is a problem in that it is necessary to always download at the time of starting the apparatus, it takes a lot of time until the pipeline is started, and it is not practical.

In FIG. 5A, the pipeline element P3 has a general-purpose function block F3 and a non-volatile memory M2 for controlling it, and the control information is written in the non-volatile memory M2 before it is assembled into a pipeline.

With this configuration, it is easy to increase or decrease the number of pipelines. However, each pipeline element P
In order to change the processing content of No. 3, since it does not have a download function, it is necessary to physically remove the non-volatile memory M2 from the pipeline once and rewrite the content in another system, which is troublesome. was there.

In FIG. 5B, each pipeline element P4 uses a general-purpose function block F4 and a non-volatile memory M3 for controlling the general-purpose function block F4, and further the non-volatile memory M3.
Download data bus 10 for rewriting the contents of
One is provided for 0, and one is provided for each non-volatile memory M3, and the control signal line 101 for downloading is provided.

In this configuration, in order to change the processing contents of each pipeline element P4, one data bus 100 and control signals corresponding to the number of nonvolatile memories are controlled to control the general purpose function block F4 from the download hardware D2. You can write data. Therefore, although the processing contents of the pipeline element P4 can be changed very easily, when the number of stages of the pipeline becomes large, the control signal line for controlling each non-volatile memory M3 as compared with the download data bus 100. 101 becomes very large,
There is a problem that the control logic becomes large-scale.

Therefore, an object of the present invention is to provide a data processing device capable of downloading data relating to processing function control to pipeline elements constituting a pipeline by using a simple hardware interface.

Another object of the present invention is to provide a data processor capable of downloading data relating to processing function control to each processor with a simple hardware interface even if the number of pipeline elements constituting the pipeline is increased or decreased. Is to provide.

[0015]

A data processing apparatus according to claim 1, wherein each of the plurality of pipeline elements having a processing function has a signal output side of the preceding pipeline element and a signal of the next pipeline element. A processing unit including a pipeline in which the input side is connected in series according to a predetermined order, and a signal output side and a signal input side of the signal input side of the head pipeline element and the signal output side of the tail pipeline element of this pipeline. Each of the plurality of pipeline elements is connected to the other pipeline element and has a download unit for downloading the control data regarding the processing function to each of the pipeline elements. Then, each element is given a prohibition signal on the signal input side prior to downloading,
In response to this, it is set to the download ready state, outputs a prohibition signal to the signal output side, and at the start of the download, if a permission signal is given to the signal input side, it is set to the download permission state and the control data destined for itself is downloaded. It is configured to input and to give a permission signal to the signal input side of the next-stage pipeline element upon completion of input of the data.

According to another aspect of the data processor of the present invention, the processing section further includes a plurality of pipelines, and the download section further has a plurality of input ports and a plurality of output ports on its signal input side and signal output side. A plurality of pipelines, each of the plurality of input ports and each of the plurality of output ports are connected to the signal input side of each of the first pipeline element and the signal output side of the second pipeline element, Configured to selectively download lines.

According to a third aspect of the present invention, there is provided the data processing device, wherein the predetermined order is a download order for each pipeline element in the pipeline.

According to another aspect of the data processing device of the present invention, the download section described above outputs a prohibition signal from each pipeline to its signal input side in response to outputting a prohibition signal from its signal output side to each pipeline. When input, it is characterized in that it is detected that each pipeline is in a download ready state.

According to a fifth aspect of the present invention, in the data processing device, the download unit outputs a permission signal from each pipeline to its signal input side in response to the permission signal output from its signal output side to each pipeline. When input, it is detected that the download is completed in each pipeline.

[0020]

In the data processing device according to each of the first to fifth aspects, since it is possible to connect the download unit to each pipeline unit, there is only one download unit regardless of the number of pipeline elements in the pipeline. Of course, it is not necessary to change the number of wires and the number of data buses related to the connection between the download unit and each pipeline.

In the data processing device according to the second aspect, since one download unit and a plurality of pipelines can be connected, only one download unit is required regardless of the number of pipelines.

Further, one of the plurality of pipelines is selectively downloaded by the download section.

In the data processing device according to the third aspect, each pipeline element in each pipeline is transferred to the download permitted state in accordance with a predetermined download order and the corresponding control data is downloaded.

In the data processing device according to the fourth aspect, the download section detects the completion of the download preparation state in each pipeline prior to the download.

In the data processing device according to the fifth aspect, at the time of downloading, the download section detects the completion of the download in each pipeline.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a pipeline processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a pipeline element according to an embodiment of the present invention. FIG. 3 is a block diagram of a pipeline processing apparatus according to another embodiment of the present invention.

In FIG. 1, four pipeline elements 21 ...
A pipeline processor is shown with 24 connected in series.

In FIG. 1, the pipeline processing unit downloads the pipeline elements 21 to 24 and program data for controlling each element so as to process the pipeline input I and output the pipeline output O. Includes download hardware 36.

Pipeline elements 21-24 are connected in series via data buses 25-29 and control signal lines 30-34. The pipeline elements 21 to 24 are provided by the download hardware 36 when downloading program data.
The program data is downloaded from the download data bus 12 while being controlled by the control signal lines 30 to 34.

The download hardware 36 is
Prior to the start of downloading to the corresponding pipeline, the download inhibit signal S1 is input / output to detect the completion of the download preparation state of the pipeline, and the download enable signal S2 is input / output at the start of the download of the pipeline. A signal input / output unit 361 and a state detection unit 362 for detecting completion of download are included.

In this embodiment, the control signal lines 30 to 34 are used.
With respect to each pipeline element adjacent to each other via the control signal line, the element on the output side of the control signal line is referred to as an “element in the next stage”, and the element on the input side of the control signal line is referred to as an “element in the previous stage”.

FIG. 2 shows a pipeline element according to an embodiment of the present invention. The pipeline element PE analyzes the program data given from the function block 1 which is a general-purpose processing function, the non-volatile memory 2 for storing the program data relating to the function control of the function block 1, and the download data bus 12. In accordance with the input signal via the protocol analyzer 3 which outputs the program data to the data bus 13 and outputs the signal to the download control signal line 9 and the download control signal lines 9 and 10, the signal is sent to the memory write control bus 8 and the output control signal line 11. It includes a memory write controller 4 for outputting.

In operation, when the program data is downloaded from the download data bus 12, the protocol analyzer 3 inputs the data addressed to itself from the bus 12 and analyzes it. The download data input via the bus 13 is sent to the memory 2.

On the other hand, when the memory write controller 4 inputs the download permission signal S2 via the download control signal line 10, the memory write controller 4 accordingly becomes the download permission state and sends the write control signal to the memory 2 via the memory write control bus 8. At the same time, the download non-permission signal is sent to the output control line 11 to the pipeline element at the preceding stage.

The non-volatile memory 2 writes the program data supplied via the data bus 18 based on the write control signal supplied from the control bus 8.

After that, when the protocol analyzer 3 detects the end of the download data input via the data bus 12, the data transmission to the bus 13 is stopped accordingly and the download to the controller 4 via the control signal line 9 is performed. Notify completion.

When the controller 4 receives the completion notification, it accordingly controls the memory 2 via the control bus 8 to complete the data writing.

Next, when the pipeline processing is started,
The function block 1 stores the pipeline element input PI from the next stage pipeline element or the pipeline input I provided from the pipeline input bus 6 into the memory 2
Processing based on the program data transmitted by the control bus 5 of FIG. Then, the pipeline element output PO is sent to the preceding pipeline element or pipeline output O via the pipeline output bus 7.

In the present embodiment, the download to each pipeline element is performed so that the destination of the data to be downloaded there and the pipeline element selected as the data transfer destination match.

In other words, the order of pipeline elements to be downloaded is determined in advance, the pipeline elements are selected according to the order, and the data is transferred in that order.

To implement this, first the order of pipeline elements to be downloaded is determined.

Next, the plurality of pipeline elements are connected to each other according to the determined order. That is, as shown in FIG. 2, the pipeline element download control signal line 10 for inputting signals (download prohibition signal S1 and download permission signal S2) for starting the download operation from the pipeline element in the previous stage. And the pipeline control element of the next stage is provided with the output control circuit 11 for outputting the signal (the download prohibition signal S1 and the download permission signal S2) for controlling the download operation. The output control line 11 of the element is connected to the download control signal line 10 of the pipeline element in which the (i + 1) th download is performed.

Hereinafter, the output control line 11 and the download control signal line 10 are connected in the order in which the download is performed, and one chain of a plurality of pipeline elements is completed. This chain is independent of the chain of pipelines (the chain of data transfers between the data buses from pipeline input I to pipeline output O).

It is now assumed that the apparatus is configured, for example, as shown in FIG. 1 according to the chain of pipeline elements according to the download order described above.

First, for downloading, the download hardware 36 gives a download prohibition (non-permission) signal S1 to the control signal line 30 (download control signal line 10) on the input side of the element 24 at the head of the pipeline. As a result, the control signal line 31 on the output side of the pipeline element 24 is
(Output control line 11) is also provided with the download prohibition signal S1, and the download prohibition signal S1 is transmitted to all the pipeline elements below.

Pipeline element 2 at the tail of the pipeline
The signal on the control signal line 34 (output control line 11) on the output side of 1 is the signal input / output unit 361 of the download hardware 36.
Is input and is monitored by the state detection unit 362, and if it is the download prohibition signal S1, it is confirmed that the preparation for download is completed in all the pipeline elements 21 to 24 of the pipeline.

In response to the detection of the completion of the download preparation described above, the signal input / output unit 361 of the download hardware 36 next outputs the control signal line 30 (download control signal The download authorization signal S2 is provided via line 10). In response to this, the pipeline element 24 is set to the download permitted state. The hardware 36 sends the download data for the element 24 via the data bus 12 and then sends a completion code in response to all the data for the element 24 being sent.

Since the pipeline element 24 has been set to the download permitting state, the data addressed to itself downloaded via the data bus 12 is fetched and written in the non-volatile memory 2. After that, when the controller 4 detects the download completion notification via the protocol analyzer 3 and the control signal line 9, the download permission signal S2 is sent to the next pipeline element 23 via the control signal line 31 (output control line 11). give.

The pipeline element that has finished downloading will not take in data from the download data bus 12 thereafter unless the download inhibit signal S1 is input again via the control signal line 10 (control signal line 30). .

As described above, since the download hardware 36 sends the data of each pipeline element to the data bus 12 in a predetermined download order, the data corresponding to each pipeline element is downloaded according to the download order. Then, the download of the final pipeline element 21 is completed.

The signal input / output unit 361 and the state detection unit 362 of the download hardware 36 receive the download permission signal S2 from the output control line 11 (control signal line 34) of the pipeline element 21, and accordingly all pipeline elements are responded. Detect that the download to is complete.

As described above, according to this embodiment, the download hardware 36 corresponds to the pipeline 1
Since there are three pipeline elements, even if the number of pipeline elements in the pipeline increases, the pipeline and hardware 3
No change is made to the connection form with 6, and the hardware required for downloading data to the pipeline can be made extremely simple.

By the way, in the apparatus of FIG. 1, the pipeline elements are combined into one download chain by the control signal line, but it is not limited to this. That is, it is possible to divide a plurality of pipeline elements into a plurality of pipelines in advance and perform partial download to the selected pipeline. This example is shown in FIG.

In the apparatus shown in FIG. 3, the download chain is divided into, for example, two parts to enable partial download.

In the apparatus of FIG. 3, pipeline elements 41 to
Including 44, a first download chain of elements 41 and 42 and a second download chain of elements 43 and 44 are constructed.

The download of each download chain is controlled by the download hardware 57 including the signal input / output unit 571 and the status detection unit 572, and the hardware 57 is the same as the download hardware 36 described in FIG. Either one of the selected first and second download chains can be downloaded individually.

It is now assumed that the first download chain is selected as the download target.

First, the hardware 57 starts with the control signal line 50.
To the download prohibition signal S via the signal input / output unit 571.
When 1 is sent and then the download prohibition signal S1 is input through the control signal line 52, the state detection unit 572 detects that the first download chain is in the download ready state.

The hardware 57 then controls the control signal line 50.
To the download permission signal S via the signal input / output unit 571.
2 is transmitted, and the data corresponding to each element is downloaded according to a predetermined download order.

When the download of the hardware 57 is completed and the download permission signal S2 is input from the signal input / output unit 571 through the control signal line 52, the state detection unit 57 is detected.
2 confirms the completion of the download in the first download chain.

The second download chain is also performed in the same manner as the first download chain, and the description thereof will be omitted.

As described above, according to the apparatus of FIG. 3, since the chain of FIG. 1 is further divided into two and partial download to the selected chain is possible, flexibility in downloading is improved.

[0065]

In the data processing device according to each of the first to fifth aspects, it is possible to connect the download unit to each pipeline unit. As a result, only one download unit is required regardless of the number of pipeline elements, and the number of wirings and data buses related to the connection between the download unit and the pipeline does not change at all, so the pipeline can be implemented using a simple hardware interface. Control data can be downloaded to each of the constituent pipeline elements.

According to the data processor of claim 2, 1
It is possible to connect one download section and multiple pipelines. As a result, only one download unit is required regardless of the number of pipelines. Therefore, even if the number of pipelines and the number of pipeline elements that make up each pipeline increase, each pipeline element can be used with a simple hardware interface. The control data can be downloaded to.

Further, since the download section can download to any one of the pipelines, the flexibility of the download process is improved.

In the data processing device according to any one of claims 3 to 5, each pipeline element shifts to the download permitted state according to the download order, and the download section starts the download after confirming the download preparation state of each pipeline. However, since the completion of the download is detected after that, the certainty of the download to each pipeline and each pipeline element is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a pipeline processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a pipeline element according to an embodiment of the present invention.

FIG. 3 is a block diagram of a pipeline processing device according to another embodiment of the present invention.

FIG. 4A and FIG. 4B are diagrams showing first and second configuration examples of a conventional pipeline processing apparatus.

5A and 5B are diagrams showing third and fourth configuration examples of a conventional pipeline processing apparatus.

[Explanation of symbols]

 1 Function Block 2 Non-Volatile Memory 3 Protocol Analyzer 4 Memory Write Controller 21-24, 41-44 and PE Pipeline Element 36 and 57 Download Hardware S1 Download Disable Signal S2 Download Permission Signal A considerable part is shown.

Claims (5)

[Claims] 1. A processing unit including a pipeline, wherein each of a plurality of pipeline elements having a processing function includes a pipeline in which a signal output side of a preceding stage element and a signal input side of a next stage element are connected in series in a predetermined order. On the signal input side of the head pipeline element and on the signal output side of the tail pipeline element of the pipeline,
The signal output side and the signal input side are respectively connected, and a download unit for downloading control data relating to the processing function to each of the pipeline elements via a common bus is provided, and each of the elements is provided in the download. In advance, a prohibition signal is given to the signal input side, and accordingly, a download preparation state is set,
The prohibition signal is output to the signal output side, and at the start of the download, when the permission signal is given to the signal input side, the control data addressed to itself and downloaded in response to the permission state is input. A data processing device, wherein the permission signal is given to a signal input side of the next-stage pipeline element in response to completion of input of the control data. 2. The processing unit further includes a plurality of the pipelines, and the download unit further has a plurality of input ports and a plurality of output ports on a signal input side and an output side thereof, respectively. Each of the plurality of input ports and each of the plurality of output ports are connected to the signal input side of each head pipeline element and the signal output side of each tail pipeline element, and are selectively connected to either pipeline. The data processing device according to claim 1, wherein the data is downloaded to the data processing device. 3. The data processing device according to claim 1, wherein the predetermined order is the order of the download to each pipeline element in the pipeline. 4. The download section, when the prohibit signal is input from the pipelines to the signal input side in response to the prohibit signal being output from the signal output side to the pipelines, 4. The data processing device according to claim 1, wherein the data processing device detects that the line is in the download preparation state. 5. The download section, when the enable signal is input from the pipelines to the signal input side in response to the output of the enable signal from the signal output side to the pipelines, 5. The data processing device according to claim 1, wherein the completion of the download is detected on a line.