JPH03189728A - Register designating system for double word access instruction - Google Patents

Abstract

PURPOSE:To facilitate the designation of a register number by designating a single object double word access instruction based on the value of a register designating field for the code of the double word access instruction and then designating another register number with the output of a register designating number generating circuit. CONSTITUTION:The value of a register designating field of a double word access instruction is inputted to a register number generating circuit 5 together with the vale of a qualification register 4. The circuit 5 produces the register numbers based on these input values. The number of one of two registers used to the double word access instruction is designated based on the number of one of both registers. The other register number is designated with the output of the circuit 5. Thus the register Nos can be designated with higher flexibility under such a restriction where only a single register number can be written into an instruction code.

Description

[Detailed Description of the Invention] [Summary] Regarding the register specification method for double word access instructions, we have developed a more flexible register specification method under the constraint that only one register number can be written in the instruction code of double word access instructions. The purpose is to enable register number specification, and in computers with double word access instructions, the modified register that can be rewritten by the instruction and the value of the register specification field of the instruction code of the double word access instruction. A register number generation circuit that outputs a register number based on the value of a modified register is provided, and one of the two register numbers that are the target of a double word access instruction is specified by the value of the register specification field in the code,
The configuration is such that the number of the other register is designated by the output of the register designation number generation circuit.

[Industrial application field]

The present invention relates to a register specification system for double word access instructions in a computer having double word access instructions.

[Conventional technology]

Instructions for sending and receiving data between registers and other registers, and between registers and memory are provided as basic instructions in ordinary computers. Furthermore, various lengths of data to be sent and received, such as byte, word, and double word, are often supported. Here, double word
When focusing on access instructions, it would be ideal if the two target registers could be embedded independently in the instruction code, but due to consistency with word instructions and constraints from the overall instruction system, The reality is that only register numbers can be used in instructions. Therefore, in the prior art, a highly restrictive method has been adopted, such as specifying even-numbered registers in the instruction code and combining them with odd-numbered registers that are one more.

[Problem to be solved by the invention]

As described above, in the conventional technology, it is not possible to freely designate two registers to be subjected to a double word access instruction, and as a result, the degree of freedom in creating a program is restricted.

The present invention was created in view of this point, and is a double code that allows more flexible register number specification under the constraint that only one register number can be written in an instruction code. The purpose is to provide a register specification method for word access instructions.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. In the present invention, a special internal register called a modification register 4 is provided, and a register number circuit 5 is provided which can generate another register number from the value of the register designation field in the instruction code and the contents of the modification register 4. The register number generation circuit 5 is preferably an exclusive OR, but other types may be used.

[Effect]

The value of the register designation field of the double word access instruction and the value of the modification register 4 are input to the register number generation circuit 5. The register number generation circuit 5 generates register numbers based on these inputs. One of the two registers targeted by the double word access instruction
The number of registers is specified by the value of the register specification field of the double word access instruction, and
The number of each register is designated by the output of the register number generation circuit 5.

〔Example〕

FIG. 2 is a diagram of one embodiment of the present invention.

In the figure, 1 is a register specification field in the instruction code, 2-1 and 2-2 are two ports of the register, and 3-
1 and 3-2 are address input signals to each port, 4 is a modification register, and 5 is a register number generation circuit, respectively.

For example, a two-port register file can be used as a set of registers. The contents of register specification field 1 remain as they are, and address 3 is sent to port 2-1.
It becomes -1. The value of the register designation field 1 and the value of the modification register 4 are input to the register number generation circuit 5. The address input 3-2 is a signal output from the register number generation circuit 5.

Qualification register 4 has the same bit width as register specification field 1. For example, corresponding bits of register designation field 1 and modification register 4 are subjected to some operation in register number generation circuit 5, and address input 3-
It becomes 2. The value of the modification register 4 can be set by a program. As an example of the operation performed by the register number generation circuit 5, consider exclusive OR. i-th of modification register 4
Assuming that the bit is "1", the value of the i-th bit in the bit string of register designation field 1 is inverted. If only the least significant bit of the modification register 4 is set to "1", it will be the same as the odd/even system described in the prior art.

FIG. 3 is a block diagram showing an example of the configuration of the register number generation circuit 5. As shown in FIG. In the same figure, 5-1 is a selection flag, 5-
2 indicates a calculation unit.

The arithmetic unit 5-2 has functions such as exclusive OR, logical product, logical sum, negation, addition, and subtraction, for example. Which of these calculations is to be performed is selected by the selection flag 5-1. The value of the selection flag 5-1 can be set by a program.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to designate two target register numbers in a double word access instruction more flexibly than before. This makes it possible to use limited register resources efficiently, which greatly contributes to improving the quality of programs.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram showing an example of the configuration of a register number generation circuit of the present invention. l...Register specification field in instruction code, 2-
1 and 2-2... Two ports of register, 3-1 and 3
-2...Address input signal to each port, 4...Modification register, 5...Register number generation circuit, 5-1.
...Selection flag, 5-2...Arithmetic unit.

Claims (1)

[Claims] In a computer having a double word access instruction, a modification register (4) that can be rewritten by the instruction, and a value of a register specification field of an instruction code of the double word access instruction and a modification register (4). A register number generation circuit (5) that outputs a register number based on the value of
One of the two register numbers targeted by the double word access instruction is specified by the value of the register specification field of the instruction code of the double word access instruction, and the number of the other register is specified by the value of the register specification field of the instruction code of the double word access instruction. A register designation method for double word access instructions characterized in that a number is designated by the output of a register designation number generation circuit (5).