JPH0828703B2 - Signal transmission circuit - Google Patents
Signal transmission circuitInfo
- Publication number
- JPH0828703B2 JPH0828703B2 JP15099789A JP15099789A JPH0828703B2 JP H0828703 B2 JPH0828703 B2 JP H0828703B2 JP 15099789 A JP15099789 A JP 15099789A JP 15099789 A JP15099789 A JP 15099789A JP H0828703 B2 JPH0828703 B2 JP H0828703B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- capacitor
- output
- transmission line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） この発明は信号送出回路に関し、特にたとえば１つの
伝送路に複数の場所からのデータ信号を送る多重伝送に
使用される、信号送出回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit, and more particularly to a signal transmission circuit used for multiplex transmission for transmitting data signals from a plurality of locations to one transmission path.
（従来技術） 従来、多重伝送に使用される信号送出回路としては、
たとえば伝送路に伝送される同期信号をカウント、時分
割的にデータ信号を伝送路に送出する回路があった。こ
の場合、同期信号としては、たとえば一定周期の矩形波
が用いられている。そして、複数の信号送出回路では、
それぞれ所定の数だけ同期信号をカウントしたとき、伝
送路にデータ信号が送出される。このようにして、１つ
の伝送路に複数の場所からデータ信号が送出され、それ
らを処理することができる。(Prior Art) Conventionally, as a signal transmission circuit used for multiplex transmission,
For example, there is a circuit that counts the synchronization signals transmitted to the transmission line and sends the data signal to the transmission line in a time division manner. In this case, as the synchronizing signal, for example, a rectangular wave having a constant period is used. And in the plurality of signal transmission circuits,
When the synchronization signals are counted by a predetermined number, the data signal is sent to the transmission line. In this way, data signals can be sent out from a plurality of places on one transmission path and processed.
（発明が解決しようとする課題） しかしながら、従来の信号送出回路では、データ信号
を送出するとき、同期信号の極性とデータ信号の極性と
が同じであった。そのため、データ信号を受信しても、
同期信号とデータ信号との区別が困難であった。(Problems to be Solved by the Invention) However, in the conventional signal transmission circuit, when transmitting the data signal, the polarity of the synchronization signal and the polarity of the data signal were the same. Therefore, even if the data signal is received,
It was difficult to distinguish the sync signal and the data signal.
それゆえに、この発明の主たる目的は、同期信号と逆
の極性のデータ信号を送出することができる、信号送出
回路を提供することである。Therefore, a main object of the present invention is to provide a signal sending circuit capable of sending a data signal having a polarity opposite to that of a sync signal.
（課題を解決するための手段） この発明は、伝送路に供給される同期信号に応じて伝
送路にデータ信号を送出する信号送出回路であって、同
期信号とデータ信号とが同期したことに応じて「Ｌ」レ
ベルの信号が出力される同期回路と、同期回路の出力側
にその一端が接続され、同期回路の出力が「Ｈ」レベル
のときに充電され、同期回路の出力が「Ｌ」レベルのと
きに放電されるコンデンサ回路と、コンデンサ回路の他
端と伝送路との間に接続され、同期回路の出力が「Ｌ」
レベルになったことに応じて閉じるスイッチング回路と
を含む、信号送出回路である。(Means for Solving the Problem) The present invention relates to a signal transmission circuit for transmitting a data signal to a transmission line in accordance with a synchronization signal supplied to the transmission line, in which the synchronization signal and the data signal are synchronized. In response to the synchronous circuit outputting an “L” level signal, one end of the synchronous circuit is connected to the output side of the synchronous circuit, and when the output of the synchronous circuit is at the “H” level, the synchronous circuit outputs “L”. The capacitor circuit that is discharged when the level is "L" is connected between the other end of the capacitor circuit and the transmission line, and the output of the synchronous circuit is "L".
A signal transmission circuit including a switching circuit that closes in response to a level change.
（作用） 同期回路の出力が「Ｈ」レベルにあるとき、コンデン
サ回路の一端側が正、他端側が負となってコンデンサが
充電される。この状態で同期回路の出力が「Ｌ」レベル
になると、スイッチング回路が閉じて、コンデンサ回路
と伝送路とが電気的に接続される。このとき、コンデン
サ回路の一端側は負となり、他端側は正となる。したが
って、コンデンサの極性も逆方向となり、充電されてい
た電荷は放電される。(Operation) When the output of the synchronous circuit is at "H" level, one end of the capacitor circuit becomes positive and the other end becomes negative, and the capacitor is charged. When the output of the synchronizing circuit becomes "L" level in this state, the switching circuit is closed and the capacitor circuit and the transmission path are electrically connected. At this time, one end of the capacitor circuit becomes negative and the other end becomes positive. Therefore, the polarity of the capacitor is also in the opposite direction, and the charge that has been charged is discharged.
（発明の効果） この発明によれば、同期回路の出力の変化によって、
コンデンサ回路の両端の電圧の極性が変化し、スイッチ
ング回路が閉じたとき（オンの状態になったとき）、同
期信号と逆の極性のデータ信号が伝送路に送出される。
したがって、同期信号とデータ信号とを区別することが
簡単であり、データ信号の処理を確実にすることができ
る。(Effect of the Invention) According to the present invention, the change in the output of the synchronous circuit causes
When the polarity of the voltage across the capacitor circuit changes and the switching circuit is closed (turned on), the data signal having the opposite polarity to the sync signal is sent to the transmission line.
Therefore, it is easy to distinguish the synchronization signal and the data signal, and the processing of the data signal can be ensured.
この発明の上述の目的，その他の目的，特徴および利
点は、図面を参照して行う以下の実施例の詳細な説明か
ら一層明らかとなろう。The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.
（実施例） 第１図はこの発明の一実施例を示す回路図である。こ
の信号送出回路10は伝送路12に接続される。(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of the present invention. The signal transmission circuit 10 is connected to the transmission line 12.
信号送出回路10は同期回路13を含む。同期回路13はイ
ンバータ14とNAND回路16とを含み、インバータ14の入力
側に伝送路12が接続される。インバータ14の出力側は、
NAND回路16の一方の入力側に接続される。さらに、NAND
回路16の他方の入力側には、データ信号用信号線18が接
続される。The signal transmission circuit 10 includes a synchronization circuit 13. The synchronization circuit 13 includes an inverter 14 and a NAND circuit 16, and the transmission line 12 is connected to the input side of the inverter 14. The output side of the inverter 14 is
It is connected to one input side of the NAND circuit 16. In addition, NAND
A data signal signal line 18 is connected to the other input side of the circuit 16.
NAND回路16の出力側はコンデンサ回路19の一端に接続
される。コンデンサ回路19は、抵抗20,コンデンサ22お
よびダイオード24を含む。そしてNAND回路16の出力側は
抵抗20の一端に接続され、抵抗20の他端はコンデンサ22
の一端に接続される。コンデンサ22の他端はダイオード
24のアノードに接続され、ダイオード24のカソードは接
地される。さらに、コンデンサ22の他端は、スイッチン
グ回路26を介して伝送路12に接続される。The output side of the NAND circuit 16 is connected to one end of the capacitor circuit 19. The capacitor circuit 19 includes a resistor 20, a capacitor 22 and a diode 24. The output side of the NAND circuit 16 is connected to one end of the resistor 20, and the other end of the resistor 20 is connected to the capacitor 22.
Connected to one end of. The other end of the capacitor 22 is a diode
It is connected to the anode of 24 and the cathode of the diode 24 is grounded. Further, the other end of the capacitor 22 is connected to the transmission line 12 via the switching circuit 26.
スイッチング回路26は、NAND回路16の出力に同期し、
NAND回路16の出力が「Ｈ」レベルのときに開いて「Ｌ」
レベルのときに閉じる。The switching circuit 26 is synchronized with the output of the NAND circuit 16,
Open when the output of NAND circuit 16 is "H" level, then "L"
Close when level.
第２図は、それぞれインバータ14の入力側（ａ）点,N
AND回路16の一方の入力側（ｂ）点,NAND回路16の他方の
入力側（ｃ）点およびNAND回路16の出力側（ｄ）点にお
ける信号波形を示す波形図である。伝送路12には、第２
図の（ａ）に示すように、一定周期の矩形の同期信号が
伝送される。この同期信号は、第２図の（ｂ）に示すよ
うに、インバータ14によって反転させられる。この同期
信号を所定の数だけカウントしたとき、第２図の（ｃ）
に示すように、NAND回路16の他方の入力側にデータ信号
が入力される。FIG. 2 shows points (a), N on the input side of the inverter 14, respectively.
7 is a waveform diagram showing signal waveforms at one input side (b) point of the AND circuit 16, the other input side (c) point of the NAND circuit 16 and an output side (d) point of the NAND circuit 16. FIG. The transmission line 12 has a second
As shown in (a) of the figure, a rectangular synchronization signal having a constant period is transmitted. This synchronizing signal is inverted by the inverter 14 as shown in FIG. When this synchronization signal is counted by a predetermined number, (c) of FIG.
As shown in, the data signal is input to the other input side of the NAND circuit 16.
NAND回路16にデータ信号が入力されない間、（ｄ）点
の出力は「Ｈ」となる。このとき、スイッチング回路26
は開いた状態（オフの状態）であり、信号送出回路10の
出力側は伝送路12と切り離されている。したがって、抵
抗20,コンデンサ22およびダイオード24で形成される回
路が働き、コンデンサ22の一端側が正、コンデンサ22の
他端側が負の状態となって、コンデンサ22が充電され
る。While the data signal is not input to the NAND circuit 16, the output at point (d) is "H". At this time, the switching circuit 26
Is in an open state (off state), and the output side of the signal transmission circuit 10 is separated from the transmission line 12. Therefore, the circuit formed by the resistor 20, the capacitor 22, and the diode 24 operates, one end side of the capacitor 22 is in the positive state, and the other end side of the capacitor 22 is in the negative state, and the capacitor 22 is charged.
さらに、反転された同期信号とデータ信号とが両方と
も「Ｈ」になったとき、（ｄ）点の出力は「Ｌ」とな
る。このとき、スイッチング回路26は閉じた状態（オン
の状態）になり、信号送出回路10の出力側と伝送路12と
は接続される。この場合、（ｄ）点の出力が「Ｌ」にな
るため、コンデンサ22の両端の極性は逆になり、コンデ
ンサ22の一端側が負，コンデンサ22の他端側が正とな
る。そのため、スイッチング回路26,コンデンサ22およ
び抵抗20で形成される回路が働き、充電されたコンデン
サ22が放電する。このとき、コンデンサ22の他端側は、
伝送路12に対して負の状態となり、伝送路12に負のデー
タ信号が送出される。Furthermore, when both the inverted sync signal and data signal are "H", the output at point (d) is "L". At this time, the switching circuit 26 is in a closed state (on state), and the output side of the signal transmission circuit 10 and the transmission line 12 are connected. In this case, since the output at the point (d) becomes "L", the polarities of both ends of the capacitor 22 are reversed, one end of the capacitor 22 is negative and the other end of the capacitor 22 is positive. Therefore, the circuit formed by the switching circuit 26, the capacitor 22, and the resistor 20 operates, and the charged capacitor 22 is discharged. At this time, the other end of the capacitor 22 is
The transmission line 12 is in a negative state, and a negative data signal is transmitted to the transmission line 12.
このように、この発明によれば、同期信号が正である
のに対し、負のデータ信号が送出される。したがって、
同期信号とデータ信号とが区別しやすく、データ信号の
処理が確実となる。Thus, according to the present invention, the sync signal is positive, whereas the negative data signal is transmitted. Therefore,
The sync signal and the data signal can be easily distinguished, and the processing of the data signal is ensured.
第１図はこの発明の一実施例を示す回路図である。 第２図は第１図に示す信号送出回路の（ａ）点，（ｂ）
点，（ｃ）点および（ｄ）点における波形図である。 図において、10は信号送出回路、12は伝送路、13は同期
回路、14はインバータ、16はNAND回路、18はデータ信号
用信号線、19はコンデンサ回路、20は抵抗、22はコンデ
ンサ、24はダイオード、26はスイッチング回路を示す。FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 shows points (a) and (b) of the signal transmission circuit shown in FIG.
It is a waveform diagram in a point, a (c) point, and a (d) point. In the figure, 10 is a signal sending circuit, 12 is a transmission line, 13 is a synchronizing circuit, 14 is an inverter, 16 is a NAND circuit, 18 is a data signal signal line, 19 is a capacitor circuit, 20 is a resistor, 22 is a capacitor, 24 Is a diode and 26 is a switching circuit.
Claims (1)
伝送路にデータ信号を送出する信号送出回路であって、 前記同期信号と前記データ信号とが同期したことに応じ
て「Ｌ」レベルの信号が出力される同期回路、 前記同期回路の出力側にその一端が接続され、前記同期
回路の出力が「Ｈ」レベルのときに充電され、前記同期
回路の出力が「Ｌ」レベルのときに放電されるコンデン
サ回路、および 前記コンデンサ回路の他端と前記伝送路との間に接続さ
れ、前記同期回路の出力が「Ｌ」レベルになったことに
応じて閉じるスイッチング回路を含む、信号送出回路。1. A signal transmission circuit for transmitting a data signal to the transmission line in response to a synchronization signal supplied to the transmission line, wherein the signal is "L" when the synchronization signal and the data signal are synchronized. A synchronous circuit for outputting a level signal, one end of which is connected to the output side of the synchronous circuit, charged when the output of the synchronous circuit is at "H" level, and the output of the synchronous circuit is at "L" level A signal, which includes a capacitor circuit that is sometimes discharged, and a switching circuit that is connected between the other end of the capacitor circuit and the transmission line and that is closed in response to the output of the synchronous circuit becoming the “L” level. Sending circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15099789A JPH0828703B2 (en) | 1989-06-13 | 1989-06-13 | Signal transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15099789A JPH0828703B2 (en) | 1989-06-13 | 1989-06-13 | Signal transmission circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0314336A JPH0314336A (en) | 1991-01-23 |
| JPH0828703B2 true JPH0828703B2 (en) | 1996-03-21 |
Family
ID=15509028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15099789A Expired - Lifetime JPH0828703B2 (en) | 1989-06-13 | 1989-06-13 | Signal transmission circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828703B2 (en) |
-
1989
- 1989-06-13 JP JP15099789A patent/JPH0828703B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0314336A (en) | 1991-01-23 |
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