JPH02158280A - Pedestal clamping circuit - Google Patents

Abstract

PURPOSE:To prevent distortion in an output signal or an error in the next processing circuit occurring by extending a clamping pulse setting its leading or trailing edge which becomes the forefront of a synchronizing signal pulse as an origin longer than an on-going one by the width of the synchronizing signal pulse. CONSTITUTION:The clamping pulse with prescribed width setting the leading or trailing edge of the forefront of the synchronizing signal pulse as the origin is inputted to a clamping circuit 8, and the electric charge of a coupling capacitor is discharged, then, the DC component of an image signal is reproduced. since the width of the clamping pulse outputted from a one-shot circuit 51 is decided by a time constant element assembled in the one-shot circuit 51, it is set at the pulse width within which the trailing edge of the clamping pulse can be housed in a back porch. Therefore, the clamping pulse can be added on the clamping circuit 8 earlier and longer than the on-going one. In such a way, it is possible to obtain a pedestal clamping circuit in which no distortion in the output signal or no error in the next processing circuit occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to stabilizing the pedestal level of an image signal of a video interface device connected to a printer or the like and preventing distortion.

[Conventional technology]

Figure 3 is a groove diagram of a conventional pedestal clamp circuit that reproduces the DC component of a generally known image signal, and Figures 4 and 5 are the relationships among the input signal, crank pulse, and output signal in the circuit shown in Figure 3. FIG. In Figure 3, (1)
(21) is the input terminal for the image signal from which the synchronization signal has been separated; (3) is the terminal for the pedestal clamp circuit; and (3) is the input terminal for the A/D conversion circuit, which is the next processing circuit. (5) is a clamp pulse generation circuit that receives an input synchronizing signal pulse and generates a clamp pulse based on the rising edge of the latter stage of the pulse, and the width of the generated clamp pulse is fixed. (8) is a clamp circuit It consists of a coupling capacitor, a group of transistors, and a DC constant voltage gear that sets the pedestal level of the output signal.

The operation of the clamp circuit (8) configured as described above will be explained. The image signal input from the input terminal (2) is sent to the output terminal (
3). At this time, the voltage at the output terminal (
(pedestal level) gradually rises from the voltage of the constant voltage source (reference pedestal level). Here, when a clamp pulse is input from the clamp pulse generation circuit (5) to the base of the transistor, the collector and emitter of the transistor become conductive for the clamp pulse width time, and the charged charge is transferred to the transistor more than the coupling capacitor. -, and the DC component is regenerated by returning the voltage at the output terminal (3) to the reference pedestal level. For example, in a host computer that is an input source of an image signal, the synchronization signal frequency (synchronization signal period) of the image signal differs depending on the manufacturer and model, and the width of the image data signal (g) with respect to the synchronization signal period (7). The proportions also differ.

The signal processing state in the clamp circuit (8) depending on the ratio of the length of the synchronization signal period (1) and the width of the image data signal (6) will be explained with reference to FIGS. 4 and 5. Figure 4 shows the case where the synchronization signal period (1) is short. Generally, when the synchronization signal period (7) is short, the ratio of the image data signal 0 width to the synchronization signal period ω is large, and the back porch If the clamp pulse width is too long, the clamp pulse and the image data signal (g) will interfere, causing distortion in the output signal.To avoid this, the clamp pulse width should be shortened (if In the case of an input signal with a long synchronization signal period (1), the pedestal level M does not return to the reference pedestal level (Vo).The reason for this is that the charging time for the coupling capacitor becomes longer, and therefore the pedestal level M does not return to the reference pedestal level (Vo). Since the rise in the voltage is large and the clamp pulse width is short, the discharging time of the coupling capacitor is short.
Since the conduction state of the transistor is cut off before the discharge of the coupling capacitor Yu is sufficiently completed, the pedestal level (to) cannot return to the reference pedestal level (vo). This causes an error in the conversion process in the A/D conversion circuit αQ in the next process.

This state is shown in FIG.

[Problem to be solved by the invention]

In the conventional pedestal clamp circuit as described above, a clamp pulse with a width corresponding to the average synchronization signal period (1) length and the ratio of the image data signal (6) width to this is input to the clamp circuit. Therefore, depending on the model of the host computer that is the input source of the image signal, the length or shortness of the synchronization signal period, or if the ratio of the image data signal width to the synchronization signal period (1) is large, There were problems such as distortion and errors occurring.

This invention was made in order to solve the above-mentioned problems, and the synchronization signal period may be long or short depending on the type of host computer that is the input source of the image signal, or the image data signal width may be different from the synchronization signal period. It is an object of the present invention to obtain a pedestal clamp circuit that does not cause distortion in an output signal or cause errors in a subsequent processing circuit even when the ratio is large.

[Means to solve the problem]

A pedestal clamp circuit according to the present invention includes a clamp pulse generation circuit that generates a clamp pulse based on the leading edge or falling edge of a synchronizing signal pulse of an input image signal, and a clamp pulse generated from the clamp pulse generation circuit. It is equipped with a clamp circuit that receives the image signal and regenerates the DC component of the image signal.

[Effect]

In the pedestal clamp circuit according to the present invention, the clamp pulse whose starting point is the rising or falling edge of the synchronizing signal pulse is longer by the width of the synchronizing signal pulse than in the prior art.

〔Example〕

FIG. 1 is a block diagram of a pedestal clamp circuit showing an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship among input signals, clamp pulses, and output signals of the pedestal clamp circuit of FIG. 1. In the figure, (1).

+2), (3), (8), QG, (1)
, (c) are the same as those described in the above conventional example. (4) is a composite type image signal input terminal, (6
) is a separate circuit that separates the composite image signal into a synchronization signal and an image signal, and Isl is a monostable multivibrator that generates a pulse (clamp pulse) with a constant pulse width by inputting a trigger pulse and outputs it to the clamp circuit (8). The one-shot circuit is a polarity matching circuit for inputting the first rising or falling point of the synchronizing signal pulse as a trigger pulse to the one-shot circuit (incorporated), regardless of the polarity of the input synchronizing signal pulse. is a clamp pulse generation circuit consisting of a one-shot circuit and a pulse polarity matching circuit; (2); r:ts switches the input circuit to the pedestal clamp circuit depending on whether the input signal is a composite type or a separate type; Switching instruction signals for the first and second multiplexers are input from the host computer through signal lines (not shown).

In the pedestal clamp circuit configured as described above, the synchronizing signal pulses separated by the input or the separate circuit (6) are passed through the pulse polarity matching circuit so that the first rising or falling edge of the synchronizing signal pulse is connected to the one-shot circuit @O The polarity of the trigger pulse is matched by inverting the polarity so that the positive polarity is input as the starting trigger. When the trigger pulse is input to the one-shot circuit section υ, a clamp pulse having a predetermined pulse width based on the rising point of the trigger pulse, that is, the first rising or falling point of the synchronizing signal pulse, is output to the clamp circuit (8). ), the false charge in the coupling capacitor is discharged, and the DC component of the image signal is regenerated.

The width of the clamp pulse output from the one-shot circuit Ill is determined by the time constant element (capacitor and resistor) built into the one-shot circuit, so the end (falling edge) of the clamp pulse must be within the pulse width that falls within the back porch. Set.

Therefore, compared to the conventional example, the clamp pulse is applied to the clamp circuit (8) earlier and longer by the width of the synchronizing signal pulse, so the discharge time of the coupling capacitor υ becomes longer, and the clamp pulse and the image data signal 0 are This situation is shown in Figure 2.

〔Effect of the invention〕

As explained above, the present invention includes a clamp pulse generation circuit that generates a clamp pulse based on the leading edge or trailing edge of a synchronizing signal pulse of an input image signal, and a clamp that reproduces a DC component using the clamp pulse. By providing a circuit, the length of the synchronization signal period can be adjusted depending on the model of the host computer that is the input source of the image signal.
Alternatively, even when the ratio of the image data signal width to the synchronization signal period is large, it is possible to obtain a pedestal clamp circuit that does not cause distortion in the output signal or errors in the subsequent processing circuit.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a pedestal clamp circuit showing an embodiment of the present invention, and Fig. 2 is a diagram showing the relationship between the input signal, clamp pulse, and output stop signal in the configuration of Fig. 1. , FIG. 3 is a block diagram of a conventional pedestal clamp circuit, and FIGS. 4 and 5 are diagrams showing the relationships among input signals, clamp pulses, and output signals in the configuration of FIG. 3, respectively. In the figure, (1) is a synchronization signal input terminal, (2) is an image signal input terminal, (3) is an output terminal, (4) is a composite type image signal input terminal, ■ is a clamp pulse generation circuit, and One-shot circuit, Ifi is a pulse polarity matching circuit, (8) is a clamp circuit, ω is a synchronization signal period, (
b) is an image data signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A clamp pulse generation circuit that generates a clamp pulse based on the leading rising or falling edge of the synchronizing signal pulse of the input image signal, and a DC component reproduction of the image signal upon receiving the clamp pulse from this clamp pulse generating circuit. A pedestal clamp circuit characterized by being equipped with a clamp circuit that performs.