JPH0828360B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0828360B2
JPH0828360B2 JP61276300A JP27630086A JPH0828360B2 JP H0828360 B2 JPH0828360 B2 JP H0828360B2 JP 61276300 A JP61276300 A JP 61276300A JP 27630086 A JP27630086 A JP 27630086A JP H0828360 B2 JPH0828360 B2 JP H0828360B2
Authority
JP
Japan
Prior art keywords
film
semiconductor
semiconductor device
region
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61276300A
Other languages
Japanese (ja)
Other versions
JPS63128733A (en
Inventor
政彦 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP61276300A priority Critical patent/JPH0828360B2/en
Publication of JPS63128733A publication Critical patent/JPS63128733A/en
Publication of JPH0828360B2 publication Critical patent/JPH0828360B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、稼働イオンの侵入による特性変化を防止し
た半導体装置に関する。
Description: TECHNICAL FIELD The present invention relates to a semiconductor device in which characteristic changes due to penetration of operating ions are prevented.

〔発明の概要〕[Outline of Invention]

本発明は、半導体基板に形成された抵抗体を有するSR
AM(Static Random Access Memory)等の半導体装置に
於いて、半導体チップを分割するスクライブ領域に半導
体基板と同一導電型の導電領域を形成し、スクライブ領
域に臨む半導体チップの断面を覆うと共に導電領域に接
触している導電膜を形成し、半導体基板に印加されてい
る電位を導電領域を介して導電膜にも印加することによ
って、構成が簡単であるにも拘らず可動イオンの半導体
チップへの侵入を防止して特性が変化しない半導体装置
を提供するものである。
The present invention relates to an SR having a resistor formed on a semiconductor substrate.
In semiconductor devices such as AM (Static Random Access Memory), a conductive region of the same conductivity type as the semiconductor substrate is formed in the scribe region that divides the semiconductor chip, and covers the cross section of the semiconductor chip facing the scribe region and also in the conductive region. By forming a conductive film in contact and applying the potential applied to the semiconductor substrate to the conductive film through the conductive region, mobile ions can enter the semiconductor chip despite the simple structure. The present invention provides a semiconductor device which prevents the above-mentioned phenomenon and does not change its characteristics.

〔従来の技術〕[Conventional technology]

高抵抗型SRAMの抵抗体は、通常多結晶Siにより形成さ
れている。この高抵抗部の形成後、その上には保護膜と
してPSG膜、AsSG膜又はSiO2膜とか、パッシベーション
膜としてプラズマSi3N4膜等が形成される。
The resistor of the high resistance type SRAM is usually formed of polycrystalline Si. After the formation of this high resistance portion, a PSG film, an AsSG film or a SiO 2 film as a protective film, a plasma Si 3 N 4 film or the like as a passivation film is formed thereon.

ところが、プラズマCVD法で形成されたSi3N4膜は水素
を大量に含んでおり、電界とか熱等の外部エネルギーに
よりそのSi3N4膜中の水素は内部に拡散し高抵抗体に侵
入する。
However, the Si 3 N 4 film formed by the plasma CVD method contains a large amount of hydrogen, and hydrogen in the Si 3 N 4 film diffuses inside due to external energy such as electric field and heat, and penetrates into the high resistance body. To do.

一方、電子ビーム又はスパッタ等の処理により発生す
るダメッジを除去するために、H2雰囲気中で熱処理が行
われるが、この水素アニールの際にも、水素が高抵抗体
に侵入する。
On the other hand, a heat treatment is performed in an H 2 atmosphere in order to remove damaging generated by a treatment such as electron beam or sputtering, but hydrogen also infiltrates the high resistance body during this hydrogen annealing.

この様にして、水素が多結晶Siからなる高抵抗体に侵
入すると、高抵抗体の抵抗値が変動してしまい設計値の
抵抗値が得られない問題がある。
In this way, when hydrogen enters the high resistance body made of polycrystalline Si, the resistance value of the high resistance body fluctuates, and there is a problem that the designed resistance value cannot be obtained.

また抵抗値の変動の問題以外にも、半導体チップをパ
ッケージングした後、長期間の使用のうちにナトリウム
イオンとかカリウムイオンが半導体チップに侵入して、
半導体装置の特性を劣化させる問題があった。
In addition to the problem of resistance fluctuation, after packaging the semiconductor chip, sodium ions or potassium ions enter the semiconductor chip during long-term use,
There is a problem that the characteristics of the semiconductor device are deteriorated.

そこで高抵抗体への水素の侵入防止や耐湿性改善のた
めに、本出願人は、先に特願昭61-191229号で、スクラ
イブラインに露出した半導体チップ本体の側面を、Alの
様な水素を透過させない膜や、PSG膜等の水素を吸収す
る膜で被う半導体装置の構造を提案した。
Therefore, in order to prevent hydrogen from penetrating into the high-resistance element and improve the moisture resistance, the applicant of the present application has previously proposed in Japanese Patent Application No. 61-191229 that the side surface of the semiconductor chip main body exposed to the scribe line be made of Al-like material. We proposed the structure of a semiconductor device covered with a hydrogen impermeable film or a hydrogen absorbing film such as a PSG film.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかしこの特許出願の構造を採用しても、なお高抵抗
体の抵抗値やトランジスタの特性が変動する事が判明し
た。本発明者がその原因の究明に努めた結果、スクライ
ブラインの側壁からの可動イオンの侵入が、抵抗値等の
変動の原因となっている事をつきとめた。
However, it was found that the resistance value of the high resistance body and the characteristics of the transistor still fluctuate even if the structure of this patent application is adopted. As a result of the inventor's efforts to investigate the cause, it has been found that the invasion of mobile ions from the side wall of the scribe line is the cause of fluctuations in the resistance value and the like.

この点を第2図に基づいて説明する。半導体処理の一
連の工程が終了した後、スクライブライン9に沿って半
導体ウェーハはスクライブされて個々のペレットに分離
される。半導体装置の表面はパッシベーション膜のプラ
ズマSi3N4膜8で被われているが、スクライブライン領
域のプラズマSi3N4膜8はスクライブを確実に行うため
に除去されている。H+、Na+、Cl-等の可動イオンは、基
板1と露出したプラズマSi3N4膜8の界面から半導体チ
ップ本体に侵入してしまう。
This point will be described with reference to FIG. After completion of a series of semiconductor processing steps, the semiconductor wafer is scribed along the scribe line 9 to be separated into individual pellets. Surface of the semiconductor device have been covered with the plasma the Si 3 N 4 film 8 of the passivation film, plasma the Si 3 N 4 film 8 of the scribe line region is removed in order to ensure scribe. Mobile ions such as H + , Na + and Cl enter the semiconductor chip body from the interface between the substrate 1 and the exposed plasma Si 3 N 4 film 8.

H+が高抵抗体である多結晶Si膜4にまで拡散した場合
には、その抵抗値が変動してしまうと言う問題点があ
る。
If H + diffuses into the polycrystalline Si film 4 which is a high resistance element, there is a problem that the resistance value changes.

半導体チップをパッケージングした後、Na+等のイオ
ンが上記侵入路を通ってチップ本体に到達すると、トラ
ンジスタ特性等が悪化すると言う問題点もある。
After packaging the semiconductor chip, if ions such as Na + reach the chip body through the invasion path, there is a problem that the transistor characteristics and the like deteriorate.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、半導体チップを分割するスクライブ領域に
半導体基板と同一導電型の導電領域を形成し、スクライ
ブ領域に臨む上記半導体チップの断面を覆うと共に導電
領域に接触している導電膜を形成し、半導体基板に印加
されている電位を導電領域を介して導電膜にも印加する
ことによって、前記問題点を解決したものである。
The present invention forms a conductive region of the same conductivity type as a semiconductor substrate in a scribe region that divides a semiconductor chip, and forms a conductive film that covers the cross section of the semiconductor chip facing the scribe region and is in contact with the conductive region, The above-mentioned problem is solved by applying the potential applied to the semiconductor substrate to the conductive film through the conductive region.

〔作用〕[Action]

本発明の半導体装置の構造によれば、本体チップとス
クライブラインの界面で、パッシベーション膜が露出し
ていても、本体チップの側面が導電膜で被われていて、
その導電膜に半導体基板の電位が印加されているので、
電気的バリヤが形成され、外部からH+、Na+、Cl-等の可
動イオンが本体チップに侵入することが阻止される。つ
まり、その導電膜に正のバイアスが加わっていると、
H+、Na+等の正イオンは反発されてチップ内部に侵入で
きず、Cl-等の負イオンは導電膜中に取り込まれてしま
い、何れにしろ可動イオンは本体チップに侵入すること
はできないことになる。
According to the structure of the semiconductor device of the present invention, at the interface between the main body chip and the scribe line, even if the passivation film is exposed, the side surface of the main body chip is covered with the conductive film,
Since the potential of the semiconductor substrate is applied to the conductive film,
An electrical barrier is formed, and mobile ions such as H + , Na + and Cl are prevented from entering the main body chip from the outside. That is, if a positive bias is applied to the conductive film,
Positive ions such as H + and Na + are repelled and cannot enter the inside of the chip, and negative ions such as Cl are taken into the conductive film, and mobile ions cannot enter the main body chip anyway. It will be.

〔実施例〕〔Example〕

第1図Aの断面図と、第1図Bの上面図に基づいて、
本発明の半導体装置の実施例を説明する。通常の製造方
法によりn型Si基板1内にpウェルを形成して周辺CMOS
で、メモリユニットを高抵抗SRAMとした半導体装置を形
成する。この際、n型Si基板1内のスクライブライン領
域9に相当する部分にはn+領域を設けておく。CVD法に
よりAsSG膜7、Si3N4膜6を形成した後、Al金属をスパ
ッタリングして配線電極を形成する工程に入るが、この
Al金属のスパッタリングのマスクに導電膜10形成用の部
分を付加しておく。これにより、Al金属による配線電極
の形成と導電膜10の形成が同時に行える。この実施例に
於いては、この導電膜10の幅は2.6μmである。この
後、プラズマCVD法によりSi3N4膜8が全面に形成され、
スクライブライン領域のSi3N4膜が除去される。第1図
Bで示される導電膜10の間のスクライブライン領域9で
スクライブが行われ、ウェーがチップに分割される。
Based on the cross-sectional view of FIG. 1A and the top view of FIG. 1B,
An embodiment of the semiconductor device of the present invention will be described. A p-well is formed in the n-type Si substrate 1 by the usual manufacturing method to form a peripheral CMOS.
Then, a semiconductor device in which the memory unit is a high resistance SRAM is formed. At this time, an n + region is provided in a portion corresponding to the scribe line region 9 in the n-type Si substrate 1. After the AsSG film 7 and the Si 3 N 4 film 6 are formed by the CVD method, Al metal is sputtered to form a wiring electrode.
A portion for forming the conductive film 10 is added to an Al metal sputtering mask. As a result, the wiring electrode made of Al metal and the conductive film 10 can be formed at the same time. In this embodiment, the conductive film 10 has a width of 2.6 μm. After that, the Si 3 N 4 film 8 is formed on the entire surface by the plasma CVD method,
The Si 3 N 4 film in the scribe line region is removed. Scribe is performed in the scribe line region 9 between the conductive films 10 shown in FIG. 1B, and the way is divided into chips.

この半導体装置の動作中には、基板1には+5Vのバッ
クバイアスが印加されるので、導電膜10にも+5Vが印加
され、外部からの可動イオン侵入が阻止される。
Since a back bias of +5 V is applied to the substrate 1 during operation of this semiconductor device, +5 V is also applied to the conductive film 10 and mobile ion invasion from the outside is blocked.

〔発明の効果〕〔The invention's effect〕

本発明の構造の半導体装置により、従来の技術では制
御しきれなかった製造プロセス中での高抵抗素子への水
素の侵入、さらに装置の完成後にNa+等の可動イオンが
装置内部に侵入して起こる信頼性の低下等が防止でき
る。
With the semiconductor device having the structure of the present invention, hydrogen invades into the high-resistance element during the manufacturing process that could not be controlled by the conventional technique, and mobile ions such as Na + enter the device after completion of the device. It is possible to prevent a decrease in reliability that occurs.

スクライブライン上に露出したチップ本体の側壁部を
被う様に、配線電極のマスクパターンをわずかに修正す
るのみで、本発明の構造の半導体装置を得る事が出来、
工程上何らの変更も要しない、と言う効果もある。
The semiconductor device having the structure of the present invention can be obtained by slightly modifying the mask pattern of the wiring electrode so as to cover the side wall portion of the chip body exposed on the scribe line.
There is also an effect that no change is required in the process.

しかも、半導体チップの断面を被う導電膜に印加して
いるには半導体基板に印加されている電位であってそれ
とは異なる別の電位ではない。このため、特別な配線等
が不要であって、構成が簡単である。
Moreover, the potential applied to the conductive film covering the cross section of the semiconductor chip is the potential applied to the semiconductor substrate and is not a different potential. Therefore, no special wiring or the like is required, and the structure is simple.

【図面の簡単な説明】[Brief description of drawings]

第1図A、Bは本発明の半導体装置の断面図である。 第2図は従来の半導体装置の断面図である。 1……基板、2……フィールド酸化膜 3、5……SiO2膜、4……多結晶Si膜 6……Si3N4膜、7……AsSG膜 8……プラズマSi3N4膜 9……スクライブライン領域 10……保護膜、11……チップ本体 12……PSG膜、13……Al電極1A and 1B are cross-sectional views of the semiconductor device of the present invention. FIG. 2 is a sectional view of a conventional semiconductor device. 1 ... Substrate, 2 ... Field oxide film 3, 5 ... SiO 2 film, 4 ... Polycrystalline Si film 6 ... Si 3 N 4 film, 7 ... AsSG film 8 ... Plasma Si 3 N 4 film 9 …… Scribe line area 10 …… Protective film, 11 …… Chip body 12 …… PSG film, 13 …… Al electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体チップを分割するスクライブ領域に
半導体基板と同一導電型の導電領域が形成されており、 上記スクライブ領域に臨む上記半導体チップの断面を覆
うと共に上記導電領域に接触している導電膜が形成され
ており、 上記半導体基板に印加されている電位が上記導電領域を
介して上記導電膜にも印加されている半導体装置。
1. A conductive region having the same conductivity type as that of a semiconductor substrate is formed in a scribe region dividing a semiconductor chip, and a conductive region that covers a cross section of the semiconductor chip facing the scribe region and is in contact with the conductive region. A semiconductor device in which a film is formed, and the potential applied to the semiconductor substrate is also applied to the conductive film via the conductive region.
JP61276300A 1986-11-19 1986-11-19 Semiconductor device Expired - Fee Related JPH0828360B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61276300A JPH0828360B2 (en) 1986-11-19 1986-11-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61276300A JPH0828360B2 (en) 1986-11-19 1986-11-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS63128733A JPS63128733A (en) 1988-06-01
JPH0828360B2 true JPH0828360B2 (en) 1996-03-21

Family

ID=17567527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61276300A Expired - Fee Related JPH0828360B2 (en) 1986-11-19 1986-11-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0828360B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814887A (en) * 1996-01-26 1998-09-29 Nippon Steel Corporation Semiconductor device and production method thereof
DE69942994D1 (en) * 1999-01-15 2011-01-13 St Microelectronics Srl Barrier structure for peripherals of integrated circuits
CN113451474B (en) * 2020-08-11 2022-04-19 重庆康佳光电技术研究院有限公司 LED chip and preparation method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780719A (en) * 1980-11-07 1982-05-20 Fujitsu Ltd Semiconductor device
JPS5790962A (en) * 1980-11-27 1982-06-05 Oki Electric Ind Co Ltd Semiconductor device
JPS5980936A (en) * 1983-08-31 1984-05-10 Hitachi Ltd Electronic parts

Also Published As

Publication number Publication date
JPS63128733A (en) 1988-06-01

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