JPH0828289B2 - Chip varistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a chip varistor functioning as a voltage non-linear resistance, and in particular, it is possible to reduce electrostatic capacitance while improving surge withstand capability, and consequently to reduce manufacturing cost. At the same time, it relates to a structure that can be adopted for a high-frequency signal line.

[Conventional technology]

Generally, a varistor is a resistor element whose resistance value changes non-linearly according to an applied voltage, and is used as a surge absorbing element for preventing an abnormal voltage from being applied.
In addition, as electronic components have been made into chips in recent years,
A chip type varistor has also been proposed as the varistor. As an example of such a chip varistor, conventionally,
There is a laminated varistor as shown in Fig. 5 (Japanese Patent Publication Sho 58-
(See Japanese Patent No. 23921). This laminated varistor 10 alternately laminates ceramic layers 11 and internal electrodes 12 and integrally sinters them, and forms connection electrodes 14 as external terminals on both end faces 13a, 13b of the sintered body 13. Further, the connection electrodes 14 and the internal electrodes 12 alternately exposed on both end faces 13a and 13b of the sintered body 13 are formed.
And one end surface 12a thereof are connected to each other.

The laminated varistor 10 is naturally required to have better characteristics, for example, lower voltage of V _{1 mA} or improvement of surge withstand capability. This reduction in voltage can be realized by making the thickness of the ceramic layer 11 as thin as possible. Further, the improvement of the surge resistance can be realized by increasing the number of laminated layers of the ceramic layer 11 and the internal electrode 12.For example, in order to obtain the surge withstanding capacity of 50 to 100 A, the internal electrode 12 should be laminated in 10 to 20 layers. ing.

[Problems to be solved by the invention]

However, the above conventional laminated varistor has the following problems.

I. Since the internal electrodes must withstand high temperatures during firing, noble metals such as Ag and Pd are used, and thus the cost increases as the number of laminated layers increases. By the way, most of the manufacturing cost of the laminated varistor is occupied by the precious metal.

II. Also, as the number of stacked layers increases, the capacitance increases, so that it can be used for a 200 V power supply line, for example, but it cannot be used for a high frequency signal line, and its application is limited.

III. Further, in the above-mentioned conventional laminated varistor, the thickness of each ceramic layer is set to be small in order to obtain a low varistor voltage, and therefore the distance between the internal electrodes is very narrow. Moreover, since the ceramics layer portion that develops this voltage non-linearity is located inside the sintered body, the supply of oxygen to the ceramics layer becomes insufficient during firing, especially during the temperature decrease process, resulting in a dense firing. It is difficult to get a union. As a result, improvement in surge withstand is hindered and 100A
The degree is limited. Furthermore, since the ceramics layer portion is disposed inside the sintered body, it is difficult to dissipate heat when a current flows and heat is generated, which also impedes improvement of surge withstand capability.

The present invention has been made to solve the above-mentioned conventional problems, and it is possible to reduce the electrostatic capacitance while improving the surge withstand capability, can be used for high-frequency signal lines, and can reduce the manufacturing cost. It is intended to provide a chip varistor having a structure.

[Means for solving problems]

Therefore, the invention of the first aspect of the present application, a ceramics sintered body having varistor characteristics, and a two-layer internal electrode embedded in the sintered body, a part of an end of which is led to a side surface of the sintered body, A first external electrode electrically connected to the internal electrode and a second external electrode formed on the surface of the sintered body so as to face the internal electrode are provided, and the internal electrode and the second external electrode are provided. It is characterized in that the thickness of the ceramics layer between the external electrodes is set smaller than the thickness of the ceramics layer between the internal electrodes.

In the invention of the second aspect, the ceramics sintered body is Zn
It is characterized by containing O as a main component and at least BiF ₃ as an additive.

[Action]

According to the chip varistor of the present invention, two layers of internal electrodes are formed in the ceramics sintered body, and the external electrodes forming a pair with the internal electrodes are formed on the outer surface of the sintered body. The ceramic layer sandwiching the electrodes and exhibiting the voltage non-linear characteristic is located on the surface portion of the sintered body. As a result, oxygen can be sufficiently supplied in the firing step, the conventional oxygen deficiency can be eliminated, and the surge resistance can be improved accordingly. In addition, since the ceramics layer serves as the surface portion, heat is easily dissipated even if heat is generated due to the application of current, and the surge withstand capability can be improved also from this point. Therefore, it is possible to obtain a value higher than the surge withstand capability, which was obtained by laminating a large number of internal electrodes as in the past, with four layers of the internal electrode and the external electrode, and as a result, the amount of expensive precious metal used can be reduced to 2 / 5 to 1/5, and the manufacturing cost can be reduced accordingly. Further, since the above-mentioned ceramic layer may be two layers, the capacitance can be reduced accordingly, and it can be used for a high frequency signal line.

In addition, the mechanical strength of this chip varistor can be increased, and cracks and chips during surface mounting can be prevented. Furthermore, in the second aspect of the invention, B is added to the main component ZnO.
Since iF ₃ is added, surge withstand capability can be further improved.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 are diagrams for explaining a process of forming the present invention, and FIG. 4 is a diagram for explaining a chip varistor according to an embodiment of the present invention.

1 to 3, reference numeral 1 is a chip varistor in the course of establishment of the present invention. That is principally ZnO, this inside a rectangular parallelepiped ceramic sintered body 2 comprising a BiF _3, buried internal electrodes 3 made of Ag-Pd alloy only one layer, the sintered body 2 The external electrode 4 facing the internal electrode 3 is formed on the outer surface. Further, one end surface 3a of the internal electrode 3 is exposed at the one end surface 2a of the sintered body 2, and the remaining portion is enclosed in the sintered body 2. The one end surface 4a of the external electrode 4 is the other end surface of the sintered body 2.
It is located at the upper edge of 2b, and the other peripheral edge is located inside the peripheral edge of the sintered body 2 when seen in a plan view. Further, connection electrodes 6 are formed on both end surfaces 2a, 2b of the sintered body 2,
One end surface 2a of the internal electrode 3 and one end surface 4a of the external electrode 4 are connected to each of the connection electrodes 6.

Internal electrode 3 and external electrode 4 of the ceramics sintered body 2
A portion sandwiched between and is a first ceramics layer 5a that exhibits a voltage non-linear characteristic, and the ceramics layer 5a is set to have a thickness capable of obtaining a predetermined varistor voltage. Also,
The portion of the sintered body 2 other than the first ceramic layer 5a is
It is the second ceramic layer 5b as a dummy. The ceramic layer 5a that exhibits the above-mentioned voltage non-linearity is set to be extremely thin so as to obtain a predetermined varistor voltage. Therefore, if it is left as it is, it becomes difficult to form the connection electrode and it is easily damaged by an external force. Therefore, the ceramic layer 5b as the dummy is sufficiently thicker than the ceramic layer 5a, in order to secure an end area capable of forming connection electrodes as external connection terminals on both end faces of this sintered body, and to secure strength against external force. It is necessary, and this enables chipping. The outer surface of the sintered body 2 excluding the connection electrode 6 is covered with a glaze 7 made of zinc borosilicate, and the glaze 7 covers the external electrode 4.

Next, a method of manufacturing the chip varistor 1 in the above establishment process will be described.

First, ZnO (97.9mol%), CoO (0.5m
ol%), MnO (0.5mol%), Sb ₂ O ₃ (0.5mol%), Bi ₂ O ₃ (0.
5 mol%) and BiF ₃ (0.1 mol%) are weighed in predetermined proportions and mixed. Distilled water was added to the mixed ceramic raw material and mixed in a ball mill for 24 hours, after which the distilled water was filtered, dried, and then calcined at 800 ° C for 2 hours.
Next, this temporary sintered body is crushed. Here, this calcination-pulverization may be repeated a plurality of times, whereby each raw material powder can be uniformly mixed and the surge resistance can be improved.

Next, the above powder is dispersed in an alcohol solution together with a polyvinyl butyral resin to obtain a slurry. A green sheet having a predetermined thickness is formed from this slurry by a doctor blade method, and the green sheet is cut into a rectangular shape having a predetermined size to form a large number of ceramic layers. As a result, the first ceramics layer 5a exhibiting voltage nonlinearity and the second ceramics layer 5b as a dummy are formed.

Next, as shown in FIG. 3, the first ceramic layer is formed.
The external electrode 4 is formed by printing a paste made of an Ag-Pd alloy on the upper surface of 5a. In this case, one end surface 4a of the external electrode 4
Is formed so that it is located at the end edge of the ceramics layer 5a and the other end surface is located inside the ceramics layer 5a. Then, the above-mentioned paste is printed on the upper surface of one second ceramic layer 5b to form the internal electrodes 3. Also in this case, one end surface of the internal electrode 3
3a is formed so as to be located at the end edge of the ceramics layer 5b and the other peripheral edge is located inside the ceramics layer 5b. And
The outer electrode 4 of the first ceramics layer 5a and the inner electrode 3 of the second ceramics layer face each other with the ceramics layer 5a sandwiched therebetween, and the one end faces 3a, 4a of the respective electrodes 3, 4 have ceramics layers 5b, 5a.
The two second ceramic layers 5b are stacked one on top of the other so that they are alternately positioned at the edges of the two, and these are pressed by a press to form a laminate. Then, as a result, one end surface of the internal electrode 3
Only 3a is exposed on the end face of the laminate, the remaining part is completely embedded in the laminate, and the external electrode 4 is exposed on the upper surface of the laminate.

Next, the laminated body is heated and fired at 950 ° C. for 2 hours to obtain a sintered body 2. In this firing step, oxygen is supplied to the first ceramics layer 5a, so that a ceramics layer free from oxygen defects can be obtained. And both end surfaces 2a, 2 of the sintered body 2
A glaze 7 made of zinc borosilicate is applied to the outer surface excluding b and baked.

Finally, both ends 2a, 2b of the sintered body 2 are coated with Ag paste and then baked, and the surfaces of the Ag paste are coated with a Ni film and then a Sn film by electrolytic plating to form the connection electrodes 6. . As a result, the chip varistor 1 is manufactured.

Next, the function and effect of the chip varistor 1 will be described.

According to the chip varistor 1, the ceramic sintered body 2
Since the internal electrode 3 is embedded in the inside and the external electrode 4 facing the internal electrode 3 is formed on the outer surface of the sintered body 2, both electrodes 3, 4
Since the first ceramics layer 5a sandwiched by is located on the surface portion of the sintered body 2, sufficient oxygen can be supplied to the ceramics layer 5a at the time of firing in the manufacturing process described above, and as a result, surge withstand capability can be increased. Moreover, since the ceramics layer 5a is located on the surface portion, it becomes easy to dissipate heat when a current flows to generate heat, and the surge withstand capability can be improved also from this point. As a result, the internal electrode 3 and the external electrode 4 are
Since it requires only two layers, the amount of expensive precious metal used is
It can be reduced to about 5 to 1/10, and the manufacturing cost can be reduced accordingly. In addition, since the number of layers can be increased, the electrostatic capacity can be reduced accordingly, and it can be used for a high frequency signal line, and the application can be expanded.

Further, by providing the second ceramics layer 5b while setting the first ceramics layer 5a to an extremely thin thickness necessary for lowering the varistor voltage, the area required for forming the connection electrode 6 or the mechanical It is possible to secure the desired strength, support chip formation, and make the overall thickness thinner than the conventional structure, which contributes to the reduction in the thickness of component elements.

Furthermore, since the surface of the external electrode 4 is covered with the glaze 7, the deterioration of the external electrode 6 due to humidity can be prevented, and the electrolytic plating process when forming the connection electrode 6 can be facilitated.

Next, the result of the characteristic test conducted to confirm the effect of the chip varistor 1 will be described.

In this test, the varistor voltage, the non-linear coefficient, the electrostatic capacitance, and the surge withstand capability were measured for the example samples prepared by the above-described manufacturing method. The surge resistance was measured by applying an impact current of 8/20 μs twice at intervals of 5 minutes and measuring the limit current value at which the varistor voltage did not change by 10% or more. Further, for comparison, the same measurement was performed on a commercially available laminated varistor (structure of FIG. 5) in which 16 internal electrodes were laminated. Further, as shown in FIG. 6, a chip varistor in which a pair of internal electrodes 16 and 16 were embedded inside a sintered body 15 was prepared, and the same measurement was performed.

The table shows the results. As is clear from the table, in the case of the conventional sample (column 3), V _1mA can be lowered to 12.1V, but the nonlinear coefficient α is as low as 25 and the capacitance C is 15
It is as high as 00pF and has a surge resistance of about 100A. In the case of the comparative sample (column 2), V _1mA , α, and C have good results of 12.6V, 34, and 110pF, respectively,
The surge resistance is 70A, which is a large drop. It is considered that this is because the number of laminated layers of the ceramics layer and the internal electrode was small, and the ceramics layer was located inside the sintered body, so that it was lower than the conventional sample. On the other hand, in the case of the above varistor 1 (column 1), V _1mA is 12.5V, α is
It is 32, which is a satisfactory value. And C
Is 110pF, which is less than 1/10 of the conventional sample, and the surge withstand capability is 110A, which is about 1.5 times that of the comparative sample and 10% that of the conventional sample.
It is increasing, and it can be seen that all have excellent characteristics.

FIG. 4 shows a chip varistor according to an embodiment of the present invention. In the process of establishing the above invention, one layer of the internal electrode 3 was embedded in the sintered body 2, but the chip varistor 20 of the present invention, as shown in FIG. ,twenty two
And the upper surface of the sintered body 21 facing each internal electrode 22
The external electrodes 23, 23 are formed on the lower surface 21a and the lower surface 21b. In this case, the ceramic layers 24, 24 between the internal electrode 22 and the external electrode 23 are formed thinner than the ceramic layer 5b between the internal electrodes 22, 22. In this way, each internal electrode
First ceramic layer 2 sandwiched by 22 and each external electrode 23
Since 4,24 is molded in two places, surge resistance can be improved compared to the above one. Also, the above-mentioned ceramic layers 24, 24
Are both located on the surface portion of the sintered body 21, so that sufficient oxygen is supplied to the ceramic layers 24, 24 during sintering, and the surge resistance can be further improved.

〔The invention's effect〕

As described above, according to the chip varistor of the present invention,
Two layers of internal electrodes are embedded inside the ceramics sintered body, and a second external electrode facing the internal electrode is formed on the outer surface of the sintered body, thereby forming the internal electrode and the second external electrode. Since the thickness of the ceramics layer between the inner electrodes is thinner than the thickness of the ceramics layer between the internal electrodes, surge withstand capability can be improved and electrostatic capacitance can be reduced, which has the effect of enabling use in high-frequency signal lines. Moreover, there is an effect that the manufacturing cost can be reduced because the number of internal electrodes is small.

[Brief description of drawings]

FIGS. 1 to 3 are views for explaining a chip varistor according to the formation process of the present invention, and FIG. 1 shows I of FIG.
-I line sectional view, FIG. 2 is a perspective view thereof, FIG. 3 is an exploded perspective view thereof, FIG. 4 is a sectional view showing a first embodiment of the present invention, and FIG. 5 shows a conventional laminated varistor. FIG. 6 is a sectional view showing a comparative sample used in the characteristic test of the above-mentioned embodiment. In the figure, 1 and 20 are chip varistors, 2 and 21 are ceramics sintered bodies, 3 and 22 are internal electrodes, and 4 and 23 are external electrodes.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akiyoshi Nakayama 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Stock Company Murata Manufacturing Co., Ltd. (72) Inventor Yasunobu Yoneda 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Murata Manufacturing Co., Ltd. (56) Reference JP 63-99519 (JP, A) JP 63-301502 (JP, A) JP 60-144903 (JP, A)

Claims (2)

[Claims] 1. A ceramics sintered body having varistor characteristics, a two-layer internal electrode embedded in the sintered body, a part of an end of which is led to a side surface of the sintered body, and the internal electrode. A first external electrode electrically connected to the first external electrode; and a second external electrode formed on the surface of the sintered body so as to face the internal electrode. A chip varistor characterized in that the thickness of the ceramic layer between them is set smaller than the thickness of the ceramic layer between the internal electrodes. 2. The chip varistor according to claim 1, wherein the ceramics sintered body contains ZnO as a main component and at least BiF ₃ as an additive.