JPH08279607A - Manufacture of charge coupled element - Google Patents

Abstract

PURPOSE: To provide a two-electrode/two phase drive CCD which is driven at low voltage without deterioration in transfer efficiency by suppressing the cavity of electric potential between a transfer region and an electrode. CONSTITUTION: After a P-type well 2, an N-type buried channel layer 3, an insulating film 4 and the first electrode 6 have been formed on an N-type semiconductor substrate 1, P-type impurities are implanted in a self-matching manner using the first electrode 6 as a mask, and an N-type potential barrier layer 8 is formed. Then, after a conductive film 19 has been deposited on the first electrode 6 and the insulating film 4, a conductive side wall 20 is provided on the side face of the first electrode 6 by conducting anisotropic etching. Besides, after an insulating film 9 has been formed by thermally oxidizing the upper surface of the first electrode and the side wall 20, the second electrode is formed on the insulating film 9. By providing the conductive side wall 20 as above-mentioned, the position 13 on the side face of the first electrode is not almost moved back even when the insulating film 9 is formed by thermally oxidizing the first electrode 6, and as the position 13 can be coincided with the position 14 located at the end of the implantation region of the P-type impurities, the cavity of electric potential between the electrodes of transfer region can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge coupled device (charge coupled device, hereinafter abbreviated as CCD) used for a solid-state image pickup device, a memory device, and the like, and more specifically, a two-layer electrode two-phase drive CCD Manufacturing method.

[0002]

2. Description of the Related Art Recently, the number of pixels of a solid-state image pickup device has been greatly increased, and high-speed driving has been greatly advanced.
In CD, it is necessary to reduce the driving voltage and improve the transfer efficiency.

FIG. 4 is a view for explaining a method of manufacturing a conventional two-layer electrode two-phase driving CCD, which is a sectional view taken along the transfer direction of the CCD. Hereinafter, a case where the semiconductor substrate is N type, the well is P type, and the buried channel layer is N type will be described. In the conventional manufacturing process, for example, by introducing P-type impurities and N-type impurities into the N-type semiconductor substrate 1,
A P-type well 2 and an N-type buried channel layer 3 are formed, and an insulating film 4 such as a thermal oxide film or a film (ONO film) having a three-layer structure of an oxide film-nitride film-oxide film is formed on the surface. Then, an electrode layer 5 made of polycrystalline silicon or the like is formed on the insulating film 4 by the CVD method or the like (FIG. 4A). Next, the electrode layer 5 is patterned to form the first electrode 6 (FIG. 4).
(B)). Subsequently, using the first electrode 6 as a mask, a P-type impurity 7 such as boron ion is introduced by an ion implantation method or the like to form an N ⁻ -type potential barrier layer 8 in the N-type buried channel layer 3. (FIG. 4 (c)). Then, the first electrode 6
Is thermally oxidized to form an insulating film 9, and an electrode layer 10 of polycrystalline silicon or the like is formed on the insulating film 4 and the insulating film 9 by, for example, a CVD method (FIG. 4D). Finally, the electrode layer 10 is patterned and the second electrode 11 is formed so as to cover the gap between the first electrodes 6 (FIG. 4E).

By the above manufacturing process, the first electrode 6 and the second electrode 11 are alternately arranged, and the two layers having the charge storage region 24 under the first electrode 6 and the potential barrier region 25 under the second electrode 11 are formed. A two-phase electrode driven CCD is completed.

FIG. 5 is a schematic potential distribution diagram for explaining the principle of charge transfer in the formed CCD.
As shown in FIG. 5A, V _L and V _H are connected to the two signal lines.
Signal potential 12 is applied to the charge accumulation region 24 under the first electrode 6 to which the voltage V _H is applied.
Is accumulated in From that state, the voltage V _{L of the} two signal lines
When V _H and V _H are exchanged with each other, as shown in FIG. 5B, the high potential portion inside the N-type buried channel layer moves, and the signal charge 12 is also transferred accordingly. Hereinafter, similarly, by repeatedly exchanging the voltages V _L and V _H of the two signal lines, the signal charges 12 can be transferred one after another.

[0006]

However, the conventional method 2
In the layer electrode two-phase driving CCD, the first electrode 6 and the second electrode 11 are used especially when the signal charge is to be transferred with a low driving voltage.
There is a problem in that a potential dent (also referred to as a dip or a pocket) is likely to occur immediately below the insulating film between them, and it is difficult to completely transfer a signal at a low driving voltage.

FIG. 6 is a diagram for explaining the problems of the conventional manufacturing method, and is a sectional view and a schematic potential distribution diagram in the vicinity of the N ^-- type potential barrier layer 8. In the conventional manufacturing process, P-type impurities 7 such as boron ions are implanted in a self-aligned manner by using the first electrode 6 as a mask (see FIG. 6).
(A)). Next, the first electrode 6 is thermally oxidized to form the insulating film 9 with a thickness of about 0.2 μm. At this time, the position 13 on the side surface of the first electrode recedes due to thermal oxidation, and the electrode length of the first electrode 6 is short. (Fig. 6 (b)). Then, the second electrode 11 is formed so as to cover the gap between the first electrodes 6 (see FIG. 6).
(C)). In the CCD formed by such a manufacturing process, the position 13 on the side surface of the first electrode is separated from the position 14 at the end of the P-type impurity implantation region.
Immediately below the insulating film between the electrodes 11, the potential depression 15 is likely to occur (FIG. 6D). In particular, when the insulating film 4 below the first electrode 6 and the second electrode 11 is formed of an ONO film, the position 13 of the electrode side surface when the first electrode 6 is thermally oxidized
Retreat by an amount approximately equal to the film thickness of the insulating film 9 due to thermal oxidation, so that the position 14 at the end of the P-type impurity implantation region substantially coincides with the position 16 on the side surface of the second electrode (FIG. 6 (c)).

FIG. 7 shows a CC formed by a conventional manufacturing method.
For D, P-type impurities 7 that are used in the normal manufacturing process
A simulation was performed in consideration of diffusion due to a typical heat treatment after implantation of (here, boron), and the potential distribution formed inside the N-type buried channel layer was investigated by using the implantation amount of boron ions as a parameter. is there. In FIG. 7, the distance between the first electrode 6 and the second electrode 11 is 0.2 μm, and the position 14 at the end of the boron ion implantation region coincides with the position 16 on the side surface of the second electrode for the simulation. . When the boron ion implantation amount is small, a potential depression 17 is generated between the charge accumulation region 24 and the potential barrier region 25 under the electrode to which V _L is applied. On the other hand, when the boron ion implantation amount increases, the potential dent 17 disappears,
This time, the charge storage region 24 under the electrode to which V _L is applied
Then, a potential depression 18 is generated between the potential barrier regions 25 below the electrodes to which V _H is applied. When the potential dents 17 and 18 are formed in the charge transfer path, part of the signal charge is left in the dents, and the transfer efficiency deteriorates. In order to avoid this, it is necessary to determine the boron ion implantation amount under the condition that the potential depressions 17 and 18 do not occur. V
_{When L} = 0 V and V _H = 5 V, both of the potential pits 17 and 18 are generated when the boron ion implantation amount is in the range of 5 × 10 ¹¹ cm ⁻² to 1 × 10 ¹² cm ^−2. Therefore, it is possible to prevent the transfer efficiency from deteriorating (FIG. 7A).
In the case of V _L = 0V and V _H = 3V, when the boron ion implantation amount is 5 × 10 ¹¹ cm ⁻² , the potential depressions 17 and 1 are generated.
8 did not occur, but when the boron ion implantation amount fluctuated due to process variations, the potential depressions 17 and 1
8 may occur and the transfer efficiency may deteriorate (FIG. 7B). In the case of V _L = 0V and V _H = 2V, one or both of the potential pits 17 and 18 are always generated and the transfer efficiency is deteriorated regardless of the boron ion implantation amount (see FIG. 7 ( c)).

As described above, in the CCD formed by the conventional manufacturing method, when the driving voltage is 3 V or more, the first electrode 6 and the second electrode 11 are appropriately determined by appropriately determining the ion implantation amount of the P-type impurity 7. Since the potential depressions 17 and 18 do not occur immediately below the insulating film between the two, it is possible to prevent the transfer efficiency from deteriorating. However, when the drive voltage is lower than 3V, the potential dents 17 and 18 are generated regardless of the implantation amount of the P-type impurity 7, so that there is a problem that complete charge transfer cannot be performed. .

An object of the present invention is to provide a method of manufacturing a charge-coupled device which can solve the above-mentioned conventional problems and prevent deterioration of transfer efficiency even at a low driving voltage.

[0011]

According to the present invention, a first conductivity type buried channel layer is formed on a second conductivity type well or a second conductivity type semiconductor substrate provided on a first conductivity type semiconductor substrate. Then, an insulating film is formed on the first conductivity type buried channel layer, first electrodes arranged in stripes are formed on the insulating film, and the first electrodes are used as a mask in a self-aligned manner. After implanting a second conductivity type impurity to form a sidewall on the side surface of the first electrode and insulating the first electrode and, if necessary, the sidewall by thermal oxidation, A method for manufacturing a charge-coupled device, comprising forming a second electrode in the gap.

[0012]

The reason why the potential depressions 17 and 18 are likely to occur immediately below the insulating film between the first electrode 6 and the second electrode 11 can be explained as follows. That is, P-type impurities 7 such as boron ions are ion-implanted in a self-aligned manner using the first electrode 6 as a mask to form the N ⁻ type potential barrier layer 8. However, after that, the first electrode 6 is thermally oxidized and the electrode length is shortened, so that the position 13 on the side surface of the first electrode is separated from the position 14 at the end of the P-type impurity implantation region. As a result, the P-type impurities existing inside the N-type buried channel layer immediately below the insulating film between the first electrode 6 and the second electrode 11 are only the P-type impurities diffused by the heat treatment after the ion implantation. Since it is not present, a dent in the potential is likely to occur.

In the present invention, the first electrode 6 is formed,
The P-type impurity 7 is ion-implanted in a self-aligning manner using the first electrode 6 as a mask, and then the conductive side wall 2 is formed on the first electrode 6.
0 or an insulating side wall 22 is formed. Thus the first
By providing the conductive side wall 20 or the insulating side wall 22 on the electrode 6, only the conductive side wall 20 and the upper surface of the first electrode are heated when the side wall is conductive in the subsequent thermal oxidation step. When the side wall is oxidized and the side wall is insulative, only the upper surface of the first electrode is thermally oxidized, and therefore the position 13 of the side surface of the first electrode does not recede. Therefore, the position 13 of the side surface of the first electrode and the position 14 of the end of the P-type impurity implantation region after the completion of thermal oxidation are substantially aligned with each other, and the N-type buried portion immediately below the insulating film between the first electrode 6 and the second electrode 11 is formed. Since the N ⁻ -type potential barrier layer 8 is formed so that the P-type impurities are sufficiently present also inside the channel layer, the potential depressions 17 and 18 are less likely to occur, and the deterioration of the transfer efficiency can be prevented.

[0014]

【Example】

(Embodiment 1) FIGS. 1A to 1E are sectional views showing an embodiment of the present invention. FIG. 1 (a) corresponds to FIG. 4 (c) in the conventional manufacturing method, and the manufacturing method up to that point is the same as the conventional manufacturing method, and therefore the description thereof is omitted here. However, the first electrode 6 of FIG. 1A is formed in consideration of the fact that the conductive side wall 20 is provided on the side surface in a later step, and thus the first electrode 6 of FIG.
The electrode length is shorter than that of the first electrode 6. First
After forming the electrode 6 and the N ⁻ type potential barrier layer 8, a conductive film 19 such as polycrystalline silicon is formed on the first electrode 6 and the insulating film 4 by, for example, the CVD method (FIG. 1).
(B)). The film thickness of the conductive film 19 varies depending on the film thickness of the insulating film 9 to be formed between the first electrode 6 and the second electrode 11. For example, the insulating film 4 is formed of an ONO film. When the film thickness of 9 is 0.2 μm, the conductive film 19 has a film thickness of about 0.2 μm. Further, the conductive film 19 is anisotropically etched to form a conductive side wall 20 on the side surface of the first electrode 6 (FIG. 1C). Here, the conductive side wall 20 is electrically connected to the first electrode 6. After that, the upper surface of the first electrode and the conductive side wall 20 are thermally oxidized to form the insulating film 9, and the electrode layer 10 of polycrystalline silicon or the like is formed on the insulating film 4 and the insulating film 9 by, for example, the CVD method. Formed (FIG. 1D). Finally, the electrode layer 10 is patterned to form the second electrode 11 that covers the gap between the first electrodes (FIG. 1E). In the CCD formed by the above steps, when the insulating film 9 between the first electrode 6 and the second electrode 11 is formed, the position 13 of the first electrode side surface does not recede due to thermal oxidation, so the first electrode side surface Position 13 and position 14 at the end of the P-type impurity implantation region coincide with each other.

The CCD formed by the above steps is
In addition, P-type impurities (here,
Considering diffusion due to typical heat treatment after boron implantation
To simulate inside the N-type buried channel layer.
The potential distribution that is formed is determined by the boron ion implantation amount.
I investigated as a data. The result is shown in FIG. In Figure 2,
The distance between the first electrode 6 and the second electrode 11 is 0.2 μm,
The position 14 at the end of the implantation region of the long ions is on the side surface of the first electrode.
Perform a simulation with the position 13 matched
There is. When the boron ion implantation amount is small, the potential dips
17 occurs, and when the injection amount increases, the potential depression 18 is generated.
The tendency to grow is that CC formed by conventional manufacturing methods
Same as D. But N^-Forming a mold potential barrier layer 8
The position 14 of the implanted region of boron is the side surface of the first electrode.
By extending to position 13, the depressions 17 and 1 of the potential
It can be seen that the occurrence of No. 8 is suppressed. V_L= 0, V
_H = 5V, the boron ion implantation amount is 3 × 10
¹¹cm^-2~ 1.2 x 10¹²cm^-2In the range of 17
Neither and 18 occur (FIG. 2 (a)). V_L=
0, V_H= 3 V, the boron ion implantation amount is 3
× 10¹¹cm^-2~ 8 × 10¹¹cm^-2In the range of 1
Neither 7 nor 18 occurs (FIG. 2 (b)). V_L
= 0V, V_H= 2V, the boron ion
Injection volume is 3 × 10¹¹cm^-2~ 5 × 10¹¹cm^-2In the range of
Neither of the indentations 17 and 18 occurs.

From the above simulation results, according to the manufacturing method of the above embodiment, even if the driving voltage of the CCD is 3 V or less, the potential depressions 17 and 18 are formed in the charge transfer path.
Since it is possible to suppress the occurrence of the above, it is possible to prevent the deterioration of the transfer efficiency even at a low driving voltage. Further, when driven by the same voltage, the electric field that contributes to the charge transfer becomes stronger than the CCD formed by the conventional manufacturing method, and the charge transfer can be performed in a short time. It becomes possible to drive. Further, according to the manufacturing method of the above-described embodiment, the allowable range of the implantation amount of the P-type impurity 7 in which the potential pits 17 and 18 are not generated is wider than that in the conventional manufacturing method, so that the P-type impurity 7 is not included due to process variations. Even if the injection amount of the
The effect that 8 is less likely to occur is obtained.

(Embodiment 2) FIGS. 3A to 3E are sectional views showing a second embodiment of the present invention. Figure 3 (a) shows
This corresponds to FIG. 4C in the conventional manufacturing method, and the manufacturing method up to that point is the same as the conventional manufacturing method, and therefore description thereof is omitted here. However, the first electrode 6 of FIG. 3A is formed to have a shorter electrode length than that of the first electrode 6 of FIG. 4C in consideration of providing an insulating side wall 22 on the side surface in a later step. ing. After the first electrode 6 is formed and the N ⁻ type potential barrier layer 8 is formed, for example, C is formed on the first electrode 6 and the insulating film 4.
An insulating film 21 such as an oxide film or a nitride film is formed by the VD method or the like (FIG. 3B). The film thickness of the insulating film 21 varies depending on the distance between the first electrode 6 and the second electrode 11, but the distance is 0.
When the thickness is 2 μm, the insulating film 21 has a thickness of about 0.2 μm. Further, the insulating film 21 is anisotropically etched to form an insulating side wall 22 on the side surface of the first electrode 6 (FIG. 3C). Then, the upper surface of the first electrode 6 is thermally oxidized to form the insulating film 23, and the insulating film 4 and the insulating film 23 are formed.
Further, the electrode layer 10 made of polycrystalline silicon or the like is formed on the insulating side wall 22 by, for example, the CVD method (FIG. 3).
(D)). Finally, the electrode layer 10 is patterned to form the second electrode 11 that covers the gap between the first electrodes (FIG. 3).
(E)). In the CCD formed by the above steps, when the insulating film 23 between the first electrode 6 and the second electrode 11 is formed, the position 13 on the side surface of the first electrode hardly recedes due to thermal oxidation. The position 13 on the side surface and the position 14 at the end of the P-type impurity implantation region coincide.

If the CCD is formed by the manufacturing method of the above-mentioned embodiment, the transfer efficiency can be prevented from being deteriorated even at a low driving voltage, similarly to the case where the CCD is formed by the manufacturing method of the first embodiment, and further the same. When driven by the voltage, the CCD can be driven at high speed. or,
Even if the implantation amount of the P-type impurity 7 fluctuates due to the process variation, the effect that the potential depressions 17 and 18 are less likely to occur can be obtained.

[0019]

As described above in detail, according to the present invention, in the CCD of the two-layer electrode two-phase drive, the first electrode is used as a mask after the P-type impurities are ion-implanted in a self-aligned manner. By using the manufacturing method of forming the conductive or insulating side wall on the electrode, it is possible to suppress the generation of the potential dent in the charge transfer path as compared with the case of using the conventional manufacturing method. . Therefore, according to the present invention, it is possible to drive the CCD at a low voltage without deteriorating the transfer efficiency as compared with the prior art. When driven by the same voltage, C formed by the conventional manufacturing method is used.
The electric field that contributes to the charge transfer becomes stronger than that of the CD, and the charge transfer can be performed in a short time, so that the CCD can be driven at a higher speed.

[Brief description of drawings]

FIG. 1 is a two-layer electrode 2 which is an embodiment of the first invention of the present application.
It is sectional drawing which shows the manufacturing process of phase drive CCD.

FIG. 2 is a diagram showing a relationship between an implantation amount of boron and a potential distribution in a buried channel layer in a two-layer electrode two-phase driving CCD shown in one embodiment of the first invention of the present application.

FIG. 3 is a two-layer electrode 2 which is an embodiment of the second invention of the present application.
It is sectional drawing which shows the manufacturing process of CCD of a phase drive.

FIG. 4 is a cross-sectional view showing a manufacturing process of a conventional two-layer electrode two-phase drive CCD.

FIG. 5 is a schematic potential distribution diagram showing the principle of charge transfer in a two-layer electrode two-phase driving CCD.

FIG. 6 is a cross-sectional view and a schematic potential distribution diagram in the vicinity of a potential barrier region in a conventional two-layer electrode two-phase drive CCD.

FIG. 7 is a diagram showing a relationship between a boron implantation amount and a potential distribution in a buried channel layer in a conventional two-layer electrode two-phase driving CCD.

[Explanation of symbols]

1 N-type semiconductor substrate 2 P-type well 3 N-type buried channel layer 4 insulating film 5 electrode layer 6 first electrode 7 P-type impurity 8 N ^- type potential barrier layer 9 insulating film 10 electrode layer 11 second electrode 12 signal charge 13 Position of first electrode side surface 14 Position of end of P-type impurity implantation region 15 Potential dent 16 Position of second electrode side 17 Potential dent 18 Potential dent 19 Conductive film 20 Conductive sidewall 21 Insulating film 22 Insulating side wall 23 Insulating film 24 Charge storage region 25 Potential barrier region

Claims (1)

[Claims] 1. A second device provided on a first conductivity type semiconductor substrate.
A first conductivity type buried channel layer is formed on a conductivity type well or a second conductivity type semiconductor substrate, an insulating film is formed on the first conductivity type buried channel layer, and stripes are formed on the insulating film. Forming first electrodes arranged in a line, implanting second conductivity type impurities in a self-aligned manner using the first electrodes as a mask, forming sidewalls on the side surfaces of the first electrodes, and performing thermal oxidation. A method of manufacturing a charge-coupled device, comprising: insulating the first electrode and, if necessary, the side wall, and then forming a second electrode in a gap between the first electrodes.