JP3122670B2 - Charge transfer device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device, and more particularly to a structure of an insulating film between gate electrodes and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 13 is a sectional view showing a main part of a conventional charge transfer device disclosed in, for example, JP-A-2-332. In the figure, 1 is a substrate, 2 is an impurity layer, 3 is an insulating film, 4 is a first electrode, 5 is a second electrode which is electrically connected to the first electrode,
6 is a region where no gate electrode is present, and 10 is the first and second regions.
It is a gate electrode composed of an electrode.

A method of manufacturing a conventional charge transfer device as shown in FIG. 13 will be described with reference to FIGS. P
An N ^-- type impurity layer 2 is formed on a silicon substrate 1 by ion implantation, a surface of the substrate 1 is oxidized to form a silicon oxide film 3 as an insulating film, and a first conductive film is formed on the upper surface thereof by a CVD method. Is formed. (FIG. 14)

Next, a resist (not shown) is applied, the resist is patterned through a photomechanical process, and the polysilicon film of the first conductive film is etched using the resist as a mask.
(FIG. 15) Next, a polysilicon film 5 of a second conductive film is formed, and (FIG. 16)
3 is obtained.

The operation of the charge transfer device having the above-described electrode structure will be described with reference to FIGS. FIG. 17 shows a state in which the four-phase clocks φ1 to φ4 are applied to the respective electrodes. Assuming that the four-phase clock shown in FIG. 22 is used, at time t = t ₁ shown in FIG. 22, the transfer charge is transferred below the electrodes to which the φ ₁ and φ ₂ clocks are applied as shown in FIG. Is assumed to exist. (O in the figure indicates the transfer charge.)

Next, at t = t ₂ , as shown in FIG.
Is changed from L to H, a potential well is formed under the electrode to which the clock of φ3 is applied,
The transfer charge spreads below the electrodes to which the clocks of φ ₁ , φ ₂ , and φ ₃ are applied.

Next, at time t = t ₃ , the movement of the transfer charge is shown in FIG. 2 while the clock of φ ₁ is changing from H → L.
Is as shown 0, by phi ₁ clock is changed to H → L, the transfer charge becomes shallow the potential below the electrode where phi ₁ clock is applied phi _2, phi ₃ clock is applied Move under the electrode.

As described above, when the electric charges are transferred under each electrode, below the region 6 where the first electrode 4 and the second electrode 5 do not exist in FIG. A depression く φ of the channel potential occurs. The size of the depression △ φ occurs in proportion to the length Lg of the region 6 where no electrode exists. When the depression △ φ occurs, a part of the charge remains in the depression, and there is a problem that a transfer loss occurs as shown in FIG.

[0009]

Since the conventional charge transfer device is configured as described above, a depression of the channel potential is generated under the region 6 in accordance with the length Lg of the region 6, and the depth of the depression is reduced. Electrons corresponding to Δφ are caught,
There is a problem that transfer efficiency is deteriorated. Length L
Even if g is to be shortened, insulation failure occurs between adjacent electrodes, which naturally has a limit.

The present invention has been made to solve the above problems, and has as its object to provide a charge transfer device having a sufficient transfer efficiency and a manufacturing method suitable for the device.

[0011]

SUMMARY OF THE INVENTION The charge transfer device according to the present invention, provided at predetermined intervals on the insulating film, it
Multiple gates connected to each clock pulse source
Poles, and these gate electrodes are respectively the first electrode and
Is composed of a second electrode formed on an end portion of the first electrode, the insulating film thickness positioned between the first electrode, it is obtained by thinning the insulating film under the first electrode.

Further, in the manufacturing method of the present invention, after the step of forming the first electrode, the insulating film between the first electrodes is etched to a predetermined thickness.

[0013]

According to the present invention, the thickness of the insulating film located between the first electrodes is smaller than that of the insulating film below the first electrode, so that the recess of the channel potential in a region where no electrode exists is small.

Further, in the manufacturing method of the present invention, the insulating film between the first electrodes can be made thinner than that under the first electrode by etching.

[0015]

【Example】

Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a P-type silicon substrate, 2 is an N ⁻ -type impurity layer (channel), 3 is an insulating film (gate insulating film) made of a silicon oxide film, and 4 is a first electrode (gate electrode) made of a polysilicon film. ), 5 is a second electrode (gate electrode) made of a polysilicon film, 6 is a region where no electrode exists, Lg is its length, 7 is the length of the second electrode, and 10 is the gate electrode. Note that d ₁ is below the first electrode, and d ₂ is the region 6
Of the insulating film 3 of FIG.

FIG. 2 is a diagram showing a potential distribution corresponding to the electrode arrangement of FIG.

FIGS. 3 to 5 are diagrams showing potential changes depending on the length Le of the second electrode and the length Lg of the region 6. FIG.

FIGS. 6 to 9 are schematic process diagrams showing an embodiment of the present invention.

In FIG. 1, a first electrode 4 and a second electrode 5 form a gate electrode 10. The insulating film 3 made of a silicon oxide film has a function of gate insulation. The channel is formed in the N ⁻ -type impurity layer 2. As can be seen from the potential diagram shown in FIG. 2, the channel in the region 6 where the gate electrode 10 does not exist is deeper than the other portions.

This can be explained as follows with reference to FIG. In FIG 10, V _G1: potential V _G2 of the left of the gate electrode: the potential of the right of the gate electrode C _G: coupling capacitance C _G of the gate electrode and the channel immediately below the ': region 6 where there is no gate electrode and the gate electrode binding capacity phi ₁ between the channel under: channel potential immediately under the left of the gate electrode phi _2: channel potential phi ₁ immediately below the right of the gate electrode ': under regions 6 channel potential C _B: channel and the substrate 1 It shows the coupling capacitance between them.

In general, the channel is capacitively coupled to the gate electrode 10 and the substrate 1, and the smaller the capacitance, the deeper the potential. Since the coupling capacity is inversely proportional to the distance, the diagonal coupling like C _G ′ shown in FIG. 10 is smaller than the vertical coupling like C _G. The potential dip as shown in FIG. 2 occurs because C _G ′ is small in the above-described coupling capacitance. In order to reduce these dents as much as possible, a configuration in which C _G ′ is increased may be used.

Next, FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG.
The operation of the present invention will be described based on the first aspect. The insulating film thickness under the first electrode 4 is d ₁ , and the insulating film thickness between the first electrodes is d ₂ .
As d ₂ is reduced, the channel potential changes as shown in FIG. That is, as d ₂ is made thinner, the potential below the second electrode 5, that is, below the length 7 of the second electrode 5 becomes shallower, and a barrier is formed from a certain thickness.

The potential under the region 6 is gradually reduced by the potential under the region 7. The potential variation of the regions 6 and 7 as viewed from under the center of the channel of the gate electrode 10 △ and phi, positive as in FIG. 2, the negative decide, by the thickness d ₂ of the insulating film 3 under the second electrode 5 △
φ changes as shown in FIG.

This Δφ varies depending on the length Lg of the region 6 where the gate electrode 10 does not exist. In this regard, FIG.
5 will be described in detail. As the thickness d ₂ of the insulating film 3 is smaller, the channel potential therebelow becomes shallower. However, when the length Le of the second electrode 5 is increased as shown in FIG.
The region immediately below the gate electrode 10 and shallower than the potential φ ₀ becomes longer. The potential dent below the region Lg is lifted by the effect of Le. Therefore, FIG.
It is considered that if φα and φβ are determined as shown in FIG. Here, φα is the amount by which the potential becomes shallower than φ _{0 when} viewed from the left side of FIG. 4, and φβ is Lg
The amount of potential barrier that must be exceeded to move to the right when viewed from the electrons in the lower potential pit. Since electrons have thermal energy, they can cross even a certain potential barrier. When the maximum barrier to be its beyond the phi _b, in FIG. 5, | Fa | a | φβ | if you choose Le so is less than phi _b, left without even somewhat there is unevenness of the potential the electrons remains From right to right.

As described above, in the structure shown in this embodiment, after the thickness d ₂ of the gate insulating film 3 is determined, Le of the length Lg + 2Le occupied by the insulating film d ₂ is determined. As shown in FIG. 5, it has been shown that the potential dent is reduced by setting the value within the allowable range, but Le may be determined first and the optimum value of d ₂ may be selected.

Next, an example of the manufacturing method of the present invention will be described with reference to FIGS.
Will be described. First, an N ^- type impurity layer 2 is formed by implanting N-type impurity ions such as phosphorus into a silicon substrate 1 containing a P-type impurity such as boron. Then by oxidizing the surface of the substrate to form a silicon oxide film 3 of predetermined thickness d _1, depositing a first polysilicon film 4 by the subsequent CVD process.

Next, as shown in FIG. 6, the first polysilicon film 4 is processed into a predetermined pattern through a photomechanical process to form a first electrode 4 and a region 6 where the silicon oxide film 3 is exposed. Create

Next, as shown in FIG. 7, the silicon oxide film 3 in the exposed region 6 is etched to a predetermined thickness d ₂ .
The etching method may be wet etching using hydrofluoric acid or the like or dry etching using plasma. However, since the remaining oxide film 3 is used as it is as a gate insulating film, it is necessary to avoid an etching method that causes damage to lower the oxide film breakdown voltage. Also, a predetermined thickness d
₂ is d ₂ that makes the aforementioned Δφ small.

Next, as shown in FIG. 8, a second polysilicon film 5 is deposited by a CVD method. Since the CVD method has good film coverage, the film thickness is uniform even at the step portion.

Next, as shown in FIG. 9, the deposited second polysilicon film 5 is etched by an anisotropic etching method such as RIE (reactive ion etching) so that the end of the first electrode 4 is etched. Only the second electrode 5 is formed. Through the above steps, the structure shown in FIG. 1 is realized.

Embodiment 2 FIG. In the above embodiment, the polysilicon film is used as the material of the first and second electrodes 4 and 5. However, a high melting point metal such as W silicide or a conductor such as a multilayer film of polysilicon and silicide is appropriately selected. May do it.

Although a silicon oxide film is used as the gate insulating film 3, a silicon nitride film or a multilayer film thereof may be used.

Embodiment 3 FIG. Further, by employing the multilayer gate insulation film structure of the silicon oxide film 3 a silicon nitride film 8 a silicon oxide film 9 as shown in FIG. 12, the film thinning step of the gate insulating film corresponding to FIG. 7 and d ₂ Thickness control becomes easy. The reason is that in the etching of the oxide film, a sufficient etching ratio with respect to the nitride film can be obtained.
Is etched, it becomes easy to finish the etching when the nitride film 8 is exposed, and the insulating film thickness d ₂ can be stably obtained.

Embodiment 4 FIG. In the above embodiment, a P-type silicon substrate is used, but a P-type impurity layer formed on an N-type substrate may be used.

Embodiment 5 FIG. In the above embodiment, the buried channel type charge transfer device having the N-type substrate surface is shown, but a surface channel type charge transfer device having no N-type layer may be used.

[0036]

As described above, according to the present invention, the thickness of the insulating film located between the first electrodes of the gate electrode is smaller than that of the insulating film under the first electrode. And the charge transfer efficiency is improved. In addition, multiple gate electrodes are spaced
, Which reduces parasitic capacitance between gates
Thus, power consumption can be reduced.

According to the manufacturing method of the present invention, the insulating film between the first electrodes can be etched to be thinner than the insulating film under the first electrode.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a charge transfer device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a potential distribution corresponding to FIG.

FIG. 3 is a diagram showing a potential change depending on a second electrode length and an opening region length.

FIG. 4 is a diagram showing a potential change depending on a second electrode length and an opening region length.

FIG. 5 is a diagram showing a potential change according to a second electrode length and an opening region length.

FIG. 6 is a schematic process diagram showing one embodiment of the production method of the present invention.

FIG. 7 is a schematic process chart showing one embodiment of the production method of the present invention.

FIG. 8 is a schematic process chart showing one embodiment of the production method of the present invention.

FIG. 9 is a schematic process chart showing one embodiment of the production method of the present invention.

FIG. 10 is an equivalent circuit of a gate electrode end of the charge transfer device.

FIG. 11 is a diagram showing a relationship between an insulating film thickness below an end of a gate electrode and Δφ.

FIG. 12 is a sectional view showing a third embodiment of the present invention.

FIG. 13 is a sectional view showing a conventional charge transfer device.

FIG. 14 is a schematic process diagram showing a method for manufacturing a conventional charge transfer device.

FIG. 15 is a schematic process diagram showing a method for manufacturing a conventional charge transfer device.

FIG. 16 is a schematic process diagram showing a method for manufacturing a conventional charge transfer device.

FIG. 17 is an explanatory diagram showing the operation of the transfer element.

FIG. 18 is an explanatory diagram showing the operation of the transfer element.

FIG. 19 is an explanatory diagram showing the operation of a transfer element.

FIG. 20 is an explanatory diagram showing the operation of the transfer element.

FIG. 21 is an explanatory diagram showing the operation of a transfer element.

FIG. 22 shows an example of a clock voltage for driving a charge transfer element.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/762 H01L 21/339

Claims (2)

(57) [Claims] Hey and 1. A semiconductor substrate, an insulating film provided on a main surface of the semiconductor substrate, a predetermined distance on the insulating film
Connected to each clock pulse source.
A plurality of gate electrodes, and these gate electrodes
A first electrode and a first electrode formed at an end of the first electrode.
A charge transfer device comprising two electrodes, wherein the insulating film located between the first electrodes is thinner than the insulating film under the first electrode. A step of forming an insulating film and a first conductive film on a semiconductor substrate; a step of etching the conductive film to form a first electrode; and a step of forming an insulating film located between the first electrodes. A step of etching to a predetermined thickness, a step of forming a second conductive film on the first electrode and the insulating film, and anisotropically etching the second conductive film to form a second conductive film on the end of the first electrode. Forming a two-electrode.