JP2749019B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.
Method, especially charge transfer devices such as CCD (charge coupled device) type
The present invention relates to a method for manufacturing a semiconductor device having:

[0002]

2. Description of the Related Art Conventionally, as the above-mentioned charge transfer element, FIG.
4 is known. This element has a P-type impurity layer (P-type well layer) on an N-type silicon substrate 11.
The N-type channel impurity layer (charge transfer channel portion) 13 and the P-type impurity layer 13 are formed on the P-type impurity layer 12.
The mold channel stop portions 16 are formed adjacent to each other, and a gate electrode 15 is further formed thereon with a gate insulating film 14 interposed therebetween.

The charge transfer device is manufactured as follows. First, as shown in FIG. 15, a P-type impurity layer (P-type well layer) 12 is formed on the entire upper surface of an N-type silicon substrate 11, and an alignment reference layer 17 made of, for example, SiO ₂ is further formed thereon. I do. The alignment reference layer 17 has a configuration in which, for example, a mark for positioning is formed at a reference position by a protrusion provided on the upper surface of the P-type impurity layer 12.

Then, as shown in FIG. 16, a resist film 18 is formed by positioning based on the mark, and ions are implanted from a portion where the resist film 18 is not formed to form a charge transfer layer on the P-type well layer 12. An N-type channel impurity layer 13 functioning as a CCD is formed. Next, as shown in FIG. 17, after removing the resist film 18, the resist film 19 is formed by positioning again based on the mark,
P-type channel stop portions 16 are formed by ion implantation from the non-formed portions. Next, as shown in FIG. 18, after removing the resist film 19 and the alignment reference layer 17, a gate insulating film 14 and a gate electrode 15 are formed on the surface of the P-type impurity layer 12 in this order. At this time, a mark is formed on the upper surface of the gate electrode 15 by the above-described protrusion. Thereafter, the resist film 20 is formed on a part of the gate electrode 15 by positioning based on the mark, and the gate electrode 15 is removed by etching or the like while leaving the part under the resist film 20 to obtain a diagram. 14
Are manufactured.

[0005]

Therefore, in the case of the conventional charge transfer element, for example, when forming the channel impurity layer 13 as a charge transfer channel portion and when forming the channel stop portion 16, the mark formed in advance is formed. It is necessary to perform alignment based on each.
That is, in this example, the alignment needs to be performed twice. For this reason, it is necessary to expect a large margin for alignment deviation at the element design stage, and as a result, the width of the channel impurity layer 13 has a large variation, resulting in a large variation in the charge transfer amount.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of the prior art, and a semiconductor device capable of reducing the number of times of alignment and reducing the variation of the charge transfer amount.
An object of the present invention is to provide a method for manufacturing a body device .

[0007]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device , comprising: a first impurity region and a second impurity region;
Of semiconductor device in which object region is formed on semiconductor substrate
In a method, a first silicon oxide film on a semiconductor substrate is provided.
And silicon nitride film and resist pattern of predetermined shape
Are sequentially formed, and the above-described silicon
A step of etching and removing the con-nitride film;
Using the pattern as a mask through the first silicon oxide film
The first impurity region is formed by performing on-implantation.
And thermal oxidation using the silicon nitride film as a mask.
Forming a second silicon oxide film,
Forming a first step on the plate surface;
After exposing the plate surface, a first insulating film is formed on the semiconductor substrate.
Depositing and positioning the first step portion
Reference pattern for forming the second impurity region.
The second impurity region is used as a reference for positioning the mask.
Formed to have a predetermined positional relationship with one impurity region
And a step of performing Also,
The method of manufacturing a semiconductor device according to claim 2, wherein the first impurity
A region where the region and the second impurity region are formed on the semiconductor substrate;
In the method for manufacturing a conductor device, a second semiconductor substrate is provided on the semiconductor substrate.
Insulating film and resist pattern of specified shape are formed sequentially
Then, using the resist pattern as a mask, the substrate surface
Etching the second insulating film so that is not exposed,
Forming a second step in the second insulating film;
With the resist pattern as a mask through the second insulating film
The first impurity region is formed by ion implantation.
And a positioning base comprising the second step portion.
The quasi-pattern is used as a mask for forming the second impurity region.
The second impurity region is defined as a first impurity as a reference for alignment.
Process to form a predetermined positional relationship with the object area
And a step is included. Claims
3. The method for manufacturing a semiconductor device according to item 3,
A semiconductor device having a second impurity region formed on a semiconductor substrate;
In the method of manufacturing a device, a second insulating material is provided on the semiconductor substrate.
A film and a resist pattern of a predetermined shape were sequentially formed.
Thereafter, the substrate surface is exposed using the resist pattern as a mask.
So as not to leave etching the second insulation Enmaku, said
Forming a second step in the second insulating film;
Using the strike pattern as a mask, the ion
To form the first impurity region.
Process and after removing the resist pattern, the semiconductor
Depositing a third insulating film on the body substrate and forming the third insulating film on the second step portion;
Forming a corresponding third step portion;
The difference portion is aligned with the position of the mask for forming the second impurity region.
The second impurity region is defined as a first impurity region
Forming a predetermined positional relationship with respect to
It is characterized by including.

[0008] A semiconductor device according to the present invention as set forth in claim 4 is provided.
The method of manufacturing the device includes:
Channel or channel stop,
The second impurity region is connected to the charge transfer channel or channel.
Characterized in that it is the other of the channel stop portions.
4. The semiconductor device according to claim 1,
It is a manufacturing method of the device.

[0009]

According to the present invention, it is formed on a semiconductor substrate.
A reference pattern is formed simultaneously when forming one of the charge transfer channel portion and the channel stop portion, which is an example of the first impurity region and the second impurity region , and thereafter, based on the reference pattern. Form the other. Therefore, when the charge transfer channel portion and the channel stop portion of the formation may alignment adjustment number once, it can reduce the design margin by the alignment deviation during device design to about 1/2 of the conventional, thereby the charge transfer switch
Variations in the width of the channel can be reduced.

[0010]

Embodiments of the present invention will be described below.

FIG. 1 shows a charge transfer device (part) according to the present invention.
FIG. 4 is a cross-sectional view showing one embodiment of a semiconductor device according to the present invention. This half
In the charge transfer element of the conductor device , a P-type impurity layer (P-type well layer) 22 is formed on an N-type silicon substrate 21. A recess 29 is formed in a part of the upper layer of the P-type impurity layer 22, and a charge transfer C is formed under the recess 29.
An N-type channel impurity layer (charge transfer channel portion) 23 functioning as a CD is formed, and a P-type channel stop portion 26 is provided beside the N-type impurity layer. On the P-type impurity layer 22, a gate insulating film 24 is formed over the entire surface, and further thereon, the N-type channel impurity layer 2 is formed.
The gate electrode 25 is formed in the upper part of the gate electrode 3.

Next, a method of manufacturing the charge transfer device having the above-described structure will be described.

First, as shown in FIG. 2, an N-type silicon substrate 21 is doped with an impurity and then thermally diffused to form a P-type impurity layer 22. Then, on the silicon substrate 21, by the surface layer portion is thermally oxidized, or to form a 100-1000 Angstrom silicon oxide film 27a by CVD, Si ₃ N ₄ except for some further thereon The film 27b is formed. This Si ₃ N ₄ film 27b
Is formed on the entire surface of the silicon oxide film 27a by, for example, a CVD method or a sputtering method to form a resist film 27c with a thickness of 1000 to 5000 angstroms.
Is formed by patterning and etching. Incidentally, instead of the Si ₃ N ₄ film 27b, TiN,
A similar film may be formed using W, Mo, or the like.

Thereafter, as shown in FIG. 3, the exposed portion of the silicon oxide film 27a and the resist film 27c are etched, and a P layer 28a is formed by ion implantation in the P-type impurity layer 22 where the upper surface is bare. I do. Next, as shown in FIG. 4, the P layer 28a is grown by performing thermal oxidation.
Thermal oxide film 2 having a thickness of 100 to 2000 angstroms
8b is obtained. Thereby, the silicon substrate 21 and the thermal oxide film 2
The interface with 8b becomes uneven, and the depression 29 is formed on the upper surface of the silicon substrate 21. The depression 29 is used as a reference pattern for positioning as described later. Thereafter, N ^- ions are implanted to form an N-type channel impurity layer 23 under the thermal oxide film 28b. That is, the channel impurity layer (charge transfer channel portion) 23 is formed without performing alignment with respect to the reference pattern 29, and at the time of its formation, the reference pattern 29 for positioning is formed.

Next, as shown in FIG. 5, a Si ₃ N ₄ film 27 is formed.
b, after removing the silicon oxide film 27a and the thermal oxide film 28b, a gate insulating film 24 is formed over the entire surface of the P-type impurity layer 22, and thereafter, is positioned based on the reference pattern 29 as shown in FIG. Then, a resist pattern 30a for forming a channel stop portion is formed, and P ⁺ ions are implanted by an ion implantation method to form a P-type channel stop portion 26.

Next, as shown in FIG. 7, after removing the resist pattern 30a, a gate electrode 25 is deposited on the entire surface of the gate insulating film 24, and then the resist pattern is positioned based on the reference pattern 29. 30b is formed, and the gate electrode 25 is patterned. Thus, a charge transfer device having the structure shown in FIG. 1 is obtained.

Therefore, in the present invention, when the channel impurity layer (charge transfer channel section) 23 and the channel stop section 26 are formed, only the channel stop section 26 needs to be aligned with the reference pattern 29. . Therefore, the number of times of alignment may be one, and the design margin due to the misalignment at the time of element design can be reduced to about の of that of the conventional device, whereby the variation in the width of the channel impurity layer can be reduced. Variations in the transfer amount can be reduced.

In this embodiment, the reference pattern 29 is formed at the position where the charge transfer channel 23 is formed, the charge transfer channel 23 is formed first, and the channel stop 26 is formed later. On the contrary, in the present invention, the reference pattern may be formed at a position where the channel stop portion is formed, and the channel stop portion may be formed first.

FIG. 8 is a sectional view showing another embodiment of the present invention. Charge transfer provided in the semiconductor device according to this embodiment.
In the transmission element, a P-type impurity layer (P-type well layer) 32 is formed on an N-type silicon substrate 31. An N-type channel impurity layer (charge transfer channel portion) functioning as a charge transfer CCD is formed on the upper layer of the P-type impurity layer 32.
A P-type channel stop portion 3 is formed beside the
6 are provided. A first gate insulating film 34a made of, for example, SiO ₂ is formed on the entire surface of the P-type impurity layer 32, and a _second gate insulating film 34a made of, for example, Si ₃ N ₄ or SiO ₂ is formed except for a part thereof. Of the second gate insulating film 34b is formed to cover the non-formed portion and the formed portion of the second gate insulating film 34b, for example, Si ₃ N ₄ or SiO 2.
_A third gate insulating film 34c made of ₂ or the like is formed. The third gate insulating film 34c has a depression 39 above a portion where the second gate insulating film 34b is not formed. On the third gate insulating film 34c, a gate electrode 35 is formed above the N-type channel impurity layer 33 with an end disposed inside the recess 39.

Next, a method of manufacturing the charge transfer device will be described. First, as shown in FIG. 9, a P-type impurity layer 32, a first insulating film 34a, and a second insulating film 34b are formed in this order over an N-type silicon substrate 31 over the entire surface. Next, as shown in FIG.
4b, a resist film 37 is formed in a predetermined pattern,
Thereafter, the portion of the second insulating film 34b where the resist film 37 is not formed is removed by etching or the like.
7 is ion-implanted from the non-formed portion to form a P-type impurity layer 3.
A P-type channel stop portion 36 is formed in the upper layer portion 2.

Next, as shown in FIG.
Is removed, and a third gate insulating film 34c is formed to cover the non-formed portion and the formed portion of the second gate insulating film 34b. At this time, the third gate insulating film 34c is formed so that the depression 39 is formed on the portion where the second gate insulating film 34b is not formed. The depression 39 is formed so as to be used as a reference pattern for positioning.

Thereafter, as shown in FIG. 12, a resist film 38 is formed on the third gate insulating film 34c by positioning based on the reference pattern 39, and ion implantation is performed from a portion where the resist film 38 is not formed. To form an N-type channel impurity layer (charge transfer channel section) 33 in the upper layer of the P-type impurity layer 32. Next, the resist film 38
Is removed, and a gate electrode 35 is deposited on the entire surface of the third gate insulating film 34c. Thereafter, the resist pattern 40 is positioned based on the reference pattern 39.
Is formed, and the gate electrode 35 is patterned. As a result, a charge transfer device having the structure shown in FIG. 8 is obtained.

That is, in this embodiment, the channel stop portion 36 is formed via the non-formed portion of the second gate insulating film 34b for forming the reference pattern and without positioning with respect to the reference pattern 39. Thereafter, the charge transfer channel portion 33 is formed by positioning with respect to the reference pattern 39. Therefore, also in this case, although the order of forming the charge transfer channel section 33 and the channel stop section 36 is opposite to that of the above-described embodiment, the alignment is completed only once in forming them. Similar effects can be obtained.

In this embodiment, the reference pattern 39 is formed at the position where the channel stop portion 36 is formed, the channel stop portion 36 is formed first, and the charge transfer channel portion 33 is formed later. In the present invention, conversely, the reference pattern may be formed at a position where the charge transfer channel portion is formed, and the charge transfer channel portion may be formed first.

[0025]

According to the present invention, a semiconductor device is formed on a semiconductor substrate.
Example as first impurity region and second impurity region to be formed
Forming a charge transfer channel portion and a channel stop portion at the same time when forming one of the charge transfer channel portion and the channel stop portion, and then forming the other based on the reference pattern. In this case, the number of times of alignment may be one, and the design margin due to the misalignment at the time of element design can be reduced to about half of the conventional value, whereby the charge transfer channel can be reduced.
Since the variation in the width of the channel portion can be reduced, the variation in the charge transfer amount can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device including a charge transfer element of the present invention.

FIG. 2 is a sectional view showing a manufacturing step of the charge transfer device of FIG. 1;

FIG. 3 is a sectional view showing a manufacturing step of the charge transfer device of FIG. 1;

FIG. 4 is a sectional view showing a manufacturing step of the charge transfer device of FIG. 1;

FIG. 5 is a sectional view showing a manufacturing step of the charge transfer device of FIG. 1;

FIG. 6 is a sectional view showing the manufacturing process of the charge transfer device of FIG. 1;

FIG. 7 is a sectional view showing the manufacturing process of the charge transfer device of FIG. 1;

FIG. 8 is a sectional view showing another embodiment of the present invention.

FIG. 9 is a sectional view showing the manufacturing process of the charge transfer element of FIG. 8;

FIG. 10 is a sectional view showing a manufacturing step of the charge transfer element of FIG. 8;

FIG. 11 is a sectional view showing a manufacturing step of the charge transfer element of FIG. 8;

FIG. 12 is a sectional view showing a manufacturing step of the charge transfer device of FIG. 8;

FIG. 13 is a sectional view showing a manufacturing step of the charge transfer device of FIG. 8;

FIG. 14 is a cross-sectional view showing a conventional charge transfer element.

FIG. 15 is a sectional view showing a manufacturing step of the charge transfer element of FIG. 14;

FIG. 16 is a sectional view showing the manufacturing process of the charge transfer device of FIG. 14;

FIG. 17 is a sectional view showing a manufacturing step of the charge transfer element of FIG. 14;

FIG. 18 is a sectional view showing a manufacturing step of the charge transfer element of FIG. 14;

[Explanation of symbols]

21, 31 Silicon substrate 23, 33 Channel impurity layer (charge transfer channel section) 26, 36 Channel stop section 29, 39 Reference pattern (dent)

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-54561 (JP, A) JP-A-3-285354 (JP, A) JP-A-50-68065 (JP, A) JP-A-50-68065 87283 (JP, A) JP-A-54-59873 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/148 H01L 21/22 H01L 21/339 H01L 29/762

Claims (4)

(57) [Claims] 1. The semiconductor device according to claim 1, wherein the first impurity region and the second impurity region are half.
Method of manufacturing semiconductor device formed on conductive substrate
A first silicon oxide film and a silicon nitride film on the semiconductor substrate.
Layer and a resist pattern of a predetermined shape are sequentially formed,
Etching the silicon nitride film using the resist pattern as a mask
A step of removing the etching, and the first silicon oxidation using the resist pattern as a mask.
By implanting ions through the film, the first impurity
By forming a region and thermally oxidizing the silicon nitride film as a mask,
Forming a second silicon oxide film and forming a second silicon oxide film on the surface of the semiconductor substrate;
Forming a step portion, and exposing the surface of the semiconductor substrate.
A step of depositing a first insulating film and a step of positioning a reference pattern comprising the first step portion.
Alignment of a mask for forming a second impurity region;
As a reference, the second impurity region is
Forming a predetermined positional relationship by
And a method of manufacturing a semiconductor device . 2. The semiconductor device according to claim 1, wherein the first impurity region and the second impurity region are half.
Method of manufacturing semiconductor device formed on conductive substrate
Then, a second insulating film and a resist having a predetermined shape are formed on the semiconductor substrate.
After sequentially forming a resist pattern, the resist pattern is
The second mask is provided on the mask so that the substrate surface is not exposed.
Etching the insulating film, forming a second step on the second insulating film;
Forming, and using the resist pattern as a mask through the second insulating film
The first impurity region by ion implantation
Forming step and a positioning reference pattern comprising the second step portion.
Alignment of a mask for forming a second impurity region;
As a reference, the second impurity region is
Forming a predetermined positional relationship by
And a method of manufacturing a semiconductor device . 3. The semiconductor device according to claim 1, wherein the first impurity region and the second impurity region are half.
Method of manufacturing semiconductor device formed on conductive substrate
Then, a second insulating film and a resist having a predetermined shape are formed on the semiconductor substrate.
After sequentially forming a resist pattern, the resist pattern is
The second mask is provided on the mask so that the substrate surface is not exposed.
Etching the insulating film, forming a second step on the second insulating film;
Forming, and using the resist pattern as a mask through the second insulating film
The first impurity region by ion implantation
Forming and removing the resist pattern on the semiconductor substrate
A third insulating film is deposited on the second insulating film corresponding to the second step portion.
A step of forming a third step, and a step of forming the third step by a mask for forming a second impurity region.
The second impurity region is used as a reference for positioning the mask.
Formed to have a predetermined positional relationship with one impurity region
Manufacturing a semiconductor device, comprising the steps of:
How . 4. The method according to claim 1, wherein the first impurity region is a charge transfer channel.
Or the channel stop section.
The second impurity region is connected to the charge transfer channel or channel.
Characterized in that the other of the tunnel stop portion,
The semiconductor device according to claim 1.
Manufacturing method .