JPH08278902A - Program run away detecting device - Google Patents

Abstract

PURPOSE: To speedily detect a program becoming abnormal. CONSTITUTION: An address decoding part 12 monitors the address signal sent out of a CPU 32 to detect the address signal specifying an address in an address space where no address is allocated, and sends the inverse of NGCS1 signal. When the low-level signal, the inverse of NGCS1 is inverted by an inverter circuit 14 and then inputted to the CPU 32, the CPU 32 decides that the program run away and initiates MNI to perform an interruption process. Further, an address latch circuit 16 temporarily holds the address specified with the address signal when the inverse of NGCS1 signal from the address decoder part 12 goes down to the low level. This illegal address is read in at the time of the MNI processing of the CPU 32 and utilized as information for specifying the cause of malfunction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program runaway detecting device for detecting runaway of a program in a general computer.

[0002]

2. Description of the Related Art Conventionally, in a general computer, a watch dog timer is used to detect runaway of a program. For example, C
When the PU specifies the address of the specific area to which the address space is not assigned, the access is not performed and the program goes out of control. At this time, since the watchdog timer is not reset within the predetermined monitoring period, it is determined that the program has run out, and a nonmaskable interrupt (NMI) is issued to the CPU. As a result, the CPU recognizes that an abnormality has occurred and restores a recoverable one.

[0003]

A special program is required to operate the watchdog timer. In such a program, the watchdog timer monitoring period is normally set to about 1 to 2 seconds with a margin. This is because if the monitoring period is too short, it may be erroneously determined to be abnormal if there is a delay in access or the like. As described above, when the watchdog timer is used, since the monitoring period is set to about 1 to 2 seconds, it is not possible to immediately detect that an abnormality has occurred, and it takes a relatively long time to detect the abnormality. There was a problem of cost. In addition to this, there is a problem that the cause of runaway cannot be specified (access to an illegal address).

The present invention has been made under the above circumstances, and an object thereof is to provide a program runaway detecting device capable of promptly detecting that an abnormality has occurred in a program.

[0005]

In order to achieve the above object, a program runaway detecting apparatus according to a first aspect of the present invention monitors an address signal sent from a central processing unit, and assigns nothing to the address signal. Address abnormal signal generating means for detecting an address in an unspecified address space and sending an address abnormal signal to the central processing unit, and selecting a predetermined device based on the address signal For outputting the chip select signal, an access signal generating means for detecting the output of the address signal and outputting an access signal, and the chip select signal even if the access signal is output. Chip that detects this when it is not output and sends a chip select abnormality signal to the central processing unit Rect abnormal signal generating means, address holding means for temporarily holding the address designated by the address signal when the address abnormal signal or the chip select abnormal signal is received, the address abnormal signal and the chip select abnormal signal And a storage means for temporarily storing.

A program runaway detecting apparatus according to a second aspect of the present invention is the program runaway detecting apparatus according to the first aspect of the invention, wherein the address abnormality signal generating means, the address decoder, the access signal generating means, and the chip select abnormality signal generating means. Is incorporated into one PLD.

A program runaway detecting apparatus according to a third aspect of the present invention monitors an address signal sent from a central processing unit and designates an address within an address space to which no address signal is assigned. Occasionally, an address abnormality signal generating means for detecting this and sending an address abnormality signal to the central processing unit, and an address holding means for temporarily holding an address designated by the address signal when receiving the address abnormality signal , Are provided.

According to another aspect of the program runaway detecting apparatus of the present invention, an address decoder for outputting a chip select signal for selecting a predetermined device based on the address signal sent from the central processing unit, and the address signal. Is output and an access signal is output, and a chip select abnormality signal is detected when the access signal is output but the chip select signal is not output. To the central processing unit, and an address holding unit that temporarily holds the address designated by the address signal when the chip select abnormal signal is received. It is a thing.

According to a fifth aspect of the present invention, there is provided a program runaway detection apparatus which, in the first, second, third or fourth aspect of the present invention, issues an alarm when the address abnormality signal or the chip select abnormality signal is received. It is characterized by comprising means.

[0010]

According to the invention described in claim 1, the address signal is monitored, and when an address in the address space to which no address signal is assigned is designated, this is detected to generate an address abnormality signal. The address abnormal signal generating means for sending and the access signal from the access signal generating means are output, but when the chip select signal from the address decoder is not output, this is detected and the chip select abnormal signal is sent. By including the chip select abnormality signal generating means, it is possible to detect that an abnormality has occurred more quickly than in the case of using a conventional watchdog timer. Further, by temporarily storing the address abnormality signal and the chip select abnormality signal in the storage means, it is possible to specify whether the cause of the abnormality is the central processing unit side or the address decoder side. Further, when the address holding means temporarily holds the address designated by the address signal when receiving the address abnormal signal or the chip select abnormal signal, this address is used as information for specifying the cause of the malfunction. be able to.

According to a second aspect of the present invention, the address abnormal signal generating means, the address decoder, the access signal generating means, and the chip select abnormal signal generating means are incorporated in one PLD by the above configuration, so that the desired signal can be easily obtained. A circuit can be constructed.

According to the third aspect of the present invention, the address signal is monitored, and when an address in an address space to which no address signal is assigned is designated, this is detected to generate an address abnormality signal. By including the address abnormality signal generating means for transmitting, it is possible to quickly detect the abnormality of the program of the central processing unit or the abnormality of the address transmitted from the central processing unit. Further, by temporarily holding the address designated by the address signal when the address holding means receives the address abnormality signal, this address can be used as information for identifying the cause of the malfunction.

According to the invention described in claim 4, when the access signal from the access signal generating means is output but the chip select signal from the address decoder is not output, the chip is detected by the above structure. By having the chip select abnormality signal generating means for transmitting the select abnormality signal, it is possible to quickly detect the abnormality of the program of the central processing unit or the failure of the central processing unit or the address decoder. Further, by temporarily holding the address designated by the address signal when the address holding means receives the chip select abnormality signal, this address can be used as information for identifying the cause of the malfunction.

According to the fifth aspect of the present invention, by the above configuration, the alarm means for issuing an alarm when the address abnormal signal or the chip select abnormal signal is received is provided.
The operator can easily be notified that an abnormality has occurred.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a program runaway detection apparatus according to a first embodiment of the present invention, and FIG. 2 is a diagram showing a memory map in which each device is assigned to a CPU address space.

The program runaway detecting device of the first embodiment is
As shown in FIG. 1, a CPU 32, two memories, and a RAM
(Eg SRAM) 34 and ROM (eg EPR
OM) 36, which detects runaway of the program when transferring data to and from the address decoder unit 12
Inverter circuit 14 and address latch circuit 16
A latch circuit 18, and a light emitting diode (LED) 22 as an alarm means.

Generally, peripheral general-purpose devices such as the RAM 34 and the ROM 36 are mapped to addresses used for instructions in the program of the CPU 32. In the first embodiment, a total of two devices, RAM 34 and ROM 36, are assigned to the address space of the CPU 32, and the memory map at this time is shown in FIG. 1 for CPU 32
There is a memory space of M bytes, RAM34 and ROM3
Each 6 has a storage capacity of 256 kbytes.
RA for the memory area from 00000h to 3FFFFh
The memory area from C0000h to FFFFFh is assigned to the ROM 36. And
The memory area from 40000h to BFFFFh is a non-implementation area to which nothing is assigned. here,
“H” indicates that it is in hexadecimal notation.

Further, in FIG. 1, the address bus 42 is
Is a signal line for designating an address when the CPU 32 accesses the memory, and is connected from the CPU 32 to the address decoder unit 12, the address latch circuit 16, and the like. The data bus 44 is a signal line for transferring data, and includes the address latch circuit 16 and the CPU 32.
Etc. are connected to. Incidentally, in FIG. 1, an address bus and a data bus to the RAM 34 and the ROM 36 are omitted.

The address decoder unit 12 decodes the address signal from the CPU 32 and, at the same time, accesses the RAM 34 or the ROM 3 based on the address signal.
A chip select signal (bar CS ₁ signal, bar CS ₂ signal) for selecting 6 is generated. Here, RA
The bar CS ₁ signal is sent to the ROM 36 to select M34.
It sends the bar CS ₂ signal to select. Because the principle, it is impossible to only one device access to one of the cycle time, the bar CS ₁ signal and a bar CS ₂
The signals do not go low at the same time. In the first embodiment, the address bus 42 is of a synchronous type, and the CPU 32
From the strobe signal (bar AD
S signal) is output. The address decoder unit 1
One cycle is completed by finally outputting the ready signal (bar READY signal) from 2. It may be generated as a separate part from the ready signal generating circuit.
When the address decoder unit 12 receives the bar ADS signal, it checks which address is designated by the address signal and produces the bar CS ₁ signal or the bar CS ₂ signal based on the address signal. As a result, the address issued from the CPU 32 is uniquely assigned to one of the RAM 34 and the ROM 36.

By the way, the CPU 32 normally operates in the RAM 3
4 or the ROM 36 accesses the allocated memory area, but if the program of the CPU 32 is incorrect, or if the CPU 32 has an intermittent failure or a fixed failure, the unimplemented area to which nothing is allocated is accessed. Sometimes. In this case, of course,
Since neither the bar CS ₁ signal nor the bar CS ₂ signal is output,
No data will be fetched from memory. Then, since the data is undefined, the wrong state is read, and the program runs out of control. Therefore, in the first embodiment, the address decoder unit 12 includes the CPU 32.
Monitoring the address signals sent from, and sends the detection to address the abnormality signal (bar NGCS ₁ signal) this when specifying the address in the address space of the address signal is not anything assigned address It has a function as an abnormal signal generating means. For this reason, the address decoder unit 12 includes a PLD (Programabl) that incorporates a logic circuit for outputting the address abnormality signal.
e Logic Device) is being used. The bar NGCS ₁ signal is output to the inverter circuit 14, the address latch circuit 16, and the latch circuit 18.

The inverter circuit 14 inverts the bar NGCS ₁ signal and converts it into a positive logic NGCS ₁ signal. When the high level NGCS ₁ signal is input from the inverter circuit 14, the CPU 32 determines that a program runaway has occurred and determines that a non-maskable interrupt (NMI (no
nmaskable interrupt)) or a normal interrupt (maskable) and apply the specified interrupt processing.

The address latch circuit 16 temporarily holds the address designated by the address signal when the NGCS ₁ signal from the address decoder section 12 becomes low level. This address latch circuit 16
The illegal address stored in is read at the time of the NMI processing of the CPU 32 and is used as information for the CPU 32 to identify the cause of the malfunction.

The latch circuit 18 includes the address decoder section 1
It latches when the bar NGCS ₁ signal from 2 goes low. At this time, the output of the latch circuit 18 is supplied to the LED 22, and the LED 22 lights up. By providing the LED 22, it is possible to easily notify the operator that an abnormality has occurred.

Next, the operation of the program runaway detecting apparatus of the first embodiment will be described with reference to FIGS. 3 and 4. FIG.
4 is a diagram for explaining the timing of each signal, and FIG. 4 is a diagram (state transition diagram) showing the state of the address decoder unit 12 in a state machine notation. Here, in FIG.
“ST1” represents the output state of the address decoder unit 12 in which the bar NGCS ₁ signal is high level, and “ST0” represents the output state of the address decoder unit 12 in which the bar NGCS ₁ signal is low level. Also, "!" Means negative
"&" Indicates a logical product.

First, when the bar ADS signal becomes low level, the cycle is started. When this cycle is started, the address decoder section 12 is in the ST1 state. At this time, the address decoder unit 12 checks at the first rising edge of the clock whether the address signal specifies the non-mounting area. That is, the bar ADS
Signal is low level and address is 40000h to B
If it points to the memory area up to FFFFh (condition A), it is determined that the address points to the non-mounting area, and the address decoder unit 12 transits from the state of ST1 to the state of ST0. On the other hand, if the condition A is not satisfied, the state of ST1 remains as it is. If the READY signal is low level (condition B) when the address decoder unit 12 is in the ST0 state,
The state of ST0 transits to the state of ST1 to prepare for the next cycle. On the other hand, if the condition B is not satisfied, the state of ST0 remains as it is.

As a method of returning the bar NGCS ₁ signal from the low level to the high level, the bar READ is not always required.
It is not necessary to use the Y signal to return. For example, bar NGC
The S ₁ signal is externally NMI processed or interrupt acknowledge /
Some CPUs or the like cannot normally recognize an interrupt unless they are held until a cycle occurs. In this case, the bar NGCS ₁ signal may be returned when NMI processing or interrupt processing is performed.

In the program runaway detecting apparatus of the first embodiment, the address decoder unit monitors the address signal sent from the CPU, detects this when the address points to the non-mounted area, and detects the bar NGCS ₁ signal. If this bar NGCS ₁ signal is generated by sending out, an error occurs in the address sent from the CPU,
You can determine that the program has runaway. Moreover, since the address signal is directly monitored, it is possible to quickly detect the occurrence of an abnormality without requiring a dedicated program as in the case of using a conventional watchdog timer. Further, in the address latch circuit, the illegal address when the NGCS ₁ signal is generated is temporarily held, so that the illegal address is
It can be read during PU interrupt processing and used as information for the CPU to identify the cause of malfunction.
Also, information about this illegal address can be found in the debug (de
It can also be used effectively in the case of a bug).

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a schematic configuration diagram of a program runaway detecting device according to a second embodiment of the present invention.

The program runaway detecting device of the second embodiment is
As shown in FIG. 5, the address decoder unit 52 and the AND
The circuit 54 and the address latch circuit 56 are provided. In the second embodiment, the same reference numerals are given to those having the same functions as those in the first embodiment,
Detailed description thereof will be omitted. RAM34 and ROM
It is assumed that the address of 36 is assigned to the address space of the CPU 32 as in FIG.

The address decoder section 52 decodes the address signal from the CPU 32 and, at the same time, accesses the RAM 34 or the ROM 3 to be accessed based on the address signal.
A chip select signal (bar CS ₁ signal, bar CS ₂ signal) for selecting 6 is generated. The address decoder unit 52 also has a function as an access signal generation unit that detects that an address signal is output and outputs an access signal (ACS signal). For this reason,
As the address decoder section 52, a PLD incorporating a logic circuit for issuing an access signal is used.

The AND circuit 54 has an ACS signal and a bar C.
Input the S ₁ signal and the CS ₂ signal. The AND circuit 54, bar CS ₁ to ACS signal is outputted
Signal or bar CS ₂ signal is not output, this is detected to detect a chip select error signal (NGCS ₂ signal)
To serve as a chip select abnormality signal generating means. The AND circuit 54 outputs the ACS signal and the CS signal.
Only when all of the ₁ signal and the bar CS ₂ signal is high level, NGCS ₂ signal becomes high level. Therefore, access is started, but RAM 34 and ROM
When none of 36 is selected, it can be determined that an error has occurred in the address. This NGCS
_{The two} signals are output to the CPU 32 and the address latch circuit 56.

When the high level NGCS ₂ signal from the AND circuit 54 is input, the CPU 32 applies NMI,
Perform predetermined interrupt processing. In addition, the address latch circuit 5
Reference numeral 6 temporarily holds an invalid address signal from the address bus 42 when the NGCS ₂ signal from the AND circuit 54 becomes high level.

Next, the operation of the program runaway detecting apparatus of the second embodiment will be described with reference to FIGS. 6 and 7. Figure 6
7 is a diagram for explaining the timing of each signal, and FIG. 7 is a diagram (state transition diagram) showing the state of the address decoder unit 52 in a state machine notation. Here, in FIG.
“ST1” represents the output state of the address decoder section 52 in which the ACS signal is at high level, and “ST0” represents the output state of the address decoder section 52 in which the ACS signal is at low level.

When the cycle is started, the address decoder section 52 is in the ST0 state. At this time, if the bar ADS signal is at the low level (condition A), the address decoder unit 52 transits from the ST0 state to the ST1 state. On the other hand, if the condition A is not satisfied, the state of ST0 remains as it is. Next, the address decoder unit 52
There when in the state of the ST1, when none of the bars CS ₁ signal and bars CS ₂ signal is at the high level, NGCS ₂ signal from the AND circuit 54 becomes high level. on the other hand,
When either the bar CS ₁ signal or the bar CS ₂ signal is low level, the NGCS ₂ signal from the AND circuit 54 becomes low level. In addition, the address decoder unit 52 is S
In the state of T1, if the READY signal is at the low level (condition B), the state of ST1 changes to ST0.
And the NGCS ₂ signal also goes low,
It will prepare for the next cycle. On the other hand, if the condition B is not satisfied, the state of ST1 remains as it is.

[0035] In the program runaway detection apparatus of the second embodiment detects this when not in any of the bars CS ₁ signal and bars CS ₂ signal output for ACS signal from the address decoder is output By having the chip select abnormality signal generating means (AND circuit) for transmitting the NGCS ₂ signal by means of the above, when this NGCS ₂ signal is generated, it is determined that an abnormality has occurred in the address sent from the CPU and the program has run away can do. Moreover, since the bar CS ₁ signal and the bar CS ₂ signal are directly monitored, it is possible to quickly detect that an abnormality has occurred.

Particularly, in the second embodiment, unlike the case of the first embodiment, the bar CS ₁ signal and the bar CS ₂ signal are monitored to indirectly determine whether or not the address is abnormal. Even the failure of the address decoder unit can be detected, and the target of abnormality detection is expanded as compared with the case of the first embodiment. That is, in the case of the first embodiment, the address signal is monitored and the bar CS ₁ signal and the bar CS signal are monitored.
_{Since the 2} signals are not monitored, the abnormality of the address decoder itself cannot be detected. In the case of the second embodiment,
For example, CPU itself has put a normal address, the address decoder unit fails, even if the bar CS ₁ signal or bar CS ₂ signal had been fixed at a high level, it is possible to detect the abnormality.

In the address latch circuit 56,
By temporarily holding the illegal address when the NGCS ₂ signal is generated,
It can be read during U interrupt processing and used as information for the CPU to identify the cause of malfunction.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a schematic configuration diagram of a program runaway detecting device according to a third embodiment of the present invention.

The program runaway detecting device of the third embodiment is
As shown in FIG. 8, the address decoder 62 and the AND
Circuit 64, address latch circuit 66, and OR circuit 68
The LED 72 and the register section 74 are provided. In the third embodiment, those having the same functions as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. In addition, RAM34 and ROM3
It is assumed that the address 6 is assigned to the address space of the CPU 32 as in FIG.

The address decoder unit 62 decodes the address signal from the CPU 32 and, at the same time, accesses the RAM 34 or ROM 3 to be accessed based on the address signal.
A chip select signal (bar CS ₁ signal, bar CS ₂ signal) for selecting 6 is generated. The address decoder unit 62 monitors the address signal sent from the CPU 32, detects this when the address signal designates an address in an address space to which nothing is assigned, and detects the address abnormal signal (NGCS). Function as an address abnormal signal generating means for sending out ₁ signal), and the access signal (A
And a function as an access signal generating means for outputting a CS signal). Therefore, as this address decoder 62, a PLD incorporating a logic circuit for issuing an address abnormality signal and an access signal is used. NGC
The S ₁ signal is output to the OR circuit 68 and the register unit 74, and the ACS signal is output to the AND circuit 64.

The AND circuit 64 has an ACS signal and a bar C.
The S ₁ signal and the bar CS ₂ signal are input. AND circuit 6
4, the chip select and sends the detection to the chip select abnormal signal (NGCS ₂ signal) it when the bar CS ₁ signal or bar CS ₂ signal is not output to ACS signal is output abnormality signal generator Play a role as a means. The NGCS ₂ signal is output to the OR circuit 68 and the register unit 74.

The OR circuit 68 uses the NGCS ₁ signal and the NGCS signal.
When any of the CS ₂ signals becomes high level, it is determined that an abnormality has occurred and a signal is sent to the CPU 32. When receiving the signal from the OR circuit 68, the CPU 32 applies NMI and performs a predetermined interrupt process. Further, the address latch circuit 66 temporarily holds an invalid address signal from the address bus 42 when the output from the OR circuit 68 becomes high level.

The register section 74 receives the NGCS ₁ signal and NGCS signal.
The output of the CS ₂ signal is temporarily stored. CPU3
2 can identify whether the address signal is abnormal or the chip select signal is abnormal by reading the information stored in the register unit 74 during the NMI processing. FIG. 9 shows a logic for identifying the cause of the abnormality based on the outputs of the NGCS ₁ signal and the NGCS ₂ signal. When both the NGCS ₁ signal and the NGCS ₂ signal are high level, it is determined that the address signal is abnormal. In this case, the high level of the NGCS ₂ signal is considered to be due to the high level of the NGCS ₁ signal. The reason why the address signal becomes abnormal is that there is an error in the program of the CPU 32 or the output of the address of the CPU 32 itself is fixed at low level or high level.
If there is no problem in the program, it is necessary to replace the CPU 32. Also, when the NGCS ₁ signal is high level,
If the NGCS ₂ signal is low level, or if the NGCS
_{When the 1} signal is low level and the NGCS ₂ signal is high level, it is determined that the chip select signal is abnormal. The reason why the chip select signal becomes abnormal is that the output of the bar CS ₁ signal or the bar CS ₂ signal from the address decoder unit 62 is fixed at a low level or a high level. It is necessary to replace the decoder unit 62. However, NG
It is unlikely that the CS ₁ signal will be high and the NGCS ₂ signal will be low. And
When both the NGCS ₁ signal and the NGCS ₂ signal are low level, it is determined to be normal.

Further, the register section 74 outputs a signal and turns on the LED 72 when the NGCS ₁ signal or the NGCS ₂ signal becomes high level. By providing the LED 72, it can be understood that the program is created in a place where there is no address, especially when the LED 72 is turned on when the program is being developed.
In this case, if the address held in the address latch circuit 66 is read, it is checked whether there is a part in which the address is designated in the program, and the program of that part is rewritten, the program can be easily modified. You can

In the program runaway detecting apparatus of the third embodiment, the address signal sent from the CPU is monitored, and when the address indicates the non-mounting area, the address signal is detected and the NGCS ₁ signal is sent out. and generating means (address decoder), a NGCS ₂ signal by detecting this when none of the bars CS ₁ signal and bars CS ₂ signal for ACS signal from the address decoder is output not output By having the chip select abnormality signal generating means (AND circuit) for transmitting,
When the NGCS ₁ signal or the NGCS ₂ signal is generated, it can be determined that an error has occurred in the address sent from the CPU and the program has runaway. Moreover, since the address signal and the bar CS ₁ signal and the bar CS ₂ signal are monitored, it is possible to quickly detect that an abnormality has occurred.

In the register section, the NGCS ₁ signal and NGCS signal
By temporarily storing the output of the CS ₂ signal, it is possible to specify whether the cause of the abnormality is on the CPU side or the address decoder section side. Furthermore, in the address latch circuit, the NGCS ₁ signal or NGCS
By temporarily holding the illegal address when the ₂ signal occurs, this illegal address can be read during interrupt processing of the CPU and used as information for the CPU to identify the cause of malfunction. .

The present invention is not limited to the above embodiments, but various modifications can be made within the scope of the gist thereof. For example, the address latch circuit may be configured in multiple stages such as FIFO (first-in first-out) instead of one stage. The runaway of the program is stopped by the NMI processing, but there is a possibility that the address signals will be transmitted one after another even after the address abnormal signal or the chip select abnormal signal is output. In this case, if the address latch circuit is configured in, for example, three stages or four stages, each address can be stored in each step.

In each of the above embodiments, the case where the CPU issues an NMI interrupt when it receives an address abnormality signal or a chip select abnormality signal has been described.
The PU may also provide normal maskable interrupts.

Furthermore, the address decoder unit 52 and the AND circuit 54 are incorporated into one PLD in the second embodiment, and the address decoder unit 62, the AND circuit 64, and the OR circuit 68 in the third embodiment. And may be incorporated into one PLD. Thereby, a desired circuit can be easily configured.

[0050]

As described above, according to the first aspect of the invention, the address signal is monitored and detected when the address in the address space to which no address signal is assigned is designated. Address abnormal signal generating means for sending out an address abnormal signal by an address and the chip select signal is detected when the access signal is outputted from the access signal generating means but the chip select signal is not outputted from the address decoder. By having a chip select abnormality signal generating means for transmitting an abnormality signal,
Compared with the case of using the conventional watchdog timer, it is possible to detect the occurrence of an abnormality more quickly, and
By temporarily storing the address abnormality signal and the chip select abnormality signal in the storage means, it is possible to specify whether the cause of the abnormality is on the side of the central processing unit or the side of the address decoder. By temporarily holding the address designated by the address signal when the holding means receives the address abnormal signal or the chip select abnormal signal, this address can be used as information for identifying the cause of the malfunction. A program runaway detection device can be provided.

According to the second aspect of the invention, the address abnormality signal generating means, the address decoder, the access signal generating means, and the chip select abnormality signal generating means are combined into one P.
By incorporating it in the LD, it is possible to provide a program runaway detection device that can easily configure a desired circuit.

According to the third aspect of the invention, the address signal is monitored, and when an address in the address space to which no address signal is assigned is designated, this is detected and an address abnormality signal is sent out. By having the address abnormality signal generating means, it is possible to quickly detect the occurrence of an abnormality in the address sent from the central processing unit, and when the address holding means receives the address abnormality signal, it is designated by the address signal. By temporarily holding the generated address, it is possible to provide a program runaway detecting device that can use this address as information for identifying the cause of the malfunction.

According to the fourth aspect of the invention, when the access signal from the access signal generating means is output but the chip select signal from the address decoder is not output, this is detected to detect a chip select abnormality. By having the chip select abnormality signal generating means for transmitting a signal, it is possible to quickly detect the abnormality of the program of the central processing unit or the failure of the central processing unit or the address decoder, and the address holding means. Provides a program runaway detection device that can use this address as information for identifying the cause of malfunction by temporarily holding the address specified by the address signal when the chip select abnormal signal is received by be able to.

According to the fifth aspect of the present invention, by providing the alarm means for issuing an alarm when the address abnormal signal or the chip select abnormal signal is received, it is possible to easily inform the operator that an abnormal condition has occurred. It is possible to provide a programmable runaway detecting device.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a program runaway detection apparatus that is a first embodiment of the present invention.

FIG. 2 is a diagram showing a memory map in which each device is assigned to an address space of a CPU.

FIG. 3 is a diagram for explaining the timing of each signal.

FIG. 4 is a diagram (state transition diagram) showing states of an address decoder in state machine notation.

FIG. 5 is a schematic configuration diagram of a program runaway detection device that is a second embodiment of the present invention.

FIG. 6 is a diagram for explaining the timing of each signal.

FIG. 7 is a diagram (state transition diagram) showing a state of an address decoder unit in a state machine notation.

FIG. 8 is a schematic configuration diagram of a program runaway detection apparatus that is a third embodiment of the present invention.

FIG. 9 is a diagram showing a logic for identifying a cause of abnormality based on outputs of an address abnormality signal and a chip select abnormality signal.

[Explanation of symbols]

 12, 52, 62 Address decoder section 14 Inverter circuit 16, 56, 66 Address latch circuit 18 Latch circuit 22, 72 LED 32 CPU 34 RAM 36 ROM 42 Address bus 44 Data bus 54, 64 AND circuit 68 OR circuit 74 Register section

Claims (5)

[Claims] 1. An address signal sent from a central processing unit is monitored, and when the address signal designates an address in an address space to which nothing is assigned, the address signal is detected to detect an address abnormality signal. Address abnormal signal generating means for sending to the central processing unit, address decoder for outputting a chip select signal for selecting a predetermined device based on the address signal, and access by detecting output of the address signal An access signal generating means for outputting a signal, and a chip select for detecting the chip select signal when the access signal is being output but not outputting the chip select signal and sending a chip select abnormal signal to the central processing unit. Abnormal signal generating means and the address abnormal signal or the chip select abnormal signal are received. An address holding means for temporarily holding the address signal specified by the address to come, the address error signal and a program runaway detection apparatus comprising: a storage means for temporarily storing said chip select abnormality signal. 2. The program runaway detection according to claim 1, wherein the address abnormality signal generating means, the address decoder, the access signal generating means, and the chip select abnormality signal generating means are incorporated in one PLD. apparatus. 3. The address signal sent from the central processing unit is monitored, and when the address signal designates an address in an address space to which nothing is assigned, the address signal is detected to detect an address abnormality signal. A program runaway detecting device comprising: an address abnormality signal generating means for sending to a central processing unit; and an address holding means for temporarily holding an address designated by the address signal when the address abnormality signal is received. . 4. An address decoder for outputting a chip select signal for selecting a predetermined device based on an address signal sent from a central processing unit, and an access signal for detecting the output of the address signal. Access signal generating means for outputting, and a chip select abnormal signal for detecting the chip select signal when the access signal is being output but not outputting the chip select signal and sending a chip select abnormal signal to the central processing unit. A program runaway detecting apparatus comprising: a generating unit; and an address holding unit that temporarily holds an address designated by the address signal when the chip select abnormality signal is received. 5. The program runaway detecting apparatus according to claim 1, further comprising alarm means for issuing an alarm when the address abnormal signal or the chip select abnormal signal is received.