JP4621825B2 - Circuit device with CPU - Google Patents

Description

  The present invention relates to a circuit device equipped with a CPU, and more particularly to a circuit device provided with a self-diagnosis function.

  Conventionally, when a product incorporating a circuit incorporating a CPU, such as a card reader, is shipped to the market, an inspection is performed in advance to prevent a defective product from flowing into the market. In this inspection, first, a circuit equipped with a CPU is connected to an inspection apparatus, and in accordance with the inspection program, for example, a control signal is sent from the CPU to a plurality of external devices such as a motor for carrying a card and an actuator for opening and closing a shutter. It is determined whether it is transmitted and operates normally (for example, whether the card is conveyed in a desired direction or whether the shutter is opened and closed at a desired timing).

  Thus, when a product incorporating a circuit incorporating a CPU is shipped to the market, it is inspected whether each part operates normally according to the inspection program.

  However, in the conventional inspection described above, it is assumed that the CPU and CPU peripheral devices such as ROM and RAM connected to the CPU and the address bus normally operate, and the CPU and CPU peripheral devices do not operate normally. In this case, the inspection program cannot operate correctly and it is impossible to perform the inspection. In addition, it takes time to identify abnormal locations and causes of the CPU and the CPU peripheral devices.

  That is, when the CPU and the CPU peripheral device do not operate normally, a tester is applied to each contact in the circuit, for example, there is no soldering failure anywhere in the circuit (including the CPU pin). It took a long time to identify the problem part. In addition, when the circuit wiring is fine or complicated, it is difficult to apply a tester to a desired contact in the circuit, and it is difficult to identify a defective part.

  The present invention has been made in view of such a point, and an object of the present invention is to detect an abnormal position of the CPU and a peripheral device of the CPU in the circuit on which the CPU is mounted, and an abnormal position around the CPU and its cause. It is an object of the present invention to provide a circuit device having a self-diagnosis function that can easily specify the above.

  In order to solve the above-described problems, the present invention decodes an address output from the CPU, and sets a comparison address based on a chip select signal output from the CPU. The decoded value is compared.

  More specifically, the present invention provides the following.

(1) a CPU, an address decoding unit for decoding an address output from the CPU, a comparison address setting unit for setting a comparison address based on a chip select signal output from the CPU, the comparison address and the address a comparator for comparing whether the output of the decoding unit are matched, along with information indicating that said comparison address and an output of said address decoder unit do not match performs error notification triggered by input And an error notification unit for displaying the address bits which are not matched by the comparison unit .

  According to the present invention, an address decoding unit (for example, an address decoder) that decodes an address output from a CPU (in this specification, including an MPU), and a chip select signal (for example, a RAM chip select) output from the CPU. The circuit device includes a comparison address setting unit that sets a comparison address based on a signal, a ROM chip select signal, and the like, and a comparison unit that compares whether or not the comparison address matches the output of the address decoding unit. As a result, it is possible to easily identify the abnormal part of the circuit on which the CPU is mounted using the addresses of the CPU and its peripheral devices.

  That is, when the comparison address set by the comparison address setting unit matches the output from the address decoding unit, it can be seen that the address bits corresponding to the address output from the CPU are normal. If they do not match, it can be seen that the address bits corresponding to the address output from the CPU are abnormal.

  Here, the present invention uses a chip select signal for selecting a chip to be generated in the CPU and to be activated in addition to using a decode value obtained by decoding an address output from the CPU for circuit inspection. The comparison address set corresponding to is used. Since the chip select signal is a highly reliable signal transmitted through a single signal line connecting the CPU and peripheral devices (ROM, RAM, etc.), it is possible to accurately identify an abnormal address area around the CPU. Can do. The “chip select signal” refers to each signal for activating (activating) a plurality of RAMs, a plurality of ROMs, and the like.

  According to the present invention, when the information indicating that the comparison address and the output of the address decoding unit do not match is input to the circuit device described above, the error notification unit that performs error notification is provided. The examiner knows that an abnormality has occurred in the addresses around the CPU.

( 2 ) The circuit device according to ( 1 ), wherein the error notification unit includes an LED.

  According to the present invention, since the error notification unit described above is configured by using an LED, the inspector has confirmed that an abnormality has occurred in the address around the CPU by visually confirming the light emission of the LED. I understand.

( 3 ) The circuit device according to (1) or (2) , wherein the circuit device is built in a drive circuit device that drives a card reader that reads and writes data from and to a card.

  According to the present invention, the circuit device described above includes a CPU that drives a card reader (which includes a card reader / writer in this specification) that reads and writes data from and to a magnetic card or IC card. Because it is used as a self-diagnosis circuit built in the mounted drive circuit device, when the card reader is shipped to the market, if the inspection program does not operate normally due to an abnormal address around the CPU, the CPU peripheral address Can be easily identified.

(4) A circuit device including a CPU, wherein a comparison address setting unit that sets a comparison address based on a chip select signal output from the CPU, and the comparison address and an actual address output from the CPU match A comparison unit for comparing whether or not to perform an error notification triggered by input of information indicating that the comparison address and the entity address do not match, and an address that is not matched by the comparison unit A circuit device comprising a self-inspection circuit including an error notification unit for displaying a bit .

  According to the present invention, a comparison address is set in a circuit device including a CPU based on a chip select signal output from the CPU, and whether or not the comparison address matches an actual address output from the CPU. Since the self-inspection circuit for comparing the two is provided, it becomes possible to directly specify the address bit that is abnormal in the actual address output from the CPU.

  Here, the “substance address” refers to an address representing the actual status of the address line output from the CPU. For example, when an address line becomes abnormal due to a soldering failure or the like, the address is in an abnormal state reflecting the situation.

  According to the present invention, the above-described circuit device is provided with the error notification unit that performs error notification when the information indicating that the comparison address does not match the actual address is input. Can directly and easily specify which address bit is abnormal in the actual address output from the CPU.

Before Symbol error notification unit, when said physical block address and the comparison address is not matched, you further comprising a display unit for displaying the address bits inconsistent with the comparison unit.

  According to the present invention, the error notification unit described above is provided with a display unit that displays the address bits that are not matched by the comparison unit when the entity address and the comparison address do not match. By visually recognizing the display, it is possible to directly and visually specify which address bit has become abnormal.

  According to the circuit device of the present invention, for example, there is a soldering failure or the like in an address (including a CPU pin) in a CPU peripheral circuit (CPU and a CPU peripheral device such as ROM and RAM connected to the CPU and an address bus). Even if it has occurred, it is possible to easily identify the address abnormality location

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing an outline of a circuit device 1 according to an embodiment of the present invention.

  1A, a circuit device 1 includes a CPU 10 serving as a comprehensive control center, a RAM 11 (for example, DRAM or SRAM) functioning as a working area for the CPU 10, and a ROM 12 (for example, various programs and variables). For example, a flash memory, EPROM, EEPROM, etc.), an address decoder 13 for decoding an address output from the CPU 10, a comparison address setting unit 14 for receiving a RAMCS (RAM chip select) signal or a ROMCS (ROM chip select) signal, The comparison unit 15 compares the output of the address decoder 13 with the comparison address set based on the chip select signal, and the error notification unit 16 performs error notification based on the comparison result of the comparison unit 15. ing.

An address output from the CPU and used to specify a target to control information writing or reading (in the case of the RAM 11 or ROM 12, it may indicate a physical column and row in a memory cell) is an address bus. The data is transmitted to the RAM 11, ROM 12, and address decoder 13 via 101. In FIG. 1 (a), but the address bus 101 is a single line, in fact consists of for example n + 1 bits of the address _A 0 -A _n. Although only the address bus 101 is considered here as a bus, a data bus or the like may be considered as another bus.

  Of the chip select signals output from the CPU and used to select one of a plurality of chips (DSP, memory, etc.) to be activated, the RAMCS signal is supplied to the RAM 11 and the comparison address setting unit 14 via the RAMCS line 102. The ROMCS signal is transmitted to the ROM 12 and the comparison address setting unit 14 via the ROMCS line 103. That is, when the RAMCS signal becomes active (for example, an L level signal), the RAM 11 is activated and becomes active, and can be read and written. In addition, when the ROMCS signal becomes active (for example, an L level signal), the ROM 12 is activated and becomes active, and becomes readable.

  The address decoder 13 is generally composed of a logic IC, and more specifically is a combination of an AND circuit and a NOT circuit. However, the present invention is not limited to this, and may be configured by combining, for example, a flip-flop with an AND circuit and a NOT circuit. In this way, when the address decoder 13 is used, the number of signals input to the comparison unit can be reduced (the output of the address decoder is specified by a peripheral device such as a ROM or a RAM according to the output, and for each address bit. Therefore, the circuit of the comparison unit is simplified, saving the board space and reducing the component cost.

  The comparison address setting unit 14 selects a comparison address stored in advance in the RAMCS signal and the ROMCS signal. Here, the comparison address setting unit 14 corresponds to a decoder (hereinafter abbreviated as “DEC”) for decoding RAMCS and ROMCS, and a RAM address and ROM corresponding to the RAM, as shown in FIG. 1B, for example. It comprises a selector (hereinafter abbreviated as “SEL”) that stores ROM addresses in advance and outputs either RAM addresses or ROM addresses as comparison addresses based on the output of DEC. The SEL can be realized, for example, by a logic circuit that combines two AND circuits and an OR circuit that uses two outputs of the AND circuits as two inputs.

  Here, the comparison address (RAM address or ROM address) stored in the comparison address setting unit 14 in the same format as the output (decoded value) of the address decoder 13 can be compared by the comparison unit 15. It is said.

  The comparison unit 15 can also be realized by combining logic circuits. If the output (comparison address) of the comparison address setting unit 14 does not match the output (decoded value) of the address decoder 13, an error notification is sent to the error notification unit 16. Is to do. In addition, as the error notification part 16, light emitting elements, such as LED, can be used, for example.

  FIG. 2 is a flowchart showing a flow of information processing of the circuit device 1 according to the embodiment of the present invention.

  In FIG. 2, first, the CPU 10 selects a chip (or device) such as a RAM or ROM to be inspected (step S1). Thereafter, an address is output from the CPU 10 (step S2), and the address is transmitted to the address decoder 13. Next, the address decoder 13 decodes the address (step S3), and the decoded value is input to the comparison unit 15 (step S4).

  On the other hand, the CPU 10 outputs a chip select signal for selecting and activating a chip (ROM or RAM) to the comparison address setting unit 14 (step S5). Next, the comparison address setting unit 14 switches the comparison address to be inspected in response to the chip select signal from the CPU 10 (step S6). Then, an address corresponding to either RAM or ROM is output as a comparison address to the comparison unit 15 (step S7).

  Next, a comparison process is performed in the comparison unit 15 (step S8). At this time, it is determined whether or not the decoded value input in step 4 matches the comparison address input in step S7 (step S9). If they match, normal display (or special processing is performed). If there is no coincidence (step S10), an error display (for example, a process of notifying the error notification unit 16 of an error and causing the LED to shine) is performed (step S11). Then, it is determined whether or not there are other chips to be inspected, that is, whether or not to end the series of processing (step S12), and the series of processing is continued until the end of the chip to be inspected. ) Is repeated sequentially.

  As described above, according to the circuit device 1 of the present invention, if the comparison address set by the comparison address setting unit 14 and the decode value output from the address decoder 13 do not match, an error occurs. Since the LED lights up in the notification unit 16 and the address bit corresponding to the address output from the CPU is found to be abnormal, as a result, in the peripheral circuit of the CPU 10 (the ROM and the ROM connected to the CPU and the address bus) It is possible to easily identify a defective portion such as when a soldering failure or the like occurs in an address (including a CPU pin) of a CPU peripheral device such as a RAM.

  As described above, according to the present embodiment, it is possible to efficiently inspect a defective product in an inspection when a product incorporating a circuit incorporating a CPU is shipped to the market. Even after the shipment, it is possible to easily identify a defective part when a defect occurs in the product.

  As the address decoded by the address decoder 13, all the address bits to be used may be decoded, or only the upper address may be decoded in order to prevent the circuit scale from becoming large. In a board having a programmable device such as an FPGA, the address decoder 13, the comparison address setting unit 14, the comparison unit 15, the error notification unit 16, and the like may be mounted in the FPGA.

[Modification]
In the above-described embodiment, the address decoder 13 is used to simplify the circuit of the comparison unit 15 and save the board space. However, the address decoder 13 may be omitted. The following embodiment will be described.

  When the address decoder 13 is not used, the actual address output from the CPU 10 is compared with the comparison address. In this case, the comparison address has a format that can be compared with the actual address, and is stored in the comparison address setting unit 14 in advance. With such a configuration, it is possible to directly identify an abnormal address bit in the actual address output from the CPU 10.

  Further, a 7-segment display, a liquid crystal display, or the like may be connected to the error notification unit 16 as a display unit that displays a bit error location of the address bits.

  In the processing flow in the above-described embodiment, the difference in FIG. 2 is that the address output (substance address) output from the CPU 10 in step S2 and the comparison address output in step S7 are directly compared in step S8. is there. That is, steps S3 and S4 in FIG. 2 are omitted. At this time, it is possible to specify which address bit is abnormal in a bit unit by the comparison processing in the comparison unit.

  The circuit device according to the present invention is useful as one that can easily identify an abnormal address portion around the CPU of a circuit on which the CPU is mounted.

1 is a circuit diagram showing an outline of a circuit device according to an embodiment of the present invention. It is a flowchart which shows the flow of the information processing of the circuit device which concerns on embodiment of this invention.

Explanation of symbols

1 circuit device 10 CPU
11 RAM
12 ROM
13 Address decoder 14 Comparison address setting unit 15 Comparison unit 16 Error notification unit

Claims (4)

CPU,
An address decoding unit for decoding an address output from the CPU;
A comparison address setting unit for setting a comparison address based on a chip select signal output from the CPU;
A comparison unit for comparing whether or not the comparison address matches the output of the address decoding unit;
An error notification unit that performs error notification triggered by input of information indicating that the comparison address and the output of the address decoding unit do not match, and displays an address bit that is not matched by the comparison unit; And a circuit device.   The circuit device according to claim 1, wherein the error notification unit includes an LED.   3. The circuit device according to claim 1, wherein the circuit device is built in a drive circuit device that drives a card reader that reads and writes data from and to a card. A circuit device comprising a CPU,
A comparison address setting unit for setting a comparison address based on a chip select signal output from the CPU;
A comparison unit for comparing whether or not the comparison address and the actual address output from the CPU match;
An error notification unit for notifying an error when information indicating that the comparison address and the entity address do not match is input, and displaying an address bit that is not matched by the comparison unit. A circuit device comprising a self-test circuit.

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