JPH08278485A - Activ matrix lcd driving method - Google Patents

Abstract

PURPOSE: To provide an active matrix LCD driving method superimposing a conversion signal generated by an input video signal on a DC voltage applied to a common electrode of a TFT and eliminating DC unbalance applied to an active matrix LCD. CONSTITUTION: When a video signal VIDA inputted to a signal line 2 is impressed to the source electrode S of the TFT 3 at the on-timing of a scan signal VG inputted to a scanning line 1, the video signal VIDA whose video signal synchronizing with its odd field is phase inverted by a data signal adjustment circuit 11, and the video signal synchronizing with its even field is outputted to a low-pass filter 12 at the same phase as it is. The video signal is converted to integration voltage signals c, c' of a low frequency component at every field by the low-pass filter 12 to be outputted to an adder 13, and is superimposed on the DC voltage Vc outputted from the DC voltage 7 by the adder 13 to be applied to a pixel electrode 4 connected to the common electrode C of the TFT 3 as correction voltages c, c'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of an active matrix LCD, and more particularly, to canceling an imbalance of a DC component remaining in a pixel electrode for each selected section,
The present invention relates to a driving method of an active matrix LCD that maintains DC balance in the entire LCD display area.

[0002]

2. Description of the Related Art A circuit for one pixel of a conventional active matrix LCD has a TFT (Thin Film) connected to an intersection of a scanning line 1 and a signal line 2 as shown by a broken line in FIG.
Transistor) 3, a pixel electrode 4 connected to the common electrode C of the TFT 3 and an auxiliary capacitor 5 (Cstg). Further, on the ground side of the signal line 2 and the common electrode C in the figure, a predetermined DC voltage V, V is supplied from the DC power supplies 6, 7.
c is applied. Note that CGS in the figure is a parasitic capacitance between the gate electrode G and the source electrode S of the TFT 3.

In this circuit structure, a scanning signal 8 and a video signal (video signal) 9 are input to the scanning line 1 and the signal line 2 as shown in the figure, and the timing at which the scanning signal is input. Then, the gate electrode G of the TFT 3 is turned on, and at the ON timing, the video signal is input to the source electrode S of the TFT 3 and transmitted to the common electrode C side, and input to the pixel electrode 4 and the auxiliary capacitance Cstg connected to the common electrode C. A charge according to the video signal is accumulated.

At this time, the voltage ΔV applied to the pixel electrode 4
Is expressed by the following equation (1).

ΔV = V (VS) · CGS / (CGS + CLC + CSTG) (1) A specific example of the relationship among the scanning signal 8, the video signal 9 and the DC voltage applied to the scanning line 1, the signal line 2 and the TFT 3. This is shown in (Example 1) of FIG. In FIG. 22, the video signal V
The case where the IDA is a signal that changes in a binary manner is shown.

In FIG. 22, the so-called jump-in voltage ΔV corresponding to the above equation (1) depends on the input video signal VIDA and is asymmetrical due to AC driving. For example, the TFT 3 shown in FIG. Is NMOS
In case of (Nitride Metal Oxide Sem-iconductor), T
When a constant DC voltage Vc is applied to the common electrode C of the FT3, the DC component is always applied to the pixel electrode (liquid crystal).

Therefore, it is impossible to maintain DC balance between the pixel electrode 4 to which an irregular video signal is input and the common electrode C to which a DC voltage is applied, constantly and in the entire display area. Had occurred.

That is, conventionally, the TFT 3 shown in FIG.
Is an NMOS and, for example, when the video signal VIDA is applied to the signal line 2 as shown in the figure, as shown in the figure, the effective voltage of the pixel electrode potential Vp of the odd field and the even field in one frame is Comparing with each other, since the effective voltage of the odd field is smaller than the effective voltage of the even field, the DC voltage Vc applied to the common electrode C is such that the effective voltage of the odd field = the effective voltage of the even field. Is set to VCOM in the figure to eliminate the DC component.

[0009]

However, in the conventional method of removing the DC component in the active matrix LCD shown in (Example 1) of FIG.
Although the DC voltage Vc applied to the common electrode C of the TFT 3 is set to a value lowered to VCOM in the figure, the video signal VIDB applied to the signal line 2 shown in (Example 2) of FIG.
When the potential changes in a multi-valued manner as described above, ΔV changes due to the change in the potential. Therefore, simply lowering the DC voltage Vc applied to the common electrode C to VCOM results in "the effective voltage in the odd field". = Effective voltage of even field "," Effective voltage of odd field ≠ Effective voltage of even field ", the DC component remains, and there is a problem that the balance cannot be maintained.

An object of the present invention is to superimpose a conversion signal generated by an input video signal on a DC voltage applied to a common electrode of a TFT and to apply D to an active matrix LCD.
Active matrix LC for removing C imbalance
D drive method.

[0011]

According to the first aspect of the present invention,
A plurality of signal lines and a plurality of scanning lines are arranged in a matrix, a transistor is connected to one electrode of a pixel at each intersection of these signal lines and a scanning line, and a common voltage is applied to the common electrode of the other pixel. And scanning each scanning line at a scanning timing corresponding to the video input signal, and the video input signal input to each signal line is alternately a positive and negative video signal with respect to the common voltage. In an active matrix LCD driving method of accumulating and displaying an image signal on each pixel electrode by alternating-currently driving each transistor while inverting the polarity every predetermined period, a video input signal input to each signal line is inputted. Depending on the magnitude of the voltage change or the amount of signal, the pole side having a larger effective value voltage of the video input signal is decreased by a predetermined amount with respect to the common voltage, and the pole side having a smaller effective value voltage is reduced. It has a voltage adjusting means for generating a conversion signal adjusted so that the positive RMS voltage and the negative RMS voltage become equal to each other by a fixed amount, and the conversion signal is supplied to the common electrode of the pixel. It has a feature.

Further, as in the invention described in claim 2,
The voltage adjusting means phase-inverts the video input signal of either the odd field or the even field, and uses an integrator circuit for each of the video input signal of the other field in the same frame as the phase-inverted video input signal. It is effective to integrate and integrate and supply to the common electrode of the transistor.

Further, as in the invention described in claim 3,
It is effective that the voltage adjusting unit supplies a low frequency component of the video input signal to the common electrode of the transistor by using a low pass filter.

Further, as in the invention described in claim 4,
It is effective that the voltage adjusting unit uses a rectangular wave generating circuit to supply a rectangular wave signal corresponding to a change in the video input signal to the common electrode of the transistor.

Further, as in the invention described in claim 5,
It is effective that the voltage adjusting means uses a triangular wave generating circuit to supply a triangular wave signal corresponding to a change in the video input signal to the common electrode of the transistor.

Further, as in the invention described in claim 6,
It is effective that the voltage adjusting means uses a sawtooth wave generation circuit to supply a sawtooth wave signal corresponding to a change in the video input signal to the common electrode of the transistor.

Further, as in the invention described in claim 7,
It is effective that the voltage adjusting unit superimposes the converted signal and the predetermined voltage using an adder circuit and supplies the superposed signal to the common electrode of the transistor.

According to the invention described in claim 8,
The voltage adjusting means generates an integrated signal according to a change in the video input signal by using an integrating circuit, and adds or superimposes the integrated signal on the common voltage according to the magnitude of the integrated signal with respect to the common voltage. It is effective to perform subtractive superposition and supply to the common electrode of the transistor.

Further, as in the invention described in claim 9,
The voltage adjusting means uses an integrator circuit to generate respective integrated signals according to changes in the odd field and the even field of the video input signal, and obtains a difference signal between the odd field integrated signal and the even field integrated signal, According to the magnitude of the difference signal with respect to the common voltage, it is effective to add and subtract the difference signal to and from the common voltage and supply the difference signal to the common electrode of the transistor.

According to a tenth aspect of the present invention, the voltage adjusting means uses an adder circuit to generate each added signal in accordance with a change in the odd field and the even field of the video input signal. A difference signal between the odd field addition signal and the even field addition signal is obtained, and the difference signal is added and superimposed or subtracted and superimposed on the common voltage according to the magnitude of the difference signal with respect to the common voltage, and the difference signal is added to the common electrode of the transistor. Supply is effective.

Further, as in the invention described in claim 11, an operational amplifier can be used for the adder circuit.

According to the first aspect of the present invention, a plurality of signal lines and a plurality of scanning lines are arranged in a matrix form, and a transistor is provided at each intersection of these signal lines and scanning lines to an electrode on one side of the pixel. A common voltage is supplied to the common electrode of the other pixel to scan each scanning line at a scanning timing according to the video input signal, and the video input signal input to each signal line is supplied to the common electrode. In a driving method of an active matrix LCD, in which image signals are accumulated and displayed in each pixel electrode by alternating-currently driving each transistor while inverting the polarity of a positive and negative video signal with respect to a voltage every predetermined period. , The pole side having a larger effective value voltage of the video input signal relative to the common voltage depending on the magnitude of the voltage change or the signal amount of the video input signal input to each of the signal lines. The conversion signal is reduced by a fixed amount and the pole side having a small effective value voltage is increased by a predetermined amount to generate a converted signal adjusted by the voltage adjusting means so that the positive effective value voltage and the negative effective value voltage are equalized. Are supplied to the common electrode of the pixel.

Therefore, the conversion signal according to the change of the image input signal can be supplied to the common electrode of the transistor, and the DC imbalance of the pixel electrode connected to the common electrode can be made extremely small. Such DC imbalance can be made extremely small. As a result, deterioration of the active matrix LCD can be suppressed and reliability can be improved. Further, it is possible to reduce the deviation of the gradation due to the DC imbalance, and it is possible to improve the image quality of the active matrix LCD.

According to the second aspect of the invention, the voltage adjusting means phase-inverts the video input signal in either the odd field or the even field, and the other side in the same frame as the phase-inverted video input signal. By integrating each of the image input signals of the field of 1) using an integrating circuit and supplying the integrated signal to the common electrode of the transistor, and according to the invention of claim 3, the voltage adjusting means uses a low-pass filter. By supplying a low frequency component of the video input signal to the common electrode of the transistor, and according to the invention of claim 4, the voltage adjusting means uses a rectangular wave generation circuit to generate the video input signal. Is supplied to the common electrode of the transistor, and according to the invention of claim 5, the voltage adjustment is performed. The means supplies a triangular wave signal according to the change of the video input signal to the common electrode of the transistor by using a triangular wave generating circuit, and according to the invention of claim 6, the voltage adjusting means comprises: By supplying a sawtooth wave signal corresponding to the change of the video input signal to the common electrode of the transistor using a sawtooth wave generation circuit, D generated at the pixel electrode according to the change of the video input signal is generated.
A conversion signal that cancels the C component can be supplied to the common electrode of the transistor, the DC imbalance of the pixel electrode can be made extremely small, and the active matrix L
The DC imbalance across the entire CD can be made extremely small.

According to the seventh aspect of the invention, the voltage adjusting means superimposes the converted signal and the predetermined voltage by using an adder circuit and supplies the superposed signal to the common electrode of the transistor. It is possible to superimpose a conversion signal according to a change in the image input signal on the DC voltage and apply the superimposed signal to the pixel electrode connected to the common electrode, thereby removing the DC imbalance of the pixel electrode.

According to the eighth aspect of the invention, the voltage adjusting means uses an integrating circuit to generate an integrated signal according to a change in the video input signal, and depending on the magnitude of the integrated signal with respect to the common voltage. Then, the integrated signal is added and superposed or subtracted and superposed on the common voltage and supplied to the common electrode of the transistor, so that the integrated signal according to the change of the video input signal is added and superposed on the common voltage and shared. Can be applied to the pixel electrode connected to the electrode,
DC imbalance of the pixel electrode can be removed.

According to a ninth aspect of the invention, the voltage adjusting means uses an integrator circuit to generate respective integrated signals in accordance with changes in the odd field and the even field of the video input signal, and the odd field integration is performed. A differential signal between the signal and the even-field integrated signal is obtained, and the differential signal is added and superimposed or subtracted and superimposed on the common voltage according to the magnitude of the differential signal with respect to the common voltage and is supplied to the common electrode of the transistor. According to the tenth aspect of the invention, the voltage adjusting means uses an adder circuit to generate each addition signal according to a change in the odd field and the even field of the video input signal. A difference signal between the addition signal and the even field addition signal is obtained, and the common voltage is set to the common voltage according to the magnitude of the difference signal with respect to the common voltage. By supplying the difference signal to the common electrode of the transistor by adding and superimposing or subtracting and superimposing the difference signal, the integrated signal according to the change of the video input signal of the odd field and the even field is added and superimposed or subtracted and superposed on the common voltage to be common. It can be applied to the pixel electrode connected to the electrode, and DC imbalance of the pixel electrode can be removed.

According to the eleventh aspect of the present invention, the adder circuit can use an operational amplifier, and the adder circuit can be realized at low cost.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. (First Embodiment) FIGS. 1 to 4 are views showing a first embodiment of an active matrix LCD to which an active matrix LCD driving method of the present invention is applied. First, the configuration will be described. FIG. 1 is a diagram showing a circuit configuration for one pixel of the active matrix LCD of the first embodiment, and the same reference numerals are given to the same components as the circuit configuration shown in FIG. 9 of the related art. are doing.

In FIG. 1, the voltage adjusting means 10 branched and connected from the signal line 2 is composed of a data signal adjusting circuit 11, a low-pass filter 12 and an adder 13. The data signal adjusting circuit 11 includes the signal line 2
It is a circuit for inverting the phase of the even field so as to match the phases of the odd field and the even field of the video signal input to the low-pass filter 12.

The low-pass filter 12 outputs the phase-inverted video signal input from the data signal adjusting circuit 11 to the adder 12 as an integrated voltage signal of a low frequency component having a scanning frequency, a frame frequency or a cutoff frequency. Circuit. The adder 13 is D in the figure.
In this circuit, the DC voltage Vc output from the C power supply 7 is superimposed on the integrated voltage signal of the low frequency component input from the low pass filter 13 and applied to the pixel electrode 4 connected to the common electrode C of the TFT 3.

Further, the TFT 3 shown in FIG.
The type shall be used. Therefore, in the circuit configuration of the first embodiment, since the voltage adjusting means 10 is connected, the voltage signal obtained by averaging the input video signal is superimposed on the DC voltage Vc and applied to the common electrode C of the TFT 3. It will be.

Next, the operation of the first embodiment will be described. First, regarding the operation in the circuit of FIG. 1, a video signal VIDA (a video signal a synchronized with an odd field and a video signal b synchronized with an even field) which changes into a binary value is supplied to the signal line 2 shown in FIG. A description will be given with reference to the waveform diagram when applied.

In FIG. 2A, when the video signal VIDA input to the signal line 2 is applied to the source electrode S of the TFT 3 at the ON timing of the scan signal VG input to the scan line 1, the video signal With respect to the signal VIDA, the video signal synchronized with the odd field is phase-inverted by the data signal adjustment circuit 11, and the video signal synchronized with the even field is output to the low-pass filter 12 while keeping the same phase. As shown in b), the integrated voltage signal c of the low frequency component for each field,
It is converted to c ′ and output to the adder 13.

At this time, the integrated voltage signal c of the odd field
The relationship between the even field integrated voltage signal c ′ is basically c = c ′, but there may be a case where c ≠ c ′ depending on the magnitude of the voltage of the input video signal or the amount of the signal. .

Then, the integrated voltage signals c and c'are the DC voltage Vc output from the DC voltage 7 by the adder 13.
And is applied to the pixel electrode 4 connected to the common electrode C of the TFT 3. The correction amount by the integrated voltage signals c and c'superposed on the DC voltage Vc is added to the video signal a synchronized with the odd field and synchronized with the even field, as shown in FIG. 2C. Subtraction is performed on the video signal b.

That is, the correction voltages c, c applied to the common electrode C in the even field and the odd field.
The relation of 'can be expressed by the following equations (2) and (3). In the odd field, a-(-c) = a + c ... (2) In the even field, -b-(-c ') =-b + c' ... (3) That is, since c = c ', the odd field And the integrated voltage signals c and c'can be superposed as values for canceling the DC components of the even fields, and the result of the superposition is a + c.
≈−b + c ′.

Therefore, the DC applied to the pixel electrode 4
By superimposing the correction voltages c and c'generated by converting the input video signal VIDA that changes into the binary value shown in FIG. 2A on the voltage Vc, the DC imbalance in one frame is canceled, DC unbalance within one frame can be made extremely small, and active matrix LCD
The DC unbalance applied to the whole can be made extremely small.

Next, the operation when the binary video signal VIDA shown in FIG. 3 is applied to the signal line 2 of FIG. 1 will be described. In FIG. 3, when the video signal VIDA input to the signal line 2 is applied to the source electrode S of the TFT 3 at the ON timing of the scan signal VG input to the scan line 1, the video signal VIDA is adjusted by the data adjustment. The circuit 11 phase-inverts the video signal VIDA synchronized with the odd field and outputs the video signal VIDA synchronized with the even field to the low-pass filter 12 in the same phase. The even-field and odd-field video signals VIDA are converted into low-frequency component integrated voltage signals by the low-pass filter 12 and output to the adder 13, and the integrated signals are output from the DC power supply 7 by the adder 13. Is superimposed on the DC voltage Vc generated by the TFT 3
To the pixel electrode 4 connected to the common electrode C of
applied as p.

The correction amount by the integrated voltage signal superimposed on the DC voltage Vc is a jump which occurs in the odd field and the even field due to the change of the applied video signal VIDA, as indicated by "e" in FIG. It is superimposed on the DC voltage Vc corresponding to the change in the voltage ΔV.

The relationship between the correction voltage e applied to the common electrode C in the odd field and the even field can be expressed by the following equations (4) and (5).

In the odd field, Vp − (− e) = Vp + e ... (4) In the even field, −Vp − (− e) = − Vp + e ... (5) That is, the correction voltage e is a video synchronized with the odd field. Since it is added to the signal V IDA and subtracted from the video signal V IDA that is synchronized with the even field, it is used as a value for canceling the DC components of the odd field and the even field by the following formula (6) and the effective of one frame. The offset voltage can be obtained.

(Vp + e) + (− Vp + e) = 2e (6) As a result, the effective voltage of the odd field can be approximately equal to the effective voltage of the even field. Therefore, the correction voltage e generated by converting the input video signal VIDA that changes into the binary value shown in FIG. 3 into the DC voltage Vc applied to the pixel electrode 4 is generated.
The DC imbalance within one frame can be canceled out by superimposing the above, and the DC imbalance within one frame can be made extremely small, and the DC imbalance applied to the entire active matrix LCD can be made extremely small. .

The operation of the circuit shown in FIG. 1 will be described when the video signal VIDB shown in FIG. 4 is applied to the signal line 2 shown in FIG. In FIG. 4, when the video signal VIDB input to the signal line 2 is applied to the source electrode S of the TFT 3 at the ON timing of the scan signal VG input to the scan line 1, the video signal VIDB is data adjusted. The circuit 11 phase-inverts the video signal VIDB synchronized with the odd field and the low-pass filter 1 with the video signal VIDA synchronized with the even field being in phase.
2 is output. Then, the even-field and odd-field video signals VIDB are converted by the low-pass filter 12 into integrated voltage signals of low-frequency components and output to the adder 13, and the integrated signals are output from the DC power supply 7 by the adder 13. Superposed on the DC voltage Vc
The pixel electrode potential Vp ′ is applied to the pixel electrode 4 connected to the common electrode C of the TFT 3.

The correction amount by the integrated voltage signal superimposed on the DC voltage Vc corresponds to the change of the video signal VIDB applied in the odd field and the even field, as indicated by "e '" in FIG. It is superimposed on the DC voltage Vc and changes in the even field and the odd field.
The correction voltage e'is superimposed so as to correct the DC component due to the jump voltage .DELTA.V '.

Therefore, the DC applied to the pixel electrode 4
The input video signal V that changes into the voltage Vc into the multi-value shown in FIG.
By superimposing the correction voltage e'generated by converting the IDB by the voltage adjusting means 10, the DC imbalance between the odd field and the even field is canceled, and the DC imbalance in one frame is made extremely small. DC that can be applied to the entire active matrix LCD
The imbalance can be made extremely small.

As a result, an active matrix LCD
Can be suppressed and the reliability can be improved. Further, it is possible to reduce the deviation of the gradation due to the DC imbalance, and it is possible to improve the image quality of the active matrix LCD.

(Second Embodiment) FIGS. 5 to 8 are views showing a second embodiment of an active matrix LCD to which the driving method of the active matrix LCD of the present invention is applied. FIG. 5 shows the TFT 3 of the second embodiment.
FIG. 3 is a diagram showing a configuration of a voltage adjusting means 10 connected to a circuit for one pixel of an active matrix LCD using an NMOS type, and has the same configuration as the circuit configuration shown in FIG. 1 of the first embodiment. The same reference numerals are given to the parts, and the description of the configuration will be omitted.

In FIG. 5, the voltage adjusting means 10 branched and connected from the signal line 2 is composed of a data signal adjusting circuit 11, a low-pass filter 12 and an adder 13. The data signal adjustment circuit 11 is composed of an odd field video synchronization signal phase inversion circuit 11a and an even field video signal synchronization circuit 11b. The odd-field video synchronization signal phase inverting circuit 11a is a circuit that inverts the phase of the video signal synchronized with the odd field input to the signal line 2 and outputs it to the low-pass filter 12, and the even-field video synchronization circuit 11b is
This is a circuit that outputs a video signal, which is input to the signal line 2 and synchronized with an even field, to the low-pass filter 12 in the same phase.

When the TFT 3 is of the NMOS type, the integrated signal superimposed on the common voltage Vc by the low pass filter 12 and the adder 13 has the phases of both the odd field and the even field of the video signal, as shown in FIG. It must be on the negative side with respect to the common voltage Vc.

For this reason, the video signal synchronized with the odd field is supplied to the odd field video sync signal phase inverting circuit 11.
The video signal synchronized with the even field is already phase-inverted because it is AC-driven and the video signal synchronized with the even field video signal synchronizing circuit 11b outputs the video signal synchronized as it is. Output to the low pass filter 12.

The adder 13 adds the in-phase integrated signal for both the odd field and the even field input from the low-pass filter 12 and the DC voltage Vc output from the DC power supply 7 to add the common electrode of the TFT 3 to each other. Output to C. If the TFT 3 is a PMOS type, FIG.
The voltage adjusting means 10 having the configuration shown in is used. The data adjusting circuit 21 of the voltage adjusting means 10 is composed of an odd field video signal synchronizing circuit 21a and an even field video synchronizing signal phase inverting circuit 21b.

Odd field video signal synchronizing circuit 21a
Is a circuit for outputting a video signal synchronized with an odd field input to the signal line 2 to the low-pass filter 12 in the same phase, and an even field video synchronization signal phase inversion circuit 21b is an even field input to the signal line 2. Low-pass filter 1 by inverting the phase of the video signal synchronized with
It is a circuit that outputs to 2.

When the TFT 3 is a PMOS type, the integrated signal superposed on the common voltage Vc by the low pass filter 12 and the adder 13 has the phases of both the odd field and the even field of the video signal as shown in FIG. It needs to be on the positive side with respect to the common voltage Vc.

Therefore, the odd-field video signal synchronizing circuit 21a outputs the video signal synchronized with the odd-numbered field to the low-pass filter 12 while keeping the same phase.
Since the video signal synchronized with the even field is on the negative side with respect to the common voltage Vc, the even field video synchronization signal phase inverting circuit 21b inverts the phase and outputs the inverted signal to the low-pass filter 12.

Then, in the adder 13, the integrated signal that is in-phase for both the odd field and the even field that is input from the low pass filter 12 and the DC voltage Vc that is output from the DC power supply 7 are added, and the common electrode of the TFT 3 is added. Output to C.

Therefore, the DC applied to the pixel electrode 4
DC is applied between the odd and even fields by superimposing the integrated signal generated by converting the odd field and the even field of the input video signal in phase with the voltage Vc.
By canceling the imbalance, the DC imbalance within one frame can be made extremely small, and the DC imbalance applied to the entire active matrix LCD can be made extremely small.

As a result, the active matrix LCD
Can be suppressed and the reliability can be improved. Further, it is possible to reduce the deviation of the gradation due to the DC imbalance, and it is possible to improve the image quality of the active matrix LCD.

The low-pass filter 12 used in each of the above embodiments is an integrating circuit for integrating a video signal,
Alternatively, a rectangular wave generation circuit that generates a rectangular wave signal according to a change in a video signal, a triangular wave generation circuit that generates a triangular wave signal according to a change in a video signal, or a sawtooth wave signal according to a change in a video signal It may be a sawtooth wave generation circuit.

7 and 8 show examples of waveform patterns of the correction voltage e superimposed by the adder 12 when the integrating circuit, the triangular wave generating circuit, the rectangular wave generating circuit or the sawtooth wave generating circuit is used. . FIG. 7 shows an integrating circuit, a triangular wave generating circuit or a rectangular wave generating circuit and the adder 13 when the NMOS type is used for the TFT 3 as in the above embodiment.
5A to 5C are diagrams showing waveform patterns of the correction voltage e superimposed on the DC voltage Vc by the DC voltage Vc in this case.
Is superimposed on the negative side.

Further, FIG. 8 shows that when the PMOS type is used for the TFT 3, the integrating circuit, the sawtooth wave generating circuit, the rectangular wave generating circuit or the triangular wave generating circuit and the adder 13 cause the DC voltage.
Waveform pattern of the correction voltage e superimposed on the voltage Vc
FIG. 4 is a diagram showing the above, and in this case, the DC voltage Vc is superimposed on the positive side.

As described above, even when the integrating circuit, the triangular wave generating circuit, the rectangular wave generating circuit or the sawtooth wave generating circuit is used as the circuit for superimposing the correction voltage e, the DC component can be canceled, and the same applies. The effect of can be obtained. Moreover, the adder 13 can be configured by an operational amplifier, and the adder can be realized at low cost.

Further, the DC correction voltages e to DC shown in FIGS. 7 and 8 which are generated by using an integrating circuit, a triangular wave generating circuit, a rectangular wave generating circuit or a sawtooth wave generating circuit are used.
If the component can be cut, the DC voltage Vc is added by the adder 13.
It is also possible to directly apply the DC correction voltage e to the pixel electrode 4 without superimposing it on the pixel electrode 4. In this case, adder 1
Since 3 can be omitted, the circuit for removing the DC component of the present invention can be realized at a lower cost.

(Third Embodiment) FIGS. 9 to 11 are views showing a third embodiment of an active matrix LCD to which the driving method of the active matrix LCD of the present invention is applied. First, the configuration will be described. FIG. 9 is a diagram showing a circuit configuration for one pixel of the active matrix LCD of the third embodiment, and the same components as the circuit configuration shown in FIG. are doing.

In FIG. 9, the voltage adjusting means 30 branched from the signal line 2 is connected to the 1Hor1F delay circuit 3.
01, 1Hor1F integrating circuit 302, an adding circuit 303, a subtracting circuit 304, a selector 305, an AC converting circuit 306, and a common electrode voltage source 307. 1 Hor1
The F delay circuit 301 is a circuit that delays the analog video signal 300 input to the signal line 2 by one scanning period (1H) or one field period (1F) and outputs the delayed signal to the AC conversion circuit 306.

The 1Hor1F integration circuit 302 integrates the analog video signal 300 input to the signal line 2 in synchronization with one scanning period (1H) or one field period (1F), and the adding circuit 303 and the subtracting circuit 304. It is a circuit that outputs to. The adding circuit 303 is a 1Hor1F integrating circuit 3
The integrated value of the analog video signal that is input by being integrated in synchronization with 1H or 1F by 02 is input to the common electrode voltage source 3
07 is added to the common electrode applied voltage Vc,
This is a circuit for outputting to the selector 305.

The subtraction circuit 304 is a 1Hor1F integration circuit 3
The integrated value of the analog video signal that is input by being integrated in synchronization with 1H or 1F by 02 is input to the common electrode voltage source 3
It is a circuit that subtracts from the common electrode applied voltage Vc input from 07 and outputs it to the selector 305.

The selector 305, in synchronization with the alternating operation of the alternating circuit 306, selectively selects one of the outputs of the adding circuit 303 and the subtracting circuit 304 depending on whether the analog video signal 300 is positive or negative, This is a circuit for applying to the pixel electrode 4 connected to the common electrode C of the TFT 3. That is,
When the analog video signal 300 is positive, the selector 305 selects a voltage obtained by adding and superimposing the integrated value of the analog video signal to the common electrode applied voltage Vc by the adder circuit 303 and connected to the common electrode C of the TFT 3. When the analog video signal 300 is applied to the pixel electrode 4 and is negative, the subtraction circuit 304 selects a voltage obtained by subtracting and superimposing the integrated value of the analog video signal on the common electrode applied voltage Vc to select the TFT.
3 to the pixel electrode 4 connected to the common electrode C.

The alternating circuit 306 receives 1Hor1F by an inversion control signal input from an external control circuit (not shown).
It is a circuit for converting the analog video signal 300 delayed by 1H or 1F by the delay circuit 301 into an alternating current to generate a polarity inversion signal and outputting it to the drain driver 100.

The drain driver 100 includes the AC circuit 3
A circuit for selecting a liquid crystal drive voltage by the polarity inversion signal input from 06 and supplying it to the source electrode S of the TFT 3. The common electrode voltage source 307 is an output variable power source capable of changing the setting of the common electrode applied voltage Vc, which is the output voltage thereof, and has a value that allows for the average value of the voltage ΔV applied to the pixel electrode 4 by the analog video signal 300. Set it. By doing so, no DC component remains in the entire display area.

Further, the TFT 3 shown in FIG.
The type shall be used. Therefore, in the circuit configuration according to the third embodiment, the voltage signal obtained by averaging the input analog video signal 300 is superimposed on the common electrode applied voltage voltage Vc by connecting the voltage adjusting means 30, so that the common electrode of the TFT 3 is connected. Will be applied to C.

Next, the operation of the third embodiment will be described. First, the operation in the circuit of FIG. 9 will be described when the source signal (video signal) shown in FIG. 10 is applied to the signal line 2 of FIG. In FIG. 10, the source signal input to the signal line 2 is the source electrode S of the TFT 3 at the ON timing of the scanning signal input to the scanning line 1.
When applied to the AC signal, the 1Hor1F delay circuit 301 delays the source signal synchronized with the odd field and outputs it to the AC conversion circuit 306.
The 1F integration circuit 302 integrates the source signal synchronized with the odd field.

In the alternating circuit 306, an inversion control signal input from an external control circuit (not shown) causes
When the 1H or 1F analog video signal 300 delayed by the 1Hor1F delay circuit 301 is AC-converted to generate a polarity inversion signal, the drain driver 100 selects the liquid crystal drive voltage by the polarity inversion signal, It is supplied to the source electrode S of the TFT 3.

Further, the adding circuit 303 and the subtracting circuit 304
Then, when the integrated value of the source signal is added to or superposed on the common electrode applied voltage Vc supplied from the common electrode voltage source 307 and output to the selector 305, when the analog video signal 300 is positive, the selector 305 , The adder circuit 303 selects the added and superimposed voltage,
Applied to the pixel electrode 4 connected to the common electrode C of T3,
When the analog video signal 300 is negative, the subtraction circuit 3
The voltage that is subtracted and superimposed is selected by 04, and the TFT 3
Is applied to the pixel electrode 4 connected to the common electrode C.

Therefore, as shown in FIG. 10, the common electrode applied voltage Vc applied to the pixel electrode 4 in the odd field and the even field depends on whether the analog video signal 300 is positive or negative with respect to the common electrode applied voltage Vc. Is adjusted by adding or subtracting the integral value of the analog video signal 300 to the common electrode applied voltage Vc, and the difference A, A'between the liquid crystal effective voltage and the common voltage in each of the odd and even fields becomes substantially the same voltage value. Controlled.

Also, with respect to the change of the source signal shown in FIG. 11, the operation of the voltage adjusting means 30 causes the common electrode application applied to the pixel electrode 4 in the odd field and the even field as shown in the figure. Depending on whether the analog video signal 300 is positive or negative with respect to the voltage Vc, the analog video signal 3
The integrated value of 00 is adjusted by adding or subtracting it to the common electrode applied voltage Vc, and the difference B, B ′ between the liquid crystal effective voltage and the common voltage in each of the odd and even fields is controlled to be substantially the same voltage value. It

As a result, when an analog video signal is input, the DC imbalance between the odd field and the even field can be canceled out, and the DC imbalance within one frame can be made extremely small. The DC unbalance applied to the whole can be made extremely small.

Therefore, the active matrix LC
The deterioration of D can be suppressed and the reliability can be improved. Further, it is possible to reduce the deviation of the gradation due to the DC imbalance, and it is possible to improve the image quality of the active matrix LCD.

(Fourth Embodiment) In the third embodiment, the input video signal is an analog video signal, but the input video signal is a digital video signal. FIG. 12 shows the configuration of the voltage adjusting means. This FIG. 12 shows the TFT 3 of the fourth embodiment with N
FIG. 11 is a diagram showing a configuration of a voltage adjusting means 40 connected to a circuit for one pixel of an active matrix LCD using a MOS type, and the same configuration part as the circuit configuration shown in FIG. 9 of the third embodiment. Are denoted by the same reference numerals, and the description of the configuration will be omitted.

In FIG. 12, the voltage adjusting means 40 branched and connected from the signal line 2 is composed of a 1Hor1F storage circuit 401, an AC control circuit 402, a DAC 403, an integrator 404, a DAC 405 and an amplifier 406. . The 1Hor1F storage circuit 401 receives the digital video signal 400 input to the signal line 2 for one scanning period (1H).
Minute or one field period (1F) is stored and output to the AC control circuit 402.

The AC control circuit 402 receives 1H by an inversion control signal input from an external control circuit (not shown).
1H or 1 stored by the 1F storage circuit 401
It is a circuit for converting the digital video signal 400 for F into an alternating current to generate a polarity inversion signal and outputting it to the DAC 403. D
The AC 403 is a circuit that converts the polarity inversion signal input from the AC control circuit 402 into a predetermined analog polarity inversion signal and outputs the analog polarity inversion signal to the drain driver 100.

The accumulator 404 is a circuit for accumulating and averaging the digital video signal 400 input to the signal line 2 for one scanning period (1H) or one field period (1F) and outputting it to the DAC 405. Is.

The DAC 405 uses the accumulator 404 for 1H.
Minute or 1F averaged digital video signal 400
Is a circuit that performs digital-analog conversion processing in synchronism with the alternating current operation by the polarity inversion signal and outputs the average value to the amplifier 406. That is, when the average value input from the integrator 404 is positive with respect to the preset common electrode voltage, the DAC 405 adds the average value to the common electrode voltage to obtain a predetermined analog voltage signal. When the average value is negative, the average value is subtracted from the common electrode voltage to convert it into a predetermined analog voltage signal, which is output to the amplifier 406.

The amplifier 406 is a circuit that amplifies the analog voltage signal input from the DAC 405 with a predetermined amplification factor and applies it as the common electrode voltage Vc to the pixel electrode 4 connected to the common electrode C of the TFT 3. The average value of the digital video signal 400 integrated by the integrator 404 is positive with respect to the preset common electrode voltage in synchronization with the AC conversion of the video signal applied to the TFT-LCD in the DAC 405. When the pixel electrode 4 is added, and when it is negative, the pixel electrode 4 is subtracted as the common electrode voltage Vc by the amplifier 406.
Is applied to

At this time, the initial value of the DAC 406 is set so that the common electrode voltage Vc is set to a value that allows for the average value of the ΔV. Therefore, in the circuit configuration of the fourth embodiment, the voltage signal obtained by averaging the input digital video signal 400 is superimposed on the common electrode applied voltage voltage Vc by connecting the voltage adjusting means 40, and the common electrode of the TFT 3 Will be applied to C.

Next, the operation of the fourth embodiment will be described. The operation in the circuit of FIG. 12 will be described. This Figure 1
2, the digital video signal 400 input to the signal line 2
When the scanning signal input to the scanning line 1 is applied to the source electrode S of the TFT 3 at the ON timing, the digital video signal 400 is generated by the 1Hor1F storage circuit 401.
Digital video signal 400 synchronized with the odd field
Is stored once, then output to the AC control circuit 402, and the digital video signal 400 is integrated and averaged by the integrator 404 in synchronization with the odd field.

In the AC control circuit 402, the digital video signal 400 for 1H or 1F stored in the 1Hor1F storage circuit 401 is converted into an AC signal by an inversion control signal input from an external control circuit (not shown). A polarity inversion signal is generated and output to the DAC 403. In the DAC 403, the polarity inversion signal input from the alternating current control circuit 402 is converted into a predetermined analog polarity inversion signal and output to the drain driver 100. In the drain driver 100, the polarity inversion signal input from the alternating current control circuit 402 is inverted. The liquid crystal drive voltage is selected by the signal and supplied to the source electrode S of the TFT 3.

Further, in the DAC 405, the D / A conversion process is performed in synchronization with the alternating current operation of the alternating current control circuit 402, and the initial value preset in consideration of the average value of the common electrode voltage ΔV is compared with the initial value. When the average value input from the integrator 404 is positive, the average value is added to the common electrode voltage and converted into a predetermined analog voltage signal. When the average value is negative,
The average value is subtracted from the common electrode voltage to be converted into a predetermined analog voltage signal, which is output to the amplifier 406. Then, in the amplifier 406, the analog voltage signal input from the DAC 405 is amplified by a predetermined amplification factor and applied as the common electrode voltage Vc to the pixel electrode 4 connected to the common electrode C of the TFT 3.

Therefore, the common electrode applied voltage Vc applied to the pixel electrode 4 in the odd field and the even field
However, depending on whether the digital video signal 400 is positive or negative with respect to the common electrode voltage, the average value of the digital video signal 400 is adjusted by being added or subtracted from the common electrode voltage and adjusted, and the liquid crystal effective in each of the odd and even fields is adjusted. The difference between the voltage and the common voltage is controlled to almost the same voltage value. As a result, when a digital video signal is input, the DC imbalance between the odd field and the even field can be canceled out, and the DC imbalance within one frame can be made extremely small, which affects the entire active matrix LCD. The DC imbalance can be made extremely small.

Therefore, the active matrix LC
The deterioration of D can be suppressed and the reliability can be improved. Further, it is possible to reduce the deviation of the gradation due to the DC imbalance, and it is possible to improve the image quality of the active matrix LCD.

(Fifth Embodiment) FIGS. 13 to 16 show
It is a figure which shows 5th Embodiment of the active matrix LCD which applied the drive method of the active matrix LCD of this invention. First, the configuration will be described. FIG.
FIG. 23 is a diagram showing a circuit configuration of one pixel of the active matrix LCD of the fifth embodiment, which is the same as the conventional FIG.
The same reference numerals are given to the same components as those shown in FIG.

In FIG. 13, the voltage adjusting means 50 branched from the signal line 2 is connected to the low-pass filter 5.
1, an adder 52 and a common electrode voltage source (Vc) 53. The detailed configuration of the voltage adjusting means 50 is as follows.
As shown in FIG. 14, the low-pass filter 51 portion includes integrators 51a and 51b and a subtractor 51c.

The low-pass filter 51 integrates the analog video signal 9 input to the signal line 2 by the integrators 51a and 51b for each of the analog video signal 9 of the odd line and the analog video signal 9 of the even line. The subtractor 51c subtracts the odd line integration result and the even line integration result, and outputs the subtraction result to the adder 52.

The adder 52 adds the subtraction result of the odd line analog video signal 9 and the even line analog video signal 9 inputted from the low-pass filter 51 to the common electrode voltage source (Vc) 53 to make the TFT 3 common. It is applied to the pixel electrode 4 connected to the electrode C. In addition, the TF shown in FIG.
An NMOS type is used for T3. Therefore, in the circuit configuration of the fifth embodiment, since the voltage adjusting means 50 is connected, the voltage signal obtained by averaging the input analog video signal 9 is superimposed on the common electrode applied voltage voltage Vc so that the common electrode of the TFT 3 can be formed. Will be applied to C.

Next, the operation of the fifth embodiment will be described. First, the operation in the circuit of FIG. 13 will be described when the source signal (analog video signal) shown in FIG. 15 is applied to the signal line 2 of FIG. This Figure 1
In 5, the source signal input to the signal line 2 is the scan line 1
When applied to the source electrode S of the TFT 3 at the ON timing of the scanning signal input to the low-pass filter 51, the source signal is applied to the odd-numbered field integrator 51a and the even-numbered line integrator 51b. After each source signal synchronized with the even field is integrated, each integration result is subjected to subtraction processing by the subtractor 51c to calculate the difference between the source signals of the odd field and the even field.

Then, in the adder 52, the difference between the subtracted source signals of the odd field and the even field is added to the common electrode voltage source (Vc) 53 to generate TF.
It is applied to the pixel electrode 4 connected to the common electrode C of T3. Therefore, as shown in FIG. 15, the common electrode applied voltage Vc applied to the pixel electrode 4 in the odd field and the even field depends on whether the analog video signal 9 is positive or negative with respect to the common electrode applied voltage Vc. The integrated value of the analog video signal 9 is added to or subtracted from the applied voltage Vc to adjust it, and the difference A, A'between the liquid crystal effective voltage and the common voltage in each of the odd and even fields is controlled to be substantially the same voltage value. .

Also, with respect to the change of the source signal shown in FIG. 16, the operation of the voltage adjusting means 50 causes the common electrode application applied to the pixel electrode 4 in the odd field and the even field as shown in the figure. Depending on whether the analog video signal 9 is positive or negative with respect to the voltage Vc, the integrated value of the analog video signal 9 is added to or subtracted from the common electrode applied voltage Vc to be adjusted, and the liquid crystal in each of the odd and even fields is adjusted. The differences B and B'between the effective voltage and the common voltage are controlled to substantially the same voltage value. As a result, when an analog video signal is input, D between the odd field and the even field
By canceling the C imbalance, the DC imbalance within one frame can be made extremely small, and the DC imbalance applied to the entire active matrix LCD can be made extremely small.

Therefore, the active matrix LC
The deterioration of D can be suppressed and the reliability can be improved. Further, it is possible to reduce the deviation of the gradation due to the DC imbalance, and it is possible to improve the image quality of the active matrix LCD.

(Sixth Embodiment) FIGS. 17 to 20 show
It is a figure which shows 6th Embodiment of the active matrix LCD which applied the drive method of the active matrix LCD of this invention. First, the configuration will be described. Figure 17
FIG. 21 is a diagram showing a circuit configuration for one pixel of the active matrix LCD of the sixth embodiment, which is the same as that of the conventional FIG.
The same reference numerals are given to the same components as those shown in FIG. In FIG. 17, the voltage adjusting means 60 branched and connected from the signal line 2 is the low-pass filter 6
1, an adder 62 and a common electrode voltage source (Vc) 63. The detailed configuration of the voltage adjusting means 60 is as follows.
As shown in FIG. 18, the low-pass filter 61 part includes adders 61a and 51b, a subtractor 61c, and an AD converter 61.
d, DAC 61e.

The low-pass filter 61 performs addition processing on the digital video signal 9 input to the signal line 2 by the adders 61a and 61b for each of the odd-line digital video signal 9 and the even-line digital video signal 9. The subtractor 61c subtracts the odd line addition result and the even line addition result, and outputs the subtraction result to the DAC 61e.

The AD converter 61d performs analog-digital conversion processing on the initial common voltage input from the outside, and outputs it to the DAC 61e as a predetermined initial common digital voltage signal.

The DAC 61e receives the odd common line digital video signal 9 input from the subtractor 61c with respect to the initial common digital voltage signal input from the AD converter 61d.
When the difference value between the even line digital video signal 9 and the even line digital video signal 9 is positive, the difference value is added to the common electrode voltage to convert it into a predetermined analog voltage signal, and when the difference value is negative, the difference is added to the common electrode voltage. The value is subtracted, converted into a predetermined analog voltage signal, and output to the adder 62.

The adder 62 supplies the common electrode voltage source with the analog voltage signal in which the difference value between the odd line digital video signal 9 and the even line digital video signal 9 input from the low pass filter 61 is added and superposed. (Vc)
It is added to 63 and applied to the pixel electrode 4 connected to the common electrode C of the TFT 3.

The TFT 3 shown in FIG. 17 has an NMO.
S type shall be used. Therefore, in the circuit configuration of the sixth embodiment, since the voltage adjusting means 60 is connected, the voltage signal obtained by averaging the input digital video signal 9 is superimposed on the common electrode applied voltage voltage Vc, and the common electrode of the TFT 3 is formed. Will be applied to C.

Next, the operation of the sixth embodiment will be described. First, the operation in the circuit of FIG. 17 will be described when the source signal (digital video signal) shown in FIG. 19 is applied to the signal line 2 of FIG.

In FIG. 19, when the source signal input to the signal line 2 is applied to the source electrode S of the TFT 3 at the ON timing of the scanning signal input to the scanning line 1, the source signal is a low pass filter. After the source signals synchronized with the odd field and the even field are added by the adder 61a for odd lines and the adder 61b for even lines in 61, the respective addition results are subtracted by the subtracter 61c.
Is subtracted to calculate the difference between the source signals of the odd and even fields.

In the DAC 61e, the difference between the odd line digital video signal 9 and the even line digital video signal 9 input from the subtractor 61c is different from the initial common digital voltage signal input from the A / D converter 61d. When the value is positive, the difference value is added to the common electrode voltage and converted into a predetermined analog voltage signal, and when the difference value is negative,
The difference value is subtracted from the common electrode voltage, converted into a predetermined analog voltage signal, and output to the adder 62.

In the adder 62, the analog voltage signal in which the difference value between the odd line digital video signal 9 and the even line digital video signal 9 is added and superposed or subtracted and superposed is added to the common electrode voltage source (Vc) 63. And is applied to the pixel electrode 4 connected to the common electrode C of the TFT 3.

Therefore, as shown in FIG. 19, the common electrode applied voltage Vc applied to the pixel electrode 4 in the odd field and the even field depends on whether the digital video signal 9 is positive or negative with respect to the common electrode applied voltage Vc. The added value of the digital video signal 9 is added to or subtracted from the common electrode applied voltage Vc for adjustment, and the difference A, A'between the liquid crystal effective voltage and the common voltage in each of the odd and even fields becomes almost the same voltage value. Controlled.

Further, in response to the change of the source signal shown in FIG. 20, the operation of the voltage adjusting means 60 causes the common electrode application applied to the pixel electrode 4 in the odd field and the even field as shown in the figure. Depending on whether the digital video signal 9 is positive or negative with respect to the voltage Vc, the added value of the digital video signal 9 is added to or subtracted from the common electrode applied voltage Vc to be adjusted, and the liquid crystal in each of the odd and even fields is adjusted. The differences B and B'between the effective voltage and the common voltage are controlled to substantially the same voltage value.

As a result, when a digital video signal is input, the DC imbalance between the odd field and the even field can be canceled out, and the DC imbalance within one frame can be made extremely small. The DC unbalance applied to the whole can be made extremely small.

Therefore, the active matrix LC
The deterioration of D can be suppressed and the reliability can be improved. Further, it is possible to reduce the deviation of the gradation due to the DC imbalance, and it is possible to improve the image quality of the active matrix LCD.

[0113]

According to the first aspect of the present invention, the conversion signal according to the change of the video input signal is supplied to the common electrode of the transistor, and the DC imbalance of the pixel electrode connected to the common electrode is extremely small. Therefore, the DC imbalance applied to the entire active matrix LCD can be made extremely small. As a result, deterioration of the active matrix LCD can be suppressed and reliability can be improved. Further, it is possible to reduce the deviation of the gradation due to the DC imbalance, and it is possible to improve the image quality of the active matrix LCD.

According to the invention described in claims 2 to 6, the conversion signal for canceling the DC component generated in the pixel electrode according to the change of the video input signal can be supplied to the common electrode of the transistor, and the conversion signal of the pixel electrode can be supplied. The DC imbalance can be made extremely small, and the DC imbalance applied to the entire active matrix LCD can be made extremely small.

According to the seventh aspect of the present invention, the converted signal according to the change of the video input signal can be superimposed on the DC voltage and applied to the pixel electrode connected to the common electrode. Balance can be removed.

According to the eighth aspect of the present invention, the integrated signal according to the change of the video input signal can be applied to the pixel electrode connected to the common electrode by adding and subtracting and superposing the common voltage. The DC imbalance of the electrodes can be eliminated.

According to the ninth and tenth aspects of the present invention, the integrated signal according to the change of the video input signal in the odd field and the even field is added and superimposed or subtracted and superimposed on the common voltage, and is connected to the common electrode. It can be applied to the pixel electrode and DC imbalance of the pixel electrode can be removed.

According to the eleventh aspect of the present invention, the adder circuit can use an operational amplifier, and the adder circuit can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of one pixel of an active matrix LCD according to a first embodiment of the present invention.

FIG. 2 is a video signal V that changes into a binary value on a signal line 2 in FIG.
The figure which shows the waveform of each part in a circuit when IDA is applied, and the relationship of correction voltage c, c '.

FIG. 3 is a video signal V that changes into a binary value on a signal line 2 in FIG.
Waveform and correction voltage e of each part in the circuit when IDA is applied
FIG.

4 is a video signal V that changes into multiple values on a signal line 2 in FIG.
The figure which shows the relationship between the waveform of each part in a circuit when IDB is applied, and correction voltage e '.

FIG. 5 is a diagram showing a circuit configuration of voltage adjusting means connected to an NMOS TFT for one pixel of an active matrix LCD according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of voltage adjusting means connected to a PMOS type TFT for one pixel of an active matrix LCD according to a second embodiment of the present invention.

7 is a diagram showing respective waveform patterns of a correction voltage e superimposed on the DC voltage Vc by an integrating circuit, a triangular wave generating circuit or a rectangular wave generating circuit and the adder 13 of FIG.

8 is a diagram showing a waveform pattern of a correction voltage e superimposed on a DC voltage Vc by an adder 13 of FIG. 1 with an integrating circuit, a sawtooth wave generating circuit, a rectangular wave generating circuit or a triangular wave generating circuit.

FIG. 9 is a diagram showing a circuit configuration for one pixel of an active matrix LCD according to a third embodiment of the present invention.

10 is a diagram showing the relationship of waveforms at various parts in the circuit when a multi-valued source signal is applied to the signal line 2 of FIG.

FIG. 11 is a diagram showing the relationship of waveforms at various parts in the circuit when another source signal that changes into multiple values is applied to the signal line 2 in FIG. 9;

FIG. 12 is a PMOS-type TFT for one pixel of an active matrix LCD according to a fourth embodiment of the present invention.
FIG. 3 is a diagram showing a circuit configuration of a voltage adjusting means connected to the.

FIG. 13 is a diagram showing a circuit configuration for one pixel of an active matrix LCD according to a fifth embodiment of the present invention.

14 is a diagram showing a detailed configuration in the voltage adjusting means 50 of FIG.

FIG. 15 is a diagram showing the relationship between waveforms of various parts in the circuit when a source signal that changes into multiple values is applied to the signal line 2 of FIG. 13;

16 is a diagram showing the relationship of waveforms at various parts in the circuit when another source signal that changes into multiple values is applied to the signal line 2 in FIG.

FIG. 17 is a diagram showing a circuit configuration of one pixel of an active matrix LCD of a sixth embodiment to which the invention is applied.

FIG. 18 is a diagram showing a detailed configuration in the voltage adjusting means 60 of FIG.

FIG. 19 is a diagram showing the relationship of waveforms in various parts of the circuit when a source signal that changes into multiple values is applied to the signal line 2 in FIG. 17;

20 is a diagram showing the relationship of waveforms at various parts in the circuit when another source signal that changes into multiple values is applied to the signal line 2 in FIG.

FIG. 21 is a diagram showing a circuit configuration of one pixel of a conventional active matrix LCD.

22 is a diagram showing waveforms at various parts in the circuit when a binary video signal VIDA is applied to the signal line 2 in FIG. 21.

23 is a diagram showing waveforms at various parts in the circuit when a multivalued video signal VIDB is applied to the signal line 2 in FIG. 21.

[Explanation of symbols]

 1 Scanning Line 2 Signal Line 3 TFT 4 Pixel Electrode 5 Auxiliary Capacitance 6, 7 DC Power Supply 8 Scanning Signal 9 Video Signal 10, 30, 40, 50, 60 Voltage Adjusting Means 11 Data Signal Adjusting Circuit 11a Odd Field Video Sync Signal Phase Inversion Circuit 11b Even field video signal synchronization circuit 12, 51, 61 Low pass filter 13, 52, 62 Adder 21a Odd field video signal synchronization circuit 21b Even field video synchronization signal phase inversion circuit 51a, 51b Integrator 51c, 61c Subtractor 61d A -D converter 61e DAC 100 Drain driver 300 Analog video signal 301 1Hor1F delay circuit 302 1Hor1F integration circuit 303 Adder circuit 304 Subtractor circuit 305 Selector 306 Alternating circuit 400 Digital video signal 401 1Hor1F storage circuit 40 AC control circuit 403, 405 DAC 404 integrator 406 amplifier

Claims (11)

[Claims] 1. A plurality of signal lines and a plurality of scanning lines are arranged in a matrix, and a transistor is connected to an electrode on one side of a pixel at each intersection of these signal lines and the scanning lines, and the other pixel is common. A common voltage is supplied to the electrodes to scan each scanning line at a scanning timing according to a video input signal, and a video input signal input to each signal line is supplied with a positive voltage and a negative voltage with respect to the common voltage. In a method of driving an active matrix LCD, in which image signals are accumulated and displayed on each pixel electrode by alternating-currently driving each transistor while inverting the polarity of a video signal alternately at a predetermined cycle, the signal is input to each signal line. According to the magnitude of the voltage change of the video input signal or the amount of the signal amount, the pole side having a larger effective value voltage of the image input signal with respect to the common voltage is reduced by a predetermined amount to reduce the effective value voltage. The small pole side has a voltage adjusting means for increasing a predetermined amount to generate a conversion signal adjusted so that the positive RMS voltage and the negative RMS voltage are equal, and the conversion signal is provided to the common electrode of the pixel. A method of driving an active matrix LCD, comprising: 2. The voltage adjusting means phase-inverts a video input signal of either an odd field or an even field, and each of the video input signals of the other fields in the same frame as the phase-inverted video input signal. 2. The method of driving an active matrix LCD according to claim 1, wherein the voltage is integrated by using an integrating circuit and is supplied to the common electrode of the transistor. 3. The method for driving an active matrix LCD according to claim 1, wherein the voltage adjusting means supplies a low frequency component of the video input signal to a common electrode of the transistor by using a low pass filter. 4. The active element according to claim 1, wherein the voltage adjusting means supplies a rectangular wave signal corresponding to a change in the video input signal to a common electrode of the transistor by using a rectangular wave generating circuit. Matrix LCD driving method. 5. The active matrix LCD according to claim 1, wherein the voltage adjusting means supplies a triangular wave signal corresponding to a change in the video input signal to a common electrode of the transistor by using a triangular wave generating circuit. Driving method. 6. The active element according to claim 1, wherein the voltage adjusting means supplies a sawtooth wave signal corresponding to a change in the video input signal to a common electrode of the transistor by using a sawtooth wave generation circuit. Matrix LCD driving method. 7. The active element according to claim 1, wherein the voltage adjusting means superimposes the converted signal and a predetermined voltage by using an adder circuit and supplies the superposed signal to a common electrode of the transistor. Matrix LCD driving method. 8. The voltage adjusting means uses an integrating circuit to generate an integrated signal according to a change in the video input signal, and the integrated voltage is integrated with the common voltage according to the magnitude of the integrated signal with respect to the common voltage. 2. The method for driving an active matrix LCD according to claim 1, wherein the signals are added and superimposed or subtracted and supplied to the common electrode of the transistors. 9. The voltage adjusting means uses an integrating circuit to generate respective integrated signals according to changes in the odd field and the even field of the video input signal, and to generate the integrated signal of the odd field and the even field. Find the difference signal,
2. The active matrix LCD according to claim 1, wherein the difference signal is added and superimposed or subtracted and superimposed on the common voltage according to the magnitude of the difference signal with respect to the common voltage and is supplied to the common electrode of the transistor. Driving method. 10. The voltage adjusting means uses an adder circuit to generate respective added signals in accordance with changes in the odd field and the even field of the video input signal, and to add the odd field added signal and the even field added signal. 2. The differential signal is obtained, and the differential signal is added and superimposed or subtracted and superimposed on the common voltage according to the magnitude of the differential signal with respect to the common voltage, and is supplied to the common electrode of the transistor. Active matrix L
How to drive a CD. 11. The method for driving an active matrix LCD according to claim 7, wherein the adder circuit uses an operational amplifier.