JPH08272681A - 命令レベルで再構成可能なキャッシュを有するマイクロプロセッサー - Google Patents

命令レベルで再構成可能なキャッシュを有するマイクロプロセッサー

Info

Publication number
JPH08272681A
JPH08272681A JP8017299A JP1729996A JPH08272681A JP H08272681 A JPH08272681 A JP H08272681A JP 8017299 A JP8017299 A JP 8017299A JP 1729996 A JP1729996 A JP 1729996A JP H08272681 A JPH08272681 A JP H08272681A
Authority
JP
Japan
Prior art keywords
cache
data
instruction
microprocessor
operand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8017299A
Other languages
English (en)
Japanese (ja)
Inventor
Vargade Argade Pramod
ヴァサント アーゲイド プラモッド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of JPH08272681A publication Critical patent/JPH08272681A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
JP8017299A 1995-02-03 1996-02-02 命令レベルで再構成可能なキャッシュを有するマイクロプロセッサー Pending JPH08272681A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38303795A 1995-02-03 1995-02-03
US383037 1995-02-03

Publications (1)

Publication Number Publication Date
JPH08272681A true JPH08272681A (ja) 1996-10-18

Family

ID=23511440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8017299A Pending JPH08272681A (ja) 1995-02-03 1996-02-02 命令レベルで再構成可能なキャッシュを有するマイクロプロセッサー

Country Status (3)

Country Link
JP (1) JPH08272681A (https=)
KR (1) KR960032182A (https=)
TW (1) TW297111B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002025447A3 (en) * 2000-09-22 2002-11-28 Intel Corp Cache dynamically configured for simultaneous accesses by multiple computing engines

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002025447A3 (en) * 2000-09-22 2002-11-28 Intel Corp Cache dynamically configured for simultaneous accesses by multiple computing engines
GB2383868A (en) * 2000-09-22 2003-07-09 Intel Corp Cache dynamically configured for simultaneous accesses by multiple computing engines
US6665775B1 (en) 2000-09-22 2003-12-16 Intel Corporation Cache dynamically configured for simultaneous accesses by multiple computing engines
GB2383868B (en) * 2000-09-22 2005-02-02 Intel Corp Cache dynamically configured for simultaneous accesses by multiple computing engines

Also Published As

Publication number Publication date
TW297111B (https=) 1997-02-01
KR960032182A (ko) 1996-09-17

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